CN114610392A

CN114610392A - Instruction processing method, system, equipment and medium

Info

Publication number: CN114610392A
Application number: CN202210303130.7A
Authority: CN
Inventors: 王贤坤; 邹晓峰; 刘同强; 周玉龙; 张贞雷
Original assignee: Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Current assignee: Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Priority date: 2022-03-25
Filing date: 2022-03-25
Publication date: 2022-06-10

Abstract

The invention discloses an instruction processing method, which comprises the following steps: in response to the acquisition of the memory access instruction to be executed, sending the memory access instruction to be executed to a corresponding execution unit according to a preset field in the memory access instruction to be executed; responding to the corresponding execution unit receiving the access instruction to be executed, and preprocessing according to the access instruction to be executed; responding to the completion of the preprocessing, and judging whether a handshake signal sent by the control module is received; and responding to the received handshake signals, occupying the bus to carry out data access according to the to-be-executed access instruction. The invention also discloses a system, a computer device and a readable storage medium. The scheme provided by the invention can optimize the instruction space, reduce the scheduling logic, improve the memory access speed of the memory, increase the flexibility of instruction execution and reduce the hardware complexity.

Description

Instruction processing method, system, equipment and medium

Technical Field

The present invention relates to the field of processors, and in particular, to a method, system, device, and storage medium for processing instructions.

Background

RISC-V (open Instruction Set Architecture (ISA) based on Reduced Instruction Set Computing (RISC) principle, V represents RISC of the fifth generation), it is the whole new instruction set that is established on the basis of the continuous development and maturity of the order, have possessed and sent after the advantage, the structure is clear and simple, the modular design can be collocated at will as required, it is nimble convenient, the expandability is strong, possess complete tool chain, and because the openness of its BSD agreement, more and more countries and enterprises put into the research in RISC-V field.

Like other RISC architectures, RISC-V architectures use a dedicated Memory read (Load) write (Store) instruction access Memory (Memory), while other common instructions do not have access to Memory, the use of this strategy makes the hardware design of the processor relatively simple. However, the RISC-V processor does not support a continuous memory access in a self-increment or self-decrement mode, and although the complexity of hardware design is reduced, for a high-performance superscalar processor, a complex dynamic hardware scheduling function needs to be used to improve the performance; on the other hand, currently, a Vector (Vector) processing commonly used relates to a large amount of data interaction and calculation, the requirement on data quick access and processing is high, and a Vector extension instruction set is provided for the RISC-V, wherein the Vector access instruction is included, and the instruction set can be opened and closed in a modularization customized manner. The compatible realization of vector access and common access instructions to finish data access and memory processing with higher efficiency is a difficulty for realizing the prior RISC-V processor.

The access of RISC-V general data can only be carried out by integer access instruction, and the self-increasing and self-decreasing continuous data access is not supported for the conciseness of hardware design. The requirement of vector operation causes that RISC-V needs to expand vector access and storage instructions, and the characteristic of the RISC-V modularized instruction set causes that the vector access and storage instructions are forbidden along with configuration and are not suitable for other execution units. How to accomplish the compatible realization of vector access and common access instructions, and realize the continuous memory access function of general data without increasing the hardware complexity so as to obtain higher data access efficiency is an urgent problem to be solved.

Disclosure of Invention

In view of the above, in order to overcome at least one aspect of the above problems, an embodiment of the present invention provides an instruction processing method, including:

in response to the acquisition of the memory access instruction to be executed, sending the memory access instruction to be executed to a corresponding execution unit according to a preset field in the memory access instruction to be executed;

responding to the corresponding execution unit receiving the access instruction to be executed, and preprocessing according to the access instruction to be executed;

responding to the completion of the preprocessing, and judging whether a handshake signal sent by the control module is received;

and responding to the received handshake signals, occupying the bus to carry out data access according to the to-be-executed access instruction.

In some embodiments, sending the to-be-executed memory access instruction to a corresponding execution unit according to a preset field in the to-be-executed memory access instruction, further includes:

responding to the memory access instruction to be executed as a first type memory access instruction, and sending the memory access instruction to be executed to a first instruction execution unit;

and responding to the memory access instruction to be executed as a second type memory access instruction, and sending the memory access instruction to be executed to a second instruction execution unit.

In some embodiments, further comprising:

and in response to the control module detecting that the first instruction execution unit and/or the second instruction execution unit are/is in a non-idle state, sending a signal to an instruction transmitting module to stop sending the to-be-executed access instruction to the first instruction execution unit and/or the second instruction execution unit.

In some embodiments, in response to that the to-be-executed memory access instruction is a second type memory access instruction, sending the to-be-executed memory access instruction to a second instruction execution unit, further including:

setting a register group;

and caching the data to be accessed and stored by utilizing the register group.

Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides an instruction processing system, including:

the sending module is configured to respond to the acquisition of the memory access instruction to be executed and send the memory access instruction to be executed to a corresponding execution unit according to a preset field in the memory access instruction to be executed;

the preprocessing module is configured to respond to the corresponding execution unit receiving the memory access instruction to be executed and carry out preprocessing according to the memory access instruction to be executed;

the judging module is configured to respond to the completion of the preprocessing and judge whether a handshake signal sent by the control module is received;

and the memory access module is configured to respond to the received handshake signal and occupy the bus to access data according to the memory access instruction to be executed.

In some embodiments, the transmitting module is further configured to:

setting a register group;

and caching the data to be accessed and stored by utilizing the register group.

Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a computer apparatus, including:

at least one processor; and

a memory storing a computer program operable on the processor, wherein the processor executes the program to perform any of the steps of the instruction processing method as described above.

Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a computer-readable storage medium storing a computer program which, when executed by a processor, performs the steps of any of the instruction processing methods described above.

The invention has one of the following beneficial technical effects: the scheme provided by the invention can optimize the instruction space, reduce the scheduling logic, improve the memory access speed of the memory, increase the flexibility of instruction execution and reduce the hardware complexity.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.

FIG. 1 is a flowchart illustrating an instruction processing method according to an embodiment of the present invention;

FIG. 2 is a block diagram of an instruction pipeline architecture for a processor according to an embodiment of the present invention;

FIG. 3 is a block diagram of an instruction processing system according to an embodiment of the present invention;

FIG. 4 is a schematic structural diagram of a computer device provided in an embodiment of the present invention;

fig. 5 is a schematic structural diagram of a computer-readable storage medium according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.

It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.

According to an aspect of the present invention, an embodiment of the present invention provides an instruction processing method, as shown in fig. 1, which may include the steps of:

s1, responding to the acquired memory access instruction to be executed, and sending the memory access instruction to be executed to a corresponding execution unit according to a preset field in the memory access instruction to be executed;

s2, responding to the corresponding execution unit receiving the access instruction to be executed, and preprocessing according to the access instruction to be executed;

s3, responding to the completion of the preprocessing, judging whether a handshake signal sent by the control module is received;

and S4, responding to the received handshake signals, occupying the bus to access data according to the to-be-executed access instruction.

The proposal provided by the invention is to design and add an independent memory continuous data access instruction execution unit in an instruction pipeline, the execution unit can compatibly execute the execution of a vector extended access instruction and an integer continuous access instruction (self-defined extended instruction added by a modified optimization compiler), and is mutually independent with a general integer access instruction (Load/Store) execution unit, under the regulation and control of an access control module, the parallelism of the access instruction can be increased to the maximum extent, so that the access speed of the memory is improved, and the execution efficiency of the processor is improved. Therefore, the instruction space can be optimized, the scheduling logic is reduced, the memory access speed of the memory is improved, the flexibility of instruction execution is improved, and the hardware complexity is reduced.

In some embodiments, as shown in fig. 2, based on the research of RISC-V processor, an extended instruction suitable for memory continuous data access is designed and added according to the characteristics of vector access instruction. A memory continuous data access instruction execution unit is designed in an instruction production line, vector access instructions and self-defined memory continuous access instructions can be executed compatibly, the memory continuous data access instruction execution unit is relatively independent of an integer access instruction execution unit based on RISC-V, and according to the characteristic that two execution units access a memory, the memory access control module is used for regulating and controlling, so that the parallelism and the continuity of data access are increased to the greatest extent, the data access speed can be improved, and the execution efficiency of a processor is further improved.

In some embodiments, further comprising:

Specifically, when the instruction is actually executed, after Instruction Fetching (IF) and decoding (ID), and after decorrelation is performed by a register in a transmission (Issue) stage, the instruction is transmitted to a corresponding instruction execution unit for execution, and meanwhile, instruction information is cached in Scoreboard for unified instruction tracking management. At the moment, as long as a continuous data access instruction execution unit (DLSU) and a RISC-V general integer access instruction execution unit (LSU) are idle, the Issue module does not stop the transmission of the two types of access instructions, and the access conflict control is put into an access control module (LSCtrl). The DLSU execution unit has relatively large data volume aiming at the access and storage of continuous data, and data can not be exchanged frequently. Therefore, the method is designed to directly connect the L2Cache to complete data interaction through the bus without passing through the L1Cache, and only the write addresses of continuous write instructions need to be returned to the L1Cache to update the state during communication, so that continuous read instructions are not influenced. By the method, on one hand, frequent refreshing of large data volume to data in the L1Cache can be omitted, and the hit rate of the general memory access instruction is improved; on the other hand, when the access instruction executes conflict, the access parallelism can be improved to a certain extent: and when the access instructions do not conflict, the DLSU module and the LSU module respectively execute the instructions normally. When the access instruction executes conflict, the address calculation process in the DLSU, the virtual address conversion process in the LSU and the L1Cache hit query process can be performed in parallel, then the LSCtrl module regulates and controls, if the LSU occupies the bus before, the DLSU executes to prepare for bus occupation and suspends waiting; if the DLSU occupies the bus before, the LSU does not influence the continuous execution of the Load instruction when the Load instruction is hit; on miss, suspend waiting; when executing the Store instruction, the data can be directly written into the L1Cache, and the data is updated to a subsequent stage when the bus is idle, so that the execution of the Store instruction is not influenced.

setting a register group;

and caching the data to be accessed and stored by utilizing the register group.

Specifically, firstly, a continuous data access instruction (DLOAD/DSTORE, which is designed according to a RISC-V architecture reservation or a predefined coding space, and a specific format is not described in detail) may be added, and information such as a start address, an access length, a data bit width, and the like of the access memory may be acquired from the general register. A register set DR (or small FIFO/RAM) is set for data storage of consecutive access instructions to be read out of or written into the memory. By modifying and optimizing the compiler, portions of the code in the application code relating to contiguous data accesses can be compiled into the instruction dependent, optimizing the instruction space.

And secondly, designing a DLSU execution unit compatible with continuous data access and vector access instructions. Because the memory access is designed for continuous data access, the information such as the access address, the access length, the access data bit width, the AXI data bus bit width and the like of an AXI bus can be calculated and output through an addrGen module according to the preset information such as the access starting address, the access length, the access data bit width and the like of the AXI bus, the information such as the access address, the access length and the like of an AW channel or an AR channel of the AXI bus is received/output through a DLDU/DSTU module, and the access of memory data is completed (the specific AXI bus address and data interaction process is not detailed here). When a continuous data access instruction is executed, the register set DR is similar to a general register which can store a group of data; when a vector access instruction is executed, a register group DR is a decoupling module between a DLSU unit and a vector register group, other access execution units are not required to be realized in a vector extension instruction execution unit, the DLSU can be shared, and data interaction with the vector register is realized through DR decoupling according to instruction information executed by the DLSU. That is, when data needs to be read, data may be put into the DR from the DDR and then fed back from the DR, and when data needs to be stored, data to be stored may be put into the DR and then written into the DDR from the DR.

Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides an instruction processing system 400, as shown in fig. 3, including:

the sending module 401 is configured to send, in response to an access instruction to be executed being obtained, the access instruction to be executed to a corresponding execution unit according to a preset field in the access instruction to be executed;

the preprocessing module 402 is configured to respond to the corresponding execution unit receiving the to-be-executed memory access instruction, and perform preprocessing according to the to-be-executed memory access instruction;

a judging module 403, configured to, in response to the preprocessing completion, judge whether a handshake signal sent by the control module is received;

and the memory access module 404 is configured to, in response to receiving the handshake signal, occupy the bus to perform memory access of data according to the memory access instruction to be executed.

In some embodiments, the sending module 401 is further configured to:

setting a register group;

and caching the data to be accessed and stored by utilizing the register group.

Based on the same inventive concept, according to another aspect of the present invention, as shown in fig. 4, an embodiment of the present invention further provides a computer apparatus 501, including:

at least one processor 520; and

the memory 510, the memory 510 stores a computer program 511 that is executable on the processor, and the processor 520 executes the computer program to perform the steps of any of the instruction processing methods described above.

Based on the same inventive concept, according to another aspect of the present invention, as shown in fig. 5, an embodiment of the present invention further provides a computer-readable storage medium 601, where the computer-readable storage medium 601 stores computer program instructions 610, and the computer program instructions 610, when executed by a processor, perform the steps of any one of the instruction processing methods as above.

Finally, it should be noted that, as will be understood by those skilled in the art, all or part of the processes of the methods of the above embodiments may be implemented by a computer program, which may be stored in a computer-readable storage medium, and when executed, may include the processes of the embodiments of the methods described above.

Further, it should be appreciated that the computer-readable storage media (e.g., memory) herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory.

Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.

The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.

It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.

The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.

It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.

Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.

Claims

1. An instruction processing method, comprising the steps of:

2. The method of claim 1, wherein the to-be-executed memory access instruction is sent to a corresponding execution unit according to a preset field in the to-be-executed memory access instruction, and further comprising:

3. The method of claim 2, further comprising:

4. The method of claim 2, wherein in response to the to-be-executed memory access instruction being a second type of memory access instruction, sending the to-be-executed memory access instruction to a second instruction execution unit, further comprising:

setting a register group;

and caching the data to be accessed and stored by utilizing the register group.

5. An instruction processing system, comprising:

6. The system of claim 5, wherein the transmit module is further configured to:

7. The system of claim 6, wherein the transmit module is further configured to:

and responding to the control module detecting that the first instruction execution unit and/or the second instruction execution unit are/is in a non-idle state, sending a signal to an instruction transmitting module to stop sending the memory access instruction to be executed to the first instruction execution unit and/or the second instruction execution unit.

8. The system of claim 6, wherein the transmit module is further configured to:

setting a register group;

and caching the data to be accessed and stored by utilizing the register group.

9. A computer device, comprising:

at least one processor; and

memory storing a computer program operable on the processor, characterized in that the processor, when executing the program, performs the steps of the method according to any of claims 1-4.

10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, is adapted to carry out the steps of the method according to any one of claims 1-4.