CN114610269A

CN114610269A - Method, system equipment and medium for generating finite field multiplication circuit

Info

Publication number: CN114610269A
Application number: CN202210316454.4A
Authority: CN
Inventors: 赵璠; 王明明; 马孔明
Original assignee: Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Current assignee: Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Priority date: 2022-03-29
Filing date: 2022-03-29
Publication date: 2022-06-10

Abstract

The invention provides a method for generating a finite field multiplication circuit, which comprises the following steps: determining the data length of the data participating in the multiplication operation, and determining a primitive polynomial according to the data length; multiplying the data in a finite field to obtain a multiplication matrix table, generating an intermediate polynomial according to a product term in the multiplication matrix table, and generating a data expander circuit according to the product relation of each term in the intermediate polynomial; and generating a primitive polynomial remainder circuit according to the primitive polynomial and the intermediate polynomial, and correspondingly connecting the data expander circuit and the primitive polynomial remainder circuit. Compared with the common lookup table mode, the method for generating the finite field multiplication circuit can omit the lookup table of a positive and negative table and the corresponding logical addition operation each time of multiplication by analyzing the finite field multiplication operation, and the operation is developed by hardware in one step to realize the operation, so that the speed is improved by certain area loss.

Description

Method, system equipment and medium for generating finite field multiplication circuit

Technical Field

The invention belongs to the field of computer storage, and particularly relates to a method, a system, equipment and a medium for generating a finite field multiplication circuit.

Background

In the field of computer storage, data often needs to use some coding algorithms to protect or encrypt and decrypt data in storage and transmission, and these algorithms are often completed by awaking extra redundancy in practical implementation, and some contents related to an elliptic encryption algorithm are simply to ensure that the selection of coefficients of a construction equation in encryption is a common way to use values of a vandermonde matrix as the coefficients, and according to the characteristics of the vandermonde matrix. To have a solution to the equation and a unique solution, it is necessary to ensure that the values of the vandermonde coefficients are all different. To this end, we have obtained a standard: and constructing Van der Waals matrixes with different elements as coefficients, and then carrying out encryption and decryption or coding and decoding on the obtained equations to protect the data to be stored.

In practice, the above method operates directly, and almost inevitably encounters a problem of overflow of the calculation data. The problem of operation data overflow is inevitable when real number domain operation is directly applied to computer processing data, which involves the processing of matrix multiplication required in actual operation. At this time, people aim at a number field-finite field which can not generate operation data overflow. The whole process of operation is put in a finite field, so the overflow problem naturally does not exist. And just these operation processes only relate to four fundamental operations, and are very suitable for processing in a limited domain. In addition, since the operation rule in the finite field is simpler than that of some other fields such as a real number field, the finite field is very suitable for data operation and processing, the finite field does not have the problem of operation overflow, and the data of the operation and the obtained result are both in the finite field, so that the number of bits represented by a computer can be fixed, and the data bits are not expanded or reduced. In a specific implementation, the adopted finite field GF (2^ n) is common.

When the data is calculated by using the finite field, that is, most of the conventional finite field processing methods are realized by software, and the software is mainly realized by a table look-up mode. Although finite field multiplication has some tricks to improve the efficiency of the operation, the resource consumption of the operation is too large for the operation of a large amount of data.

Therefore, a hardware implementation without table lookup is needed.

Disclosure of Invention

To solve the above problem, the present invention provides a method for generating a finite field multiplication circuit, comprising:

determining the data length of the data participating in the multiplication operation, and determining a primitive polynomial according to the data length;

multiplying the data in a finite field to obtain a multiplication matrix table, generating an intermediate polynomial according to a product term in the multiplication matrix table, and generating a data expander circuit according to the product relation of each term in the intermediate polynomial;

and generating a primitive polynomial remainder circuit according to the primitive polynomial and the intermediate polynomial, and correspondingly connecting the data expander circuit and the primitive polynomial remainder circuit.

In some embodiments of the present invention, multiplying the data in a finite field to obtain a multiplication matrix table, and generating an intermediate polynomial from a product term in the multiplication matrix table comprises:

multiplying the data according to the data length by bit to obtain a multiplication matrix;

carrying out dislocation addition on the multiplication matrix according to a multiplication carry relation to obtain a plurality of polynomials;

merging the plurality of polynomials as each term of the intermediate polynomial into an intermediate polynomial.

In some embodiments of the invention, the method further comprises:

and connecting each item of data in the plurality of polynomials through an exclusive-OR gate logic according to the sequence to generate the expander circuit.

In some embodiments of the invention, the method of generating a primitive polynomial remainder circuit from the primitive polynomial and the intermediate polynomial comprises:

and dividing each term polynomial in the intermediate polynomial by the primitive polynomial according to a finite field calculation principle to perform a remainder operation, and sequentially passing each term data in the polynomial after the remainder operation through an exclusive-or gate logic to generate a primitive polynomial remainder circuit.

In some embodiments of the invention, multiplying the data in a finite field to obtain a multiplication matrix table comprises:

multiplying the data according to the reverse order to obtain a multiplication matrix;

In some embodiments of the invention, the method further comprises:

and determining the data length of the data participating in the multiplication operation according to the available circuit area of the hardware circuit on the actual chip.

In some embodiments of the invention, the method further comprises:

and selecting a primitive polynomial according to the circuit area to generate the primitive polynomial remainder circuit.

Another aspect of the present invention further provides a system for generating a finite field multiplication circuit, comprising:

the initialization data module is configured to determine the data length of data participating in multiplication, and determine the length of a primitive polynomial and the primitive polynomial according to the data length;

the data expander circuit generating module is configured to multiply the data in a finite field to obtain a multiplication matrix table, generate an intermediate polynomial according to a product term in the multiplication matrix table, and generate a data expander circuit according to a product relation of each term in the intermediate polynomial;

and the residual circuit generating module is configured to generate a primitive polynomial residual circuit according to the primitive polynomial and the intermediate polynomial and correspondingly connect the data expander circuit and the primitive polynomial residual circuit.

Yet another aspect of the present invention also provides a computer apparatus, including:

at least one processor; and

a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of the method of any one of the above embodiments.

Yet another aspect of the present invention further provides a computer-readable storage medium, which stores a computer program, and the computer program realizes the steps of the method of any one of the above embodiments when executed by a processor.

The method for generating the finite field multiplication circuit provided by the invention is realized by analyzing finite field multiplication operation, aiming at the concept of Galois field polynomial and realizing the quick scheme of Galois field multiplication through hardware, compared with the common lookup table mode, the lookup table of a positive and negative table and the corresponding logical addition operation can be omitted in each multiplication operation, and the operation is expanded by hardware in one step to realize the operation, so that the speed is improved through certain area loss. The method supports different primitive polynomial configurations, and the principle can be expanded to finite field operation of GF (2^ m) with more bit widths without table lookup and firmware support, so that the cost of software development is reduced.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a flowchart of a method for generating a finite field multiplication circuit according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a system for generating a finite field multiplication circuit according to an embodiment of the present invention.

FIG. 3 is a schematic structural diagram of a computer device according to an embodiment of the present invention;

FIG. 4 is a schematic structural diagram of a computer-readable storage medium according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a misalignment of a multiplication matrix for generating finite field multiplication according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of an expansion circuit for generating finite field multiplication data according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of generating a finite field multiplication polynomial remainder according to an embodiment of the present invention;

fig. 8 is a schematic diagram of a generate finite field multiply-and-remainder circuit according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.

As shown in fig. 1, the present invention provides a method for generating a finite field multiplication circuit, including:

step S1, determining the data length of the data participating in the multiplication operation, and determining a primitive polynomial according to the data length;

step S2, multiplying the data in the finite field to obtain a multiplication matrix table, generating an intermediate polynomial according to the product term in the multiplication matrix table, and generating a data expander circuit according to the product relation of each term in the intermediate polynomial;

and step S3, generating a primitive polynomial remainder circuit according to the primitive polynomial and the intermediate polynomial, and correspondingly connecting the data expander circuit and the primitive polynomial remainder circuit.

In some embodiments of the invention, the method further comprises:

and selecting a primitive polynomial according to the circuit area to generate the primitive polynomial complementation circuit.

In the embodiment of the present invention, the data to be multiplied is the bit width of the input data of the multiplication circuit, usually expressed in binary, and is the bit number of two data to be multiplied, for example, the multiplication circuit that multiplies two 8-bit data in a finite field, and the input data is understood to be 8 data lines each, and 16 data lines in total are input to the multiplication circuit. The data length may be an exponential number of 2, such as 16 bits, 32 bits, etc., as desired.

Further, after the length of the data is determined, a matrix table for multiplying the data is listed according to each bit of the data according to the length of the data in a finite field calculation mode, and the specific implementation mode of hardware is to expand the value of each bit of a multiplicand according to the value of each bit of the multiplicand. Taking the example of 8-bit data multiplication, the input a ═ a7a6a5a4a3a2a1a 0; input B ═ B7B6B5B4B3B2B1B 0; then a × B ═ (a7a6a5a4a3a2a1a0) (B7B6B5B4B3B2B1B 0). a7-a0 represents the 8 th bit to 1 st bit of the input data A, and B7-B0 represents the 8 th bit to 1 st bit of the input data B. A matrix of 64 multiplied numbers can be obtained:

[a7b7,a6b7,a5b7,a4b7,a3b7,a2b7,a1b7,a0b7,a7b6,a6b6...a7b1,a6b1,a5b1,a4b1,a3b1,a2b1,a1b1,a0b1,a7b0,a6b0,a5b0,a4b0,a3b0,a2b0,a1b0,a0b0]＝[A*[b7],A*[b6],A*[b5],A*[b4]A*[b3],A*[B2],A*[b1],A*[b0]]

further, according to the matrix table, the intermediate polynomial is obtained by performing offset addition on the multiplication result of the data bits according to the carry relation of the multiplication, and the offset addition is specifically as shown in fig. 5, that is, a plurality of polynomials are calculated according to the conventional calculation mode of multiplication-to-addition, and based on the characteristics of finite fields, carry is not required. Then, taking fig. 5 as an example, the first polynomial is a7b7, the second polynomial is a6b7+ a6b6, and the third polynomial is a5b7+ a6b6+ a7b5, i.e. adding them from bottom to top as 1 polynomial according to the dislocation matrix shown in fig. 5, and combining all the polynomials into an intermediate polynomial h (x) with 15 polynomials.

The resulting calculation result of the multiplication, i.e., the intermediate polynomial, is as follows:

H(x)＝h(14)X^14+h(13)X^13+h(12)X^12+h(11)X^11+h(10)X^10+h(9)X^9+h(8)X^8+h(7)X^7+h(6)X^6+h(5)X^5+h(4)X^4+h(3)X^3+h(2)X^2+h(1)X^1+h(0)。

h (x) represents the resulting intermediate polynomial, H (14) represents the highest order coefficient, i.e., the leftmost a7b7 shown in FIG. 5, H (13) represents a6b7+ a6b6, and x ^14 is the algebraic representation of the polynomial.

The resulting h [14:0] is the median of our operation, 15 bits, since one byte is 8 bits, the highest power expressed in the finite field is 7(0-7), so the highest power of the multiplication of the two numbers is 14.

Further, taking the calculated data bits in the polynomial in the h (x) coefficient as the input of the xor gate circuit, the corresponding data expander circuit is generated, specifically, as shown in fig. 6, in the first row of fig. 6, the coefficient of h (14) is A7B7 (written as A7B7 in the figure is the same in meaning), and h (14) has only one term, so that one xor gate logic is provided. By analogy, in the second row, for the circuit of h (13), as described above, the coefficient of h (13) is a6b7+ a6b6, and then a6b7 and a6b6 are used as inputs of an exclusive-or gate to perform an exclusive-or operation. Further, h (12) is calculated by a5b7 and a6b6 through an exclusive-or gate, and the result is exclusive-ored with a7b 5. And so on to generate a data expander circuit.

It should be noted that, because finite field calculation is adopted, the "+" in the polynomial is exclusive or logic in the finite field, and therefore exclusive or logic gates are adopted in the data expander circuits.

The input of the remainder extractor is the output result of the data expander, namely the intermediate calculation value, the intermediate calculation value obviously does not belong to the inward result of the finite field, the data representation in the finite field only has 8 bits, but the intermediate calculation value has 15 bits, and the remainder operation needs to be directly carried out on the primitive polynomial selected by people from the intermediate calculation obtained by the data expander to obtain the final operation result. In GF (2^8), 0x11D is generally selected as a primitive polynomial, which is a custom method, other suitable polynomials can be selected as the primitive polynomial, and the realization of the hardware only needs to be adjusted a little in specific operation.

Based on the operation characteristics of a finite field, the remainder operation of the intermediate value needs to be processed by combining the conditions of a polynomial and can be converted into the addition operation between the lower eight bits and the upper seven bits of the intermediate value for processing, and the mathematical principle is as follows:

first, there is a skill for calculating multiplication in multiplication operations in finite fields, which is also described in the book "cryptology and network security". For example, we select the primitive polynomial in the finite field as 0x11D, then the primitive polynomial m (x) x ^8+ x ^4+ x ^3+ x ^2+ 1;

firstly, x ^8 mod m (x) ═ m (x) -x ^8] ═ x ^4+ x ^3+ x ^2+1

From this equation, for the polynomial f (x), we can obtain:

f(x)＝b7x^7+b6x^6+b5x^5+b4x^4+b3x^3+b2x^2+b1x+b0；

x*f(x)＝(b7x^8+b6x^7+b5x^6+b4x^5+b3x^4+b2x^3+b1x^2+b0x)mod m(x)。

if b7 equals 0, then the result is a polynomial less than 8 and does not need to be modulo.

If b7 equals 1, then by the above result:

x*f(x)＝(b6x^7+b5x^6+b4x^5+b3x^4+b2x^3+b1x^2+b0x)+(x^4+x^3+x+1)；

for hardware implementation, it is easy to compute by bit exclusive or operation. For x with an exponent higher than once, it can be used in a recursive fashion. Such as: x 2 f (x) x f (x) x (x). The same applies to values x m f (x). However, for a given GF (2^8), only X ^14 needs to be calculated according to the result obtained by the above operation.

The above operation results in h (x) ^ h (14) x ^14+ h (13) x ^13+ h (12) x ^12+ h (11) x ^11+ h (10) x ^10+ h (9) x ^9+ h (8) x ^8+ h (7) x ^7+ h (6) x ^6+ h (5) x ^5+ h (4) x ^4+ h (3) x ^3+ h (2) x ^2+ h (1) x ^1+ h (0).

Let h (x) carry out the remainder operation on the selected m (x), that is, each term of h (x) polynomial adds to m (x) after taking the remainder.

Order: l (x) ^ h (7) x ^7+ h (6) x ^6+ h (5) x ^5+ h (4) x ^4+ h (3) x ^3+ h (3) x ^2+ h (1) x ^1+ h (0), can obtain:

h (x) ^ h (14) x ^14+ h (13) x ^13+ h (12) x ^12+ h (11) x ^11+ h (10) x ^10+ h (9) x ^9+ h (8) x ^8+ L (x), wherein the power of L (x) is up to 7, and the remainder operation result is the same as the remainder operation result. And the coefficients of x ^14, x ^13, x ^12, x ^11, x ^10, x ^9 and x ^8 are h (14), h (13), h (12), h (11), h (10), h (9) and h (8). The multiplication result of the last step and the coefficients can be obtained by calculation, and the processing of the step only needs to bring the result of taking the remainder of the corresponding polynomial into the primitive polynomial, namely the result is equal to the result of taking the remainder of the whole operation result on the primitive polynomial.

Therefore, in this step, polynomial expressions after the remainder of the primitive polynomial of x ^14, x ^13, x ^12, x ^11, x ^10, x ^9 and x ^8 need to be calculated in advance, and then all the obtained results are added up and added up with L (x) to obtain the corresponding operation results.

After the system selects the primitive polynomial, the polynomial expression of the high power is not fixed, taking m (x) x ^8+ x ^4+ x ^3+ x ^2+1 as an example, the following polynomial can be obtained:

L(x)＝x^7+x^6+x^5+x^4+x^3+x^2+x+1

X^8＝x*x^7＝x^8 mod m(x)＝x^4+x^3+x^2+1

X^9＝x*x^8＝x^5+x^4+x^3+x

X^10＝x*x^9＝x^6+x^5+x^4+x^2

X^11＝x*x^10＝x^7+x^6+x^5+x^3

X^12＝x*x^11＝x^8+x^7+x^6+x^4＝x^7+x^6+x^3+x^2+1

X^13＝x*x12＝x^8+x^7+x^4+x^3+x＝x^7+x^2+x+1

X^14＝x*x13＝x^8+x^3+x^2+x＝x^4+x+1

the blank term above can be regarded as a coefficient of 0, and the actual coefficients of other terms are obtained from the multiplication result of the first step, so that the remainder is obtained by adding the coefficients according to polynomial modulo operation, and the circuit structure is shown in fig. 8. Thus, the result of the operation is obtained.

Specifically, referring to the above formula or the equation list shown in fig. 7, the remainder circuit is generated by representing the corresponding bit coefficient to the right of the equal sign of the above modulo operation. The coefficient of x ^7 is h (7), the coefficient of x ^6 is h (6), the coefficient of x ^5 is h (5).. x ^0 (namely, 1) is h (0). According to the rule of the modular operation of the finite field, the circuit input and output relationship of the modular operation can be expressed as:

C[7]＝h(7)+h(11)+h(12)+h(13)；

C[6]＝h(6)+h(10)+h(11)+h(12)；

C[5]＝h(5)+h(9)+h(10)+h(11)；

C[4]＝h(4)+h(8)+h(9)+h(10)+h(14)；

C[3]＝h(3)+h(8)+h(10)+h(11)+h(12)；

C[2]＝h(2)+h(8)+h(10)+h(12)+h(13)；

C[1]＝h(1)+h(9)+h(13)+h(14)；

C[0]＝h(0)+h(8)+h(12)+h(13)+h(14)；

C7-C0 are obtained by adding the coefficients on the right side of the equation shown in FIG. 7 from top to bottom, the equal-sign right side is empty to indicate that the coefficients are 0, and h (7) of C7 represents the coefficient of x ^7 in the intermediate polynomial H (x), i.e., h (7), taking C7 as an example. h (11) is the result of taking the modulus of the first data which is not 0 and corresponds to the position below x ^7 as h (11), namely the first term of the polynomial obtained after the modulus operation of the 5 th row h (11) in the graph and the primitive polynomial is x ^ 7.

For ease of understanding, the generation of the above calculation (FIG. 7) can be understood as the addition of coefficients other than 0 from top to bottom for the data on the right side of the equal sign, x ^7 is not empty in the first row x ^7, and since L (x) represents the lower 8 bits of the intermediate polynomial, the coefficients are h (7) to h (0), respectively, so that the first term of C [7] is h (7), the second term is in row 5, row 5 is h (11) in the corresponding intermediate polynomial, the second term of C [7] is h (11), and so on, the third term is h (12), and the fourth term is h (13).

C7-C0 are the output results of the finite field multiplication of the present invention, i.e. 8 bits of result C is obtained by calculating 8 bits of input data A and 8 bits of input data B.

Since the finite field addition is realized by XOR logic, C7-C0 can also be realized by XOR logic gate of hardware circuit, and the data expander circuit in the above embodiment is combined, and the hardware realization circuit of finite field multiplication can be generated by using 15 outputs (h (14) -h (0)) of the data expander circuit as the input of the remainder circuit.

The above embodiment takes GF (2^8) as an example, and only simple xor operation needs to be performed on the calculation intermediate value according to different bit pairs in hardware implementation.

As for the adaptation to other primitive polynomials, there is only a little difference in the location of the xor operation of the residual block.

By judging the value of the externally configured primitive polynomial, the related operation weight factor is added in the operation, and different primitive polynomials correspond to different operation weight factors, so that the configuration of the remainder operation can be changed according to the configuration of the primitive polynomial, namely, the finite field multiplication operation under the condition of different primitive polynomials is adapted.

In some embodiments of the present invention, the input data of the data expansion circuit determines the size of the data expansion circuit, and in the above embodiments, the 8-bit input data is taken as an example for explanation, the deepest of the data expansion circuit needs to calculate 7 layers, and the deepest of the remainder circuit needs to calculate 5 layers. The calculation depth of the data expansion circuit and the remainder circuit and the size of the consumed chip area are determined by the length of the input data. Thus, in some embodiments, different lengths may be selected as the size of the input data as desired. Or a data expansion circuit and a remainder circuit which generate a plurality of groups of 8 bits are selected according to requirements.

In some embodiments of the invention, different primitive polynomials may also be selected as needed to generate corresponding remainder circuits. In the above embodiment, the primitive polynomial is m (x) ^8+ x ^4+ x ^3+ x ^2+1, different primitive polynomials generate different remainder circuits, and a proper primitive polynomial can be reasonably selected according to the available area of a hardware circuit in a chip to generate a corresponding remainder circuit.

As shown in fig. 2, another aspect of the present invention further provides a system for generating a finite field multiplication circuit, comprising:

the data processing method comprises an initialization data module 1, wherein the initialization data module 1 is configured to determine the data length of data participating in multiplication, and determine the length of a primitive polynomial and the primitive polynomial according to the data length;

a data expander circuit generating module 2, wherein the data expander circuit generating module 2 is configured to multiply the data in a finite field to obtain a multiplication matrix table, generate an intermediate polynomial according to a product term in the multiplication matrix table, and generate a data expander circuit according to a product relation of each term in the intermediate polynomial;

and a remainder circuit generating module 3, wherein the remainder circuit generating module 3 is configured to generate a primitive polynomial remainder circuit according to the primitive polynomial and the intermediate polynomial, and correspondingly connect the data expander circuit and the primitive polynomial remainder circuit.

As shown in fig. 3, another aspect of the present invention also provides a computer device, including:

at least one processor 21; and

a memory 22, the memory 22 storing computer instructions 23 executable on the processor 21, the instructions 23 when executed by the processor 21 implementing a method of generating a finite field multiplication circuit, comprising:

In some embodiments of the invention, the method further comprises:

As shown in fig. 4, a further aspect of the present invention also proposes a computer-readable storage medium 401, the computer-readable storage medium 401 storing a computer program 402, the computer program 402 implementing a method of generating a finite field multiplication circuit when being executed by a processor, comprising:

In some embodiments of the invention, the method further comprises:

The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.

It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.

The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.

It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, where the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.

Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of an embodiment of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.

Claims

1. A method of generating a finite field multiplication circuit, comprising:

2. The method of claim 1, wherein multiplying the data within a finite field results in a multiplication matrix table, and wherein generating an intermediate polynomial from product terms in the multiplication matrix table comprises:

3. The method of claim 2, further comprising:

4. The method of claim 1, wherein generating a primitive polynomial remainder circuit from the primitive polynomial and the intermediate polynomial comprises:

5. The method of claim 1, wherein multiplying the data in a finite field to obtain a multiplication matrix table comprises:

6. The method of claim 1, further comprising:

7. The method of claim 1, further comprising:

8. A system for generating a finite field multiplication circuit, comprising:

9. A computer device, comprising:

at least one processor; and

a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of the method of any one of claims 1 to 7.

10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 7.