CN114609495A

CN114609495A - Image test system, test element and image acquisition card

Info

Publication number: CN114609495A
Application number: CN202011329348.7A
Authority: CN
Inventors: 蔡秉谚; 郑光哲
Original assignee: King Yuan Electronics Co Ltd
Current assignee: King Yuan Electronics Co Ltd
Priority date: 2020-11-24
Filing date: 2020-11-24
Publication date: 2022-06-10

Abstract

The invention provides an image test system, which comprises a test element and an image acquisition card. The test element is used for obtaining a test signal of an object to be tested and comprises an interface conversion circuit which is used for converting a signal transmission form of the test signal. The image acquisition card is used for acquiring a test signal from the test element and acquiring image data from the test signal. The image test system also comprises a test signal clock pulse generating circuit used for obtaining the test signal clock pulse from the test signal, or the image obtaining card also comprises a pair of clock pulse input pins used for directly obtaining the test signal clock pulse from the object to be tested.

Description

Image test system, test element and image acquisition card

Technical Field

The present invention relates to a test system, a test device thereof and a data acquisition card thereof, and more particularly to an image test system, a test device thereof and an image acquisition card thereof.

Background

An image capture card associated with a semiconductor device testing apparatus generally has a logic processing unit, which can pre-decode an image signal obtained by an image capture device (e.g., a camera), and then transmit the decoded image signal to a rear-end image processing apparatus for processing. In order to meet the requirement of super high image quality, video signals are gradually transmitted in a C-type physical layer (hereinafter referred to as C-PHY) signal form instead of an original D-type physical layer (hereinafter referred to as D-PHY) signal form. The current D-PHY signal is transmitted in a differential manner and has clock data for the test system to perform timing correction of the image data; in contrast, the C-PHY signal is not transmitted differentially, and therefore, the C-PHY signal is applicable only to a shorter signal transmission path (compared to the D-PHY signal). In addition, the current C-PHY signal only has data information and does not have clock information for calibration.

Under the existing video test system architecture, the video capture card will capture the C-PHY signal through the test device (e.g. the prober), and then convert the C-PHY signal into a signal type readable by the logic processing unit in the video capture card through the data conversion unit. However, under the limitation of board layout (layout), there are cases where a long signal transmission path is provided between the prober and the data conversion unit, so that the C-PHY signal will be subjected to a lot of loss and delay due to the long path, and Jitter (Jitter) is often generated due to the signal timing offset, which affects the accuracy of the test system.

The present invention provides an improved image test system, test device and image acquisition card to solve the above problems.

Disclosure of Invention

An object of the present invention is to provide an image testing system, comprising: a test element and an image acquisition card. The test element is used for obtaining a test signal of an object to be tested and comprises an interface conversion circuit for converting a signal transmission form of the test signal; the image capture card obtains a test signal from the test element and obtains image data from the test signal. The image test system also comprises a test signal clock pulse generating circuit used for obtaining the test signal clock pulse from the test signal, or the image obtaining card also comprises a pair of clock pulse input pins used for directly obtaining the test signal clock pulse from the object to be tested.

Another objective of the present invention is to provide a test device disposed in an image test system including an image capture card, wherein the test device includes a first transmission interface, a test signal clock generating circuit, an interface converting circuit, and a second transmission interface. The first transmission interface is used for obtaining a test signal of the object to be tested; the test signal clock generating circuit is used for acquiring a test signal clock from the test signal and transmitting the test signal clock to the image acquisition card; the interface conversion circuit converts the signal transmission form of the test signal; the second transmission interface is used for transmitting the test signal to the image acquisition card.

Still another object of the present invention is to provide an image capture card disposed in an image testing system, wherein the image testing system includes a testing device for transmitting a testing signal to the image capture card, and the image capture card includes a testing signal clock generating circuit and a logic processing unit. The test signal clock generating circuit is used for acquiring a test signal clock from the test signal; the logic processing unit obtains image data from the test signal according to the test signal clock.

Drawings

FIG. 1 is a block diagram of an exemplary image testing system according to the present invention;

FIG. 2(A) is a detailed configuration diagram of a test device and an image capture card according to a first embodiment of the present invention;

FIG. 2(B) is a schematic diagram of a comparative test element and image capture card;

FIG. 3 is a detailed configuration diagram of a test device and an image capture card according to a second embodiment of the present invention;

FIG. 4 is a detailed configuration diagram of a testing device and an image capture card according to a third embodiment of the present invention;

FIG. 5 is a detailed configuration diagram of a test device and an image capture card according to a fourth embodiment of the present invention;

FIG. 6A is a circuit diagram of a test signal clock generating circuit according to an embodiment of the present invention;

FIG. 6(B) is a timing diagram of sub-signals of a test signal according to one embodiment of the present invention;

FIG. 7 is a detailed configuration diagram of a test device and an image capture card according to a fifth embodiment of the present invention;

FIG. 8 is a detailed configuration diagram of a test device and an image capture card according to a sixth embodiment of the present invention.

[ description of symbols ]

Image testing system 1

Test head 2

Test element 3

Image acquisition card 4

Test substance 7

Test signal S0

Image processing element 9

Probe card 32

Probe 33

Light source supply device 6a

First bridging plate 60

First transfer interface 34

Interface conversion circuit 36

Second transmission interface 38

Test signal clock generation circuit 80

Clock output pin 41a

Test signal clock CLK

Sub-signals S1, S2, S3

Differential sub-signals S11, S12, S21, S22, S31, S32, S41, S42

Probe card daughter board 35

Logic input interface 41

Logic processing unit 44

Transmission unit 46

Data conversion circuit 42

Clock generator 440

Preset clock clk0

First input 81

First clock acquisition module 82

Second input terminal 83

Second clock acquisition module 84

Third input 85

Third clock acquisition module 86

Circuit output 87

The first sub-signal clock clk _ s1

The second sub-signal clock clk _ s2

The third sub-signal clock clk _ s3

First buffer 821

First delay unit 822

First XOR gate 823

Second buffer 841

Second delay unit 842

Second exclusive OR gate 843

Third buffer 861

Third delay unit 862

Third XOR gate 863

First delayed sub-signal S1_ L

The second delayed sub-signal S2_ L

The third delayed sub-signal S3_ L

Period T1-T6

Signal transmission distances L1, L2.

Detailed Description

The following describes embodiments and operation principles of the image test system and the image acquisition card according to the present invention. Those skilled in the art can understand the features and effects of the present invention through the above embodiments, and can make combinations, modifications, substitutions or changes based on the spirit of the present invention.

The term "coupled" as used herein is intended to encompass both direct and indirect coupling, and is not intended to be limiting. The term "when …", "…" as used herein means "when, before or after", and is not intended to be limiting.

The use of ordinal numbers such as "first," "second," etc., herein to modify a requesting element is not by itself intended to imply any preceding order to the requesting element, nor the order in which a requesting element is sequenced or in which it is sequenced or otherwise processed, but rather the use of ordinal numbers is merely used to distinguish one requesting element having a certain name from another requesting element having a same name.

Fig. 1 is a schematic diagram of a basic architecture of an image testing system 1 according to an embodiment of the present invention. As shown in fig. 1, the image testing system 1 includes a testing head 2, a testing device 3 and an image acquisition card 4, wherein the testing device 3 can be used to contact an object 7 to be tested, wherein the object 7 can be a wafer or other semiconductor device requiring electrical testing. The test head 2 can provide a test program for electrical test to the test device 3. The test device 3 obtains a test signal S0 from the object 7. The Image obtaining card 4 can be used to obtain Image data from the signal S0, for example, if the object 7 can be an Image Sensor (Image Sensor), the Image obtaining card 4 can obtain Image data captured by the object 7 from the signal S0 and convert the Image data into a data format suitable for an Image processing element 9 (e.g., an external computer) at the back end, and if the object 7 is a processing chip of a display, the Image obtaining card 4 can also obtain Image data being played by the display from the signal S0 and convert the Image data into a data format suitable for the Image processing element 9 (e.g., a processor of a computer) at the back end; the above examples are exemplary only and not limiting.

The test head 2 may be provided with various interface cards providing necessary test programs, such as an electronic integrated card (PE card), a device power supply card (DPS card), a serial test card (SEQ card), etc., without being limited thereto.

The test element 3 may be a prober and include a probe card 32, or the test element 3 itself may be the probe card 32, without being limited thereto. The probe card 32 may be provided with a plurality of probes 33, and the probes 33 may contact pins (pins) of the object 7 to be tested, so that the test head 2 can perform an electrical test on the object 7 to be tested. In addition, the image testing system 1 may also include a light source supplying device 6 a. The light source supplying device 6a may be a tube-diameter type light source supplying device and is disposed on the testing head 2, but is not limited thereto. In one embodiment, the light source supplying device 6a focuses the light source onto the object 7 (e.g. an integrated circuit having a plurality of image sensors on a wafer) for testing the actual receiving range of the image sensors of the object 7 for comprehensive image detection, and the probe card 32 can obtain a test signal from the image sensors of the object, wherein the test signal is a C-PHY signal. In addition, in one embodiment, the image capture card 4 may be a Mobile Industry Processor Interface (MIPI) image capture card and is connected to the probe card 32 through a first bridge board 60, but is not limited thereto. In addition, the test element 3 may include a first transmission interface 34, an interface conversion circuit 36 and a second transmission interface 38. The first transmission interface 34 can receive the test signal S0 obtained by the probe 33, the interface conversion circuit 36 can be connected to the first transmission interface 34, the second transmission interface 38 can be connected to the interface conversion circuit 36, and the signal obtaining card 4 can be connected to the second transmission interface 38 and obtain the test signal from the second transmission interface 38. The first transmission interface 34 and the second transmission interface 38 correspond to different signal transmission forms, and the interface conversion circuit 36 can be used for converting the signal transmission form of the test signal.

In one embodiment, the image test system 1 further includes a test signal clock generating circuit 80 for obtaining a test signal clock CLK (shown in fig. 2(a)) from the test signal S0, wherein the test signal clock generating circuit 80 may be disposed on the test device 3 or the image capture card 4; alternatively, in another embodiment, the image capture card 4 may include a pair of clock output pins 41a for directly capturing the test signal clock CLK from the dut 7.

To highlight the effect of the present invention, an embodiment of the present invention is compared with a comparative example.

First, the embodiments of the present disclosure will be described. Fig. 2(a) is a detailed structure diagram of the test device 3 and the image capture card 4 according to the first embodiment of the invention, wherein the test signal clock generation circuit 80 is disposed on the test device 3.

As shown in fig. 2(a), the first transmission interface 34 is used for obtaining the test signal S0 from the end of the dut 7 and transmitting the test signal S0 to the test signal clock generating circuit 80, wherein the test signal S0 is transmitted in a first signal transmission form; in one embodiment, the first transmission interface 34 may be a MIPI C-PHY interface (MIPI C-PHY interface) and includes a 3-wire serial signal path, so that the test signal S0 can be divided into 3 sub-signals S1, S2, S3 (hereinafter referred to as the first sub-signal S1, the second sub-signal S2, and the third sub-signal S3) for transmission. The test signal clock generating circuit 80 is used for transmitting the test signal S0 (i.e., S1, S2, S3) to the interface converting circuit 36, and for obtaining the test signal clock CLK from the test signal S0. The interface conversion circuit 36 can convert the test signal S0 from the first signal transmission form to a second signal transmission form, and transmit the test signal S0 (i.e., S1, S2, S3) to the second transmission interface 38, and the interface conversion circuit 36 can also convert the test signal clock CLK to the second signal transmission form, and transmit the test signal clock CLK to the second transmission interface 38; in one embodiment, the second transmission interface 38 may be a high-speed logic interface and includes a plurality of pairs of high-speed logic signal paths, wherein each pair of high-speed logic signal paths may be differential logic signal paths.

Therefore, the first sub-signal S1 is transmitted as a pair of differential sub-signals S11, S12, the second sub-signal S2 is transmitted as a pair of differential sub-signals S21, S22, the third sub-signal S3 is transmitted as a pair of differential sub-signals S31, S32, and the test signal clock CLK is also transmitted as a pair of differential sub-signals S41, S42.

It should be noted that the test signal clock CLK is directly obtained from the test signal S0 and transmitted to the image capture card 4 through the same transmission path, so that the timing of the test signal clock CLK substantially corresponds to the timing of the test signal S0. Here, "substantially" allows for slight differences, for example, differences of 5% or less, 3% or less, or 1% or less, and is not limited thereto.

In one embodiment, the test device 3 may include a probe card daughter board 35, and the test signal clock generation circuit 80 and the interface conversion circuit 36 may be disposed on the probe card daughter board 35, but are not limited thereto. One of the advantageous effects of providing the probe card daughter board 35 is that the arrangement of the elements on the test element 3 can be made more flexible.

In addition, the image capturing card 4 may include a logic input interface 41, a logic processing unit 44 and a transmission unit 46, wherein the logic input interface 41 includes a plurality of pins and a data conversion circuit 42, some of the pins are used for receiving the test signal S0 (S11-S32) and the test signal clock CLK (S41, S42) from the testing device 3, and the data conversion circuit 42 is used for converting the test signal S0 and the test signal clock CLK in the second signal transmission form into a data format readable by the logic processing unit 44. In one embodiment, if the logic processing unit 44 can read the data format of the second signal transmission type, the test signal S0 and the test signal clock CLK may not be converted; for convenience of illustration, the following paragraphs will exemplify the test signal clock CLK being input to the logic processing unit 44 in a second signaling mode (differential) (the test signal S0 is illustrated as a single signal, but actually the test signal S0 may be in various signaling modes). The logic processing unit 44 can obtain the image data from the test signal S0 according to the test signal S0 and the test signal clock CLK. The image data can be transmitted to the image processing device 9 (e.g., an external computer) at the back end through the transmission unit 46. In one embodiment, the transmission unit 46 may be, for example, a fiber optic interface, but is not limited thereto.

In the present embodiment, the image capture card 4 may further include a pair of additional clock input pins 41a for receiving the test signal clock CLK from the test device 3 (S41, S42). In the embodiment, the logic processing unit 44 is a Field Programmable Gate Array (FPGA), and the conventional architecture thereof has enough pins to receive the test signal S0 and the test signal clock CLK (S41, S42), so that the logic processing unit 44 does not need to add extra pins.

Next, a comparative example will be described. Fig. 2(B) is a schematic diagram of a test device 3 and an image capture card 4 of a comparative example, which has substantially the same structure as the embodiment of fig. 2(a), but does not include the test signal clock generation circuit 80, and the image capture card 4 includes a clock generator 440.

As shown in FIG. 2(B), since the test device 3 does not have the test signal clock generating circuit 80, the test device 3 only transmits the test signal S0 to the image capture card 4, and the logic processing unit 44 must generate the predetermined clock clk0 of the test signal S0 through the clock generator 440 to capture the image data. However, the preset clock clk0 generated by the clock generator 440 is a preset value and cannot correspond to the delay of the test signal S0 on the transmission path, so that there may still be a phase difference between the timings of the clock clk0 and the test signal S0, which may cause signal jitter of the image data obtained by the logic processing unit 44, and the effective bandwidth of the signal is limited, which may cause the quality of the image data to be degraded. To fix this problem, the logic processing unit 44 must add more processing elements and use more complex algorithms, which increases the cost.

In contrast, according to the present invention, the test signal clock CLK is directly obtained from the test signal S0 by the test signal clock generating circuit 80, so that even if the test signal S0 is delayed, the test signal clock CLK obtained from itself is also delayed, and therefore the test signal clock CLK can correspond to the timing state of the test signal S0, thereby greatly reducing the problem of phase difference and improving the quality of image data.

Different embodiments of the invention are possible. Fig. 3 is a detailed configuration diagram of a test device 3 and an image acquisition card 4 according to a second embodiment of the present invention, and please refer to fig. 1 and fig. 2(a) at the same time. The embodiment of FIG. 3 is substantially the same as the embodiment of FIG. 2(A), except that the test signal clock generating circuit 80 is disposed on the image capture card 4.

As shown in fig. 3, the test signal clock generating circuit 80 is disposed on the logic input interface 41. In one embodiment, the test device 3 transmits the test signal S0 in the second signal transmission form (S11 and S12, S21 and S22, S31 and S32) to the logic input interface 41, the data conversion circuit 42 can convert the test signal S0 in the second signal transmission form into a data format readable by the logic processing unit 44 and transmit the converted test signal S0 to the logic processing unit 44, and the data conversion circuit 42 can also convert the test signal S0 in the second signal transmission form into the first signal transmission form and transmit the first signal transmission form to the test signal generating circuit 80, so that the test signal clock generating circuit 80 obtains the test signal clock CLK from the test signal S0 and transmits the test signal clock CLK to the logic processing unit 44 (the data conversion circuit 42 transmits the test signal S0 to the logic processing unit 44). In another embodiment, the data conversion circuit 42 may first convert the test signal S0 in the second signal transmission form into the first signal transmission form and transmit the first signal transmission form to the test signal clock generation circuit 80, and the test signal clock generation circuit 80 transmits the obtained test signal clock CLK and the test signal S0 to the logic processing unit 44 (the signal clock generation circuit 80 transmits the test signal S0 to the logic processing unit 44). Then, the logic processing unit 44 decodes the test signal S0 according to the test signal S0 and the test signal clock CLK to obtain the image data. Since the test signal clock CLK is obtained from the test signal S0, the two timings can be matched and good quality image data can be provided.

In the present embodiment, the logic processing unit 44 is an electric field programmable logic gate array (FPGA) chip, and the conventional architecture has enough pins to receive the test signal S0 and the test signal clock CLK, so that the logic processing unit 44 does not need to add additional pins.

The invention is also capable of different embodiments. Fig. 4 is a detailed architecture diagram of the testing device 3 and the image capturing card 4 according to a third embodiment of the present invention, and please refer to fig. 1 and fig. 2(a) at the same time.

The embodiment of fig. 4 is substantially the same as the embodiment of fig. 2(a), except that the logic processing unit 44 is a custom-built regulator chip (e.g., an Application Specific Integrated Circuit (ASIC)). Since the logic processing unit 44 of the present embodiment is an Application Specific Integrated Circuit (ASIC), an additional input pin 44a (e.g., an additional pair of pins) can be added for receiving the test signal clock CLK from the data conversion circuit 42.

The invention has different embodiments. Fig. 5 is a schematic diagram illustrating a detailed configuration of the testing device 3 and the image capturing card 4 according to a fourth embodiment of the present invention, and please refer to fig. 1 to 4.

The embodiment of FIG. 5 is substantially the same as the embodiment of FIG. 3, except that the logic processing unit 44 is a custom-built conditioning chip (e.g., an Application Specific Integrated Circuit (ASIC)). Since the logic processing unit 44 of the present embodiment is an Application Specific Integrated Circuit (ASIC), an additional input pin 44a (e.g., an additional pair of pins) can be added for receiving the test signal clock CLK from the test signal clock generating circuit 80.

In addition, in order to make the present invention clearer, the details of the test signal clock generating circuit 80 will be described next. Fig. 6(a) is a circuit configuration diagram of the test signal clock generating circuit 80 according to an embodiment of the present invention, and fig. 6(B) is a timing diagram of sub-signals of the test signal S0 according to an embodiment of the present invention, and please refer to fig. 1 to fig. 5 as an assistant.

As shown in fig. 6(a), the test signal clock generating circuit 80 includes a first input terminal 81, a first clock obtaining module 82, a second input terminal 83, a second clock obtaining module 84, a third input terminal 85, a third clock obtaining module 86, and a circuit output terminal 87. The first input 81 is connected to the first clock obtaining module 82, the second input 83 is connected to the second clock obtaining module 84, the third input 85 is connected to the third clock obtaining module 86, and the first clock obtaining module 82, the second clock obtaining module 84 and the third clock obtaining module 86 are respectively connected to the circuit output end 87.

The first input 81 is used for obtaining a first sub-signal S1 of the test signal S0 (first signal transmission type), and the first clock obtaining module 82 is used for obtaining a first sub-signal clock clk _ S1 from the first sub-signal S1 and transmitting the first sub-signal clock clk _ S1 to the circuit output 87. The second input terminal 83 is used for obtaining a second sub-signal S2 of the test signal S0, and the second clock obtaining module 84 is used for obtaining a second sub-signal clock clk _ S2 from the second sub-signal S2 and transmitting the second sub-signal clock clk _ S2 to the circuit output terminal 87. The third input terminal 85 is used for obtaining a third sub-signal S3 of the test signal S0, and the third clock obtaining module 86 is used for obtaining a third sub-signal clock clk _ S3 from the third sub-signal S3 and transmitting the third sub-signal clock clk _ S3 to the circuit output terminal 87. The circuit output 87 is used for integrating the first sub-signal clock CLK _ s1, the second sub-signal clock CLK _ s2, and the third sub-signal clock CLK _ s3 into the test signal clock CLK.

In one embodiment, the first clock retrieving module 82 includes a first buffer 821, a first delay unit 822, and a first exclusive or gate (XOR) 823. The first buffer 821 includes at least two output terminals respectively connected to the first exclusive-or gate 823 and the first delay unit 822. The first XOR gate 823 has two inputs, one of which is connected to the first buffer 821 and the other of which is connected to the first delay unit 822. The first XOR gate 823 has an output connected to the circuit output 87.

Further, the first buffer 821 obtains the first sub-signal S1 from the first input 81 and transmits the first sub-signal S1 to the first delay unit 822 and the first exclusive or gate 823. The first delay unit 822 converts the first sub-signal S1 into a first delayed sub-signal S1_ L, and transmits the first delayed sub-signal S1_ L to the first XOR gate 823. The first exclusive-or gate 823 performs exclusive-or operation on the first sub-signal S1 and the first delayed sub-signal S1_ L to generate the first sub-signal clock clk _ S1. In one embodiment, the delay of the first delay unit 822 for the first delay sub-signal S1_ L can be preset by a user. In one embodiment, the first delayed sub-signal S1_ L is delayed by at least 1/4 cycles compared to the first sub-signal S1; in one embodiment, the first delayed sub-signal S1_ L is delayed from the first sub-signal S1 by at least 1/2 cycles, but is not limited thereto.

In one embodiment, the second clock obtaining module 84 includes a second buffer 841, a second delay unit 842, and a second exclusive-or gate 843. The second buffer 841 includes at least two output terminals respectively connected to the second XOR gate 843 and the second delay unit 842. The second XOR gate 843 has two inputs, one of which is connected to the second buffer 841 and the other of which is connected to the second delay unit 842. An output of the second exclusive-or gate 843 is connected to the circuit output 87.

Further, the second buffer 841 obtains the second sub-signal S2 from the second input 83 and transmits the second sub-signal S2 to the second delay unit 842 and the second XOR gate 843. The second delay unit 842 converts the second sub-signal S2 into a second delayed sub-signal S2_ L, and transmits the second delayed sub-signal S2_ L to the second XOR gate 843. The second exclusive-or gate 843 performs exclusive-or operation on the second sub-signal S2 and the second delayed sub-signal S2_ L to generate the second sub-signal clock clk _ S2. In one embodiment, the delay of the second delay unit 842 for the second delay sub-signal S2_ L can be preset by a user. In one embodiment, the second delayed sub-signal S2_ L is delayed by at least 1/4 cycles compared to the second sub-signal S2; in one embodiment, the second delayed sub-signal S2_ L is delayed from the second sub-signal S2 by at least 1/2 cycles, but is not limited thereto.

In one embodiment, the third clock obtaining module 86 includes a third buffer 861, a third delay unit 862 and a third XOR gate 863. The third buffer 861 comprises at least two output terminals respectively connected to the third XOR gate 863 and the third delay unit 862. The third XOR gate 863 has two inputs, one of which is connected to the third buffer 861 and the other of which is connected to the third delay unit 862. An output of the third XOR gate 863 is coupled to the circuit output 87.

Further, the third buffer 861 obtains the third sub-signal S3 from the third input 85 and transmits the third sub-signal S3 to the third delay unit 862 and the third XOR gate 863. The third delay unit 862 converts the third sub-signal S3 into a third delayed sub-signal S3_ L, and transmits the third delayed sub-signal S3_ L to the third XOR gate 863. The third XOR gate 863 performs an XOR operation on the third sub-signal S3 and the third delayed sub-signal S3_ L to generate the third sub-signal clock clk _ S3. In one embodiment, the delay of the third delay unit 862 for the third delay sub-signal S3_ L can be preset by a user. In one embodiment, the third delayed sub-signal S3_ L is delayed by at least 1/4 cycles compared to the third sub-signal S3; in one embodiment, the third delayed sub-signal S3_ L is delayed from the third sub-signal S3 by at least 1/2 cycles, but is not limited thereto.

In one embodiment, the circuit output 87 may be an OR gate (OR) for performing an OR operation on the first sub-signal clock clk _ s1, the second sub-signal clock clk _ s2, and the third sub-signal clock clk _ s 3.

In an embodiment, the first delay unit 822, the second delay unit 842, and the third delay unit 862 may be implemented by an electronic circuit having a signal delay function, and are not limited thereto.

In one embodiment, if the test signal S0 is required to be output by the test signal clock generating circuit 80, the first buffer 821, the second buffer 841 and the third buffer 861 may each further have an output terminal for outputting the first sub-signal S1, the second sub-signal S2 and the third sub-signal S3.

The details of the generation process of the test signal clock CLK are described below with reference to fig. 6 (B).

As shown in fig. 6(B), the first sub-signal S1 of the test signal S0 has a high level (i.e., has valid data) during the first period T1, and the first sub-signal S1 forms the first delayed sub-signal S1_ L after being delayed by the first delay unit 842, wherein the timing of the first delayed sub-signal S1_ L is delayed by half a cycle compared with the timing of the first sub-signal S1, so that when the first sub-signal S1 and the first delayed sub-signal S1_ L are exclusive-ored by the first exclusive-or gate 823 to generate the first sub-signal clk _ S1, the first sub-signal clk _ S1 has a high level during the first half period corresponding to the first period T1, and has a low level during the second half period corresponding to the first period T1 (similarly, the timing of the fourth period T4 can be inferred). Therefore, the acquisition process of the first sub-signal clock clk _ s1 is known.

Similarly, the second sub-signal S2 of the test signal S0 has a high level during the second period T2, and the second sub-signal S2 forms the second delayed sub-signal S2_ L after being delayed by the second delay unit 842, wherein the timing of the second delayed sub-signal S2_ L is delayed by half a cycle than the timing of the second sub-signal S2, so that when the second sub-signal S2 and the second delayed sub-signal S2_ L are exclusive-ored, the second sub-signal clock clk _ S2 has a high level during the first half period corresponding to the second period T2, and has a low level during the second half period corresponding to the second period T2 (similarly, the timing of the fifth period T5 can be inferred). Therefore, the acquisition process of the second sub-signal clock clk _ s2 is known.

The obtaining process of the third sub-signal clock clk _ s3 can be derived from the obtaining processes of the first sub-signal clock clk _ s1 and the second sub-signal clock clk _ s2, and therefore, will not be described in detail.

After the first sub-signal clock CLK _ s1, the second sub-signal clock CLK _ s2, and the third sub-signal clock CLK _ s3 are ored by the circuit output terminal 87, the first sub-signal clock CLK _ s1, the second sub-signal clock CLK _ s2, and the third sub-signal clock CLK _ s3 are integrated into the test signal clock CLK. Therefore, the formation of the test signal clock CLK and the operation of the test signal clock generating circuit 80 can be understood.

Next, other embodiments of the present invention will be described. When the terminal of the object 7 to be tested can provide the test signal clock CLK by itself, the present invention can also be provided without the test signal clock generating circuit 80. Fig. 7 is a detailed configuration diagram of a test device 3 and an image acquisition card 4 according to a fifth embodiment of the present invention, and please refer to fig. 1 to fig. 6 (B).

As shown in FIG. 7, neither the test device 3 nor the image capture card 4 has the test signal clock generation circuit 80, and the image capture card 4 has an additional pair of clock input pins 41 a. The clock output pin 41a is electrically connected to the object 7 for receiving the test signal clock CLK from the object 7. It should be noted that the end 7 of the dut of the present embodiment must provide the test signal clock CLK, in other words, the end 7 of the dut can be provided with an additional pair of differential output terminals for outputting the test signal clock CLK (S41, S42) to the image capture card 4.

As shown in fig. 7, since fig. 7 is an equivalent diagram of the arrangement of the elements, a signal transmission distance (e.g., L1 in fig. 7) of the test signal clock CLK from the object 7 to the image capture card 4 is substantially equal (or similar) to a signal transmission distance (e.g., L2 in fig. 7) of the test signal S0 from the object 7 and the test element 3 to the image capture card 4, so that the delay conditions of the test signal S0 and the test signal clock CLK during transmission are also similar, and when the logic processing unit 44 processes the test signal S0 and the test signal clock CLK, the phase difference therebetween can be small, and thus the image data obtained from the test signal S0 can have good quality.

In one embodiment, "the transmission distances are substantially equal" indicates that the difference between the two transmission distances is within 20%. In one embodiment, "the transmission distances are substantially equal" means that the difference between the two transmission distances is within 10%. In one embodiment, "the transmission distances are substantially equal" means that the difference between the two transmission distances is within 5%. The present invention is not limited thereto.

Fig. 8 is a detailed configuration diagram of a test device 3 and an image acquisition card 4 according to a sixth embodiment of the invention, and please refer to fig. 1 to 7.

The embodiment of FIG. 8 is substantially similar to the embodiment of FIG. 7, except that the logic processing unit 44 of the embodiment of FIG. 8 is an Application Specific Integrated Circuit (ASIC). Since the logic processing unit 44 is an Application Specific Integrated Circuit (ASIC), it has an additional pair of input pins for receiving the test signal clock CLK.

Similar to the embodiment shown in fig. 7, the transmission distance of the test signal S0 is substantially equal to the transmission distance of the test signal clock CLK, so that the image data obtained from the test signal S0 can also have good quality.

The above-mentioned arrangement is merely an example, and there are still more arrangements between the test device 3 and the image acquisition card 4 according to the present invention.

Therefore, the present invention provides an improved image test system, test device and image capture card, which can reduce the phase difference between the test signal and the test signal clock, further solve the problem of limited signal bandwidth, reduce the cost expenditure and improve the quality of image data.

The above embodiments are merely exemplary for convenience of description, and the claimed invention shall be defined by the claims rather than the embodiments.

Claims

1. An image testing system, comprising:

the test element is used for obtaining a test signal of an object to be tested and comprises an interface conversion circuit used for converting the signal transmission form of the test signal;

an image acquisition card for acquiring the test signal from the test device and acquiring an image data from the test signal; and

the image test system also comprises a test signal clock pulse generating circuit used for obtaining a test signal clock pulse from the test signal, or the image obtaining card also comprises a pair of clock pulse input pins used for directly obtaining the test signal clock pulse from the object to be tested.

2. The image test system of claim 1, wherein the test signal clock generating circuit is disposed in the test device or the image capture card.

3. The image testing system of claim 2, wherein the testing signal comprises a first sub-signal, a second sub-signal and a third sub-signal, the testing signal clock generating circuit comprises a first input terminal for obtaining the first sub-signal, a first clock obtaining module for obtaining a first sub-signal clock from the first sub-signal and transmitting the first sub-signal clock to the circuit output terminal, a second input terminal for obtaining the second sub-signal, a third clock obtaining module for obtaining a second sub-signal clock from the second sub-signal and transmitting the second sub-signal clock to the circuit output terminal, and a circuit output terminal, the third clock obtaining module is used for obtaining a third sub-signal clock from the third sub-signal and transmitting the third sub-signal clock to the circuit output end, and the circuit output end integrates the first sub-signal clock, the second sub-signal clock and the third sub-signal clock into the test signal clock.

4. The image testing system of claim 3, wherein the circuit output is an OR gate.

5. The image testing system of claim 4, wherein the first clock obtaining module comprises a first buffer, a first delay unit and a first exclusive-or gate, the first buffer obtains the first sub-signal from the first input end and transmits the first sub-signal to the first delay unit and the first exclusive-or gate, the first delay unit converts the first sub-signal into a first delayed sub-signal and transmits the first delayed sub-signal to the first exclusive-or gate, and the first exclusive-or gate performs exclusive-or operation on the first sub-signal and the first delayed sub-signal to form the first sub-signal clock.

6. The image testing system of claim 5, wherein the second clock obtaining module comprises a second buffer, a second delay unit and a second XOR gate, the third clock obtaining module comprises a third buffer, a third delay unit and a third XOR gate, the second buffer obtains the second sub-signal from the second input terminal and transmits the second sub-signal to the second delay unit and the second XOR gate, the second delay unit converts the second sub-signal into a second delayed sub-signal and transmits the second delayed sub-signal to the second XOR gate, the second XOR gate performs XOR operation on the second sub-signal and the second delayed sub-signal to form the second sub-signal, the third buffer obtains the third sub-signal from the third input terminal and transmits the third sub-signal to the third delay unit and the third XOR gate, the third delay unit converts the third sub-signal into a third delayed sub-signal, and transmits the third delayed sub-signal to the third exclusive-or gate, which performs exclusive-or operation on the third sub-signal and the third delayed sub-signal to form the third sub-signal clock.

7. The image test system of claim 6, wherein when the test signal clock generating circuit is disposed on the test device, the first buffer further transmits the first sub-signal to the image capture card, the second buffer further transmits the second sub-signal to the image capture card, and the third buffer further transmits the third sub-signal to the image capture card.

8. The image test system of claim 1, wherein when the image capture card includes the pair of clock input pins to directly capture the test signal clock from the dut, a signal transmission distance of the test signal clock from the dut to the image capture card is equal to a signal transmission distance of the test signal clock from the dut, the test device, and the image capture card.

9. A test element is arranged in an image test system, the image test system also comprises an image acquisition card, wherein the test element comprises:

a first transmission interface for obtaining a test signal of an object to be tested;

a test signal clock generating circuit for obtaining a test signal clock from the test signal and transmitting the test signal clock to the image obtaining card;

an interface switching circuit for switching the signal transmission form of the test signal; and

and the second transmission interface is used for transmitting the test signal to the image acquisition card.

10. The test device of claim 9, wherein the test signal comprises a first sub-signal, a second sub-signal, and a third sub-signal, the test signal clock generating circuit comprises a first input terminal for obtaining the first sub-signal, a first clock obtaining module for obtaining a first sub-signal clock from the first sub-signal and transmitting the first sub-signal clock to the circuit output terminal, a second input terminal for obtaining the second sub-signal, a third clock obtaining module for obtaining a second sub-signal clock from the second sub-signal and transmitting the second sub-signal clock to the circuit output terminal, and a circuit output terminal, the third clock obtaining module is used for obtaining a third sub-signal clock from the third sub-signal and transmitting the third sub-signal clock to the circuit output end, and the circuit output end integrates the first sub-signal clock, the second sub-signal clock and the third sub-signal clock into the test signal clock.

11. The test element of claim 10, wherein the circuit output is an or gate.

12. The test device of claim 11, wherein the first clock obtaining module comprises a first buffer, a first delay unit and a first exclusive-or gate, the first buffer obtains the first sub-signal from the first input terminal and transmits the first sub-signal to the first delay unit and the first exclusive-or gate, the first delay unit converts the first sub-signal into a first delayed sub-signal and transmits the first delayed sub-signal to the first exclusive-or gate, and the first exclusive-or gate performs an exclusive-or operation on the first sub-signal and the first delayed sub-signal to form the first sub-signal clock.

13. The test device of claim 12, wherein the second clock obtaining module comprises a second buffer, a second delay unit and a second exclusive-or gate, the second buffer obtains the second sub-signal from the second input terminal and transmits the second sub-signal to the second delay unit and the second exclusive-or gate, the second delay unit converts the second sub-signal into a second delayed sub-signal and transmits the second delayed sub-signal to the second exclusive-or gate, and the second exclusive-or gate performs an exclusive-or operation on the second sub-signal and the second delayed sub-signal to form the second sub-signal clock.

14. The test device of claim 13, wherein the third clock obtaining module comprises a third buffer, a third delay unit and a third exclusive-or gate, the third buffer obtains the third sub-signal from the third input terminal and transmits the third sub-signal to the third delay unit and the third exclusive-or gate, the third delay unit converts the third sub-signal into a third delayed sub-signal and transmits the third delayed sub-signal to the third exclusive-or gate, and the third exclusive-or gate performs an exclusive-or operation on the third sub-signal and the third delayed sub-signal to form the third sub-signal clock.

15. An image acquisition card is arranged in an image test system, the image test system also comprises a test element for acquiring a test signal of an object to be tested, and the test element comprises an interface conversion circuit for converting the signal transmission form of the test signal, wherein the image acquisition card comprises:

a test signal clock generating circuit for receiving the test signal from the test element and obtaining a test signal clock from the test signal; and

a logic processing unit, which obtains an image data from the test signal according to the test signal clock.

16. The image capturing card of claim 15, wherein the test signal comprises a first sub-signal, a second sub-signal and a third sub-signal, the test signal clock generating circuit comprises a first input terminal for obtaining the first sub-signal, a first clock obtaining module for obtaining a first sub-signal clock from the first sub-signal and transmitting the first sub-signal clock to the circuit output terminal, a second input terminal for obtaining the second sub-signal, a third clock obtaining module for obtaining a second sub-signal clock from the second sub-signal and transmitting the second sub-signal clock to the circuit output terminal, and a circuit output terminal, the third clock obtaining module is used for obtaining a third sub-signal clock from the third sub-signal and transmitting the third sub-signal clock to the circuit output end, and the circuit output end integrates the first sub-signal clock, the second sub-signal clock and the third sub-signal clock into the test signal clock.

17. The image capture card of claim 16, wherein said circuit output is an or gate.

18. The image capturing card of claim 17, wherein the first clock obtaining module comprises a first buffer, a first delay unit and a first exclusive-or gate, the first buffer obtains the first sub-signal from the first input end and transmits the first sub-signal to the first delay unit and the first exclusive-or gate, the first delay unit converts the first sub-signal into a first delayed sub-signal and transmits the first delayed sub-signal to the first exclusive-or gate, and the first exclusive-or gate performs an exclusive-or operation on the first sub-signal and the first delayed sub-signal to output the first sub-signal clock.

19. The image capturing card of claim 18, wherein the second clock obtaining module comprises a second buffer, a second delay unit and a second exclusive-or gate, the second buffer obtains the second sub-signal from the second input terminal and transmits the second sub-signal to the second delay unit and the second exclusive-or gate, the second delay unit converts the second sub-signal into a second delayed sub-signal and transmits the second delayed sub-signal to the second exclusive-or gate, and the second exclusive-or gate performs an exclusive-or operation on the second sub-signal and the second delayed sub-signal to output the second sub-signal clock.

20. The image capturing card of claim 19, wherein the third clock obtaining module comprises a third buffer, a third delay unit and a third exclusive-or gate, the third buffer obtains the third sub-signal from the third input terminal and transmits the third sub-signal to the third delay unit and the third exclusive-or gate, the third delay unit converts the third sub-signal into a third delayed sub-signal and transmits the third delayed sub-signal to the third exclusive-or gate, and the third exclusive-or gate performs an exclusive-or operation on the third sub-signal and the third delayed sub-signal to output the third sub-signal clock.