CN114595160A

CN114595160A - Storage device, control method of storage device, and storage medium

Info

Publication number: CN114595160A
Application number: CN202011416491.XA
Authority: CN
Inventors: 赖敬中; 李连春; 陈春树
Original assignee: SK Hynix Inc
Current assignee: SK Hynix Inc
Priority date: 2020-12-04
Filing date: 2020-12-04
Publication date: 2022-06-07

Abstract

A storage device, a control method of the storage device, and a storage medium, which are applicable to an apparatus having a memory. Providing, by a storage device controller, a superblock valid page count table for a plurality of superblocks and a plurality of internal block valid page count tables for the plurality of superblocks, and providing a plurality of virtual block mapping tables for the plurality of memory chips to map a first superblock of the plurality of superblocks with a physical block address association to a second superblock of the plurality of superblocks. And when the storage device needs to execute garbage collection, the effective number of pages of the super blocks is reduced by updating and mapping the selected super blocks to be subjected to garbage collection to the internal blocks, so that the garbage collection efficiency is improved.

Description

Storage device, control method of storage device, and storage medium

Technical Field

The present invention relates to electronic devices, and particularly to a storage device, a method for controlling the storage device, and a storage medium.

Background

Since data stored in a nonvolatile memory device does not disappear even after power is turned off and has the characteristics of power saving and small size, the nonvolatile memory device such as a flash memory-based memory device is widely used in electronic apparatuses. In addition, nonvolatile memory devices such as solid State Storage Devices (SSD) have also gradually become memory devices equipped in computer systems such as desktop computers, notebook computers, servers, and the like.

When an electronic apparatus executes an application program to store various data such as characters, data, photographs, and broadcast audio or video, it is often necessary to request a large amount of data writing operation to a storage device in a short time. A controller of the storage apparatus may generate a write command at a write request of an electronic device (i.e., a host), and execute the generated write command. A controller of the storage device may utilize the command queue to store host write commands. The host write commands stored in the command queue can be sequentially output to the memory of the storage device for data write operation. On the other hand, storage devices also have a need for internal data movement. If the storage device is handling internal data movement, the efficiency of the execution of the write command from the electronic device may be affected, resulting in a decrease and floating of the write performance for the electronic device. As such, the decrease and floating of the write performance may be reflected in the degree flow reflected by the application or the floating instability of the efficiency of the service provided by the application.

Write Amplification (WA) is an undesirable phenomenon for flash memory or solid state disk storage devices, i.e., the amount of physical data actually written is a multiple of the amount of data written. In flash memories and solid state disks, data is written into flash memories in units of pages (pages) composed of a plurality of memory cells (cells). However, erasing can only be performed in larger units, such as blocks (blocks) consisting of a plurality of pages. If there are some pages in a block that have data that is no longer needed, these pages are called invalid pages (invalid pages), and the pages in the block that have needed data are called valid pages (valid pages). In order to make the block available for new data writing, the storage device performs a process called Garbage Collection (GC), which reads only valid pages in the block, and rewrites the valid pages in another previously erased empty block, and then erases the block to become a new empty block. All SSDs contain varying degrees of garbage collection mechanisms, but differ in the frequency and speed of execution. Garbage collection accounts for a significant portion of the write amplification of the storage devices described above.

Therefore, in many internal data movement requirements of the storage device, garbage collection is an important component, and the efficiency of garbage collection affects the overall writing efficiency of the electronic device.

Disclosure of Invention

Embodiments provide a storage device, a storage device control method, and a storage medium, which can be used in a device having a memory and can reduce the number of valid pages of a super block to be garbage collected by processing the super block when the storage device needs to perform garbage collection with respect to internal data movement, thereby improving the efficiency of garbage collection.

Embodiments provide a control method of a storage device including a storage device controller and a memory including a plurality of memory chips, the control method including the following steps. (a) Providing, by the storage device controller, a super-block valid page count table of a plurality of super-blocks (super-blocks) and a plurality of internal block valid page count tables of the plurality of super-blocks, wherein each super-block corresponds to a set of distinct, non-overlapping, plurality of physical blocks belonging to the plurality of memory chips, each physical block corresponds to a portion of a plurality of pages of a corresponding one of the plurality of memory chips, and the super-block valid page count table includes a total valid number of pages of the plurality of physical blocks corresponding to respective ones of the plurality of super-blocks, each internal block valid page count table corresponds to a super-block of the plurality of super-blocks and includes a plurality of valid number of pages corresponding to the plurality of physical blocks of the super-blocks. (b) Providing, by the storage device controller, a plurality of virtual block mapping tables of the plurality of memory chips to map a first superblock of the plurality of superblocks associated with a physical block address to a second superblock of the plurality of superblocks. (c) Determining, by the storage device controller, at least one selected super block of the plurality of super blocks to be processed for a garbage collection operation based on the super block valid page count table. (d) Reducing, by the storage device controller, a total number of valid pages of the at least one selected super block by remapping the at least one selected super block based on the plurality of internal block valid page count tables and the plurality of virtual block mapping tables. (e) Performing a garbage collection operation on the at least one selected super-block of the remap.

In one embodiment, the step (d) comprises: (d1) determining whether a memory chip to which a first physical block of a plurality of physical blocks of the at least one selected super block belongs has a second physical block based on the internal block valid page count tables, wherein the valid page number of the second physical block is smaller than that of the first physical block; and (d2) if it is determined that the memory chip to which the first physical block of the plurality of physical blocks of the at least one selected super block belongs has a second physical block with a valid page count less than the valid page count of the first physical block, remapping the first physical block and the second physical block by updating at least one of the plurality of virtual block pair mappings.

In one embodiment, the step (d1) is performed when the number of valid pages of the first physical block is greater than or equal to a valid page number threshold.

In one embodiment, in the step (d2), the first physical block and the second physical block of the at least one selected super block are remapped by updating the virtual block mapping table of the memory chip to which the first physical block and the second physical block of another super block belong.

In one embodiment, the virtual block mapping table of the memory chip is updated to include data indicating mapping of the first physical block of the at least one selected super-block to a second physical block of another super-block.

Embodiments also provide a storage medium recording program codes for causing a storage device to execute a control method of the storage device according to any one of the above embodiments.

Embodiments additionally provide a storage device comprising a memory and a storage device controller. The memory includes a plurality of memory chips. The storage device controller is electrically connected to the memory and is used for controlling the memory to perform data access on the memory, wherein the storage device controller is configured to execute a plurality of operations. The plurality of operations include the following. (a) Providing, by the storage device controller, a super-block valid page count table of a plurality of super-blocks (super-blocks) and a plurality of internal block valid page count tables of the plurality of super-blocks, wherein each super-block corresponds to a set of distinct, non-overlapping, plurality of physical blocks belonging to the plurality of memory chips, each physical block corresponds to a portion of a plurality of pages of a corresponding one of the plurality of memory chips, and the super-block valid page count table includes a total number of valid pages of the plurality of physical blocks corresponding to respective ones of the plurality of super-blocks, each internal block valid page count table corresponds to a super-block of the plurality of super-blocks and includes a plurality of valid pages corresponding to the plurality of physical blocks of the super-blocks. (b) Providing, by the storage device controller, a plurality of virtual block mapping tables of the plurality of memory chips to map a first superblock of the plurality of superblocks associated with a physical block address to a second superblock of the plurality of superblocks. (c) Determining, by the storage device controller, at least one selected super block of the plurality of super blocks to be processed for a garbage collection operation based on the super block valid page count table. (d) Reducing, by the storage device controller, a total number of valid pages of the selected super block by remapping the at least one selected super block based on the plurality of internal block valid page count tables and the plurality of virtual block mapping tables. (e) Performing a garbage collection operation on the at least one selected super-block of the remap.

In one embodiment, the operation (d) includes: (d1) determining whether a memory chip to which a first physical block of a plurality of physical blocks of the at least one selected super block belongs has a second physical block based on the internal block valid page count tables, wherein the valid page number of the second physical block is smaller than that of the first physical block; and (d2) if it is determined that the memory chip to which the first physical block of the plurality of physical blocks of the at least one selected super block belongs has a second physical block with a valid page count less than the valid page count of the first physical block, remapping the first physical block and the second physical block by updating at least one of the plurality of virtual block pair mappings.

In one embodiment, the storage device controller performs the operation when the valid page number of the first physical block is greater than or equal to a valid page number threshold (d 1).

In one embodiment, in the operation (d2), the storage device controller remaps the first physical block and the second physical block of the at least one selected super block by updating the virtual block mapping of the memory chip to which the first physical block and the second physical block of another super block belong.

In one embodiment, the storage device controller updates the virtual block mapping table of the memory chip to include data indicating mapping of the first physical block of the at least one selected super-block to a second physical block of another super-block.

The embodiment provides a storage device, a control method of the storage device and a storage medium, which can be used for a device with a memory, and can be used for the device with the memory, and when the storage device needs to perform garbage collection related to internal data movement, the effective page number of the super block can be reduced by updating and mapping the selected super block to be subjected to garbage collection so as to improve the garbage collection efficiency. Therefore, the overall writing efficiency of the electronic device using the storage device can be promoted to be improved.

For a better understanding of the nature and technical content of the present invention, reference should be made to the following detailed description of the invention, taken in conjunction with the accompanying drawings, which are set forth to illustrate, but are not to be construed to limit the scope of the invention.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive labor.

FIG. 1 is a schematic block diagram of one embodiment of a storage device;

FIG. 2 is a schematic block diagram of one embodiment of a storage device controller;

FIG. 3 is a schematic flow chart diagram illustrating one embodiment of a method for controlling a storage device;

FIG. 4 is a schematic diagram of one embodiment of a super-block;

FIG. 5 is a schematic diagram of one embodiment of a plurality of internal block valid page count tables for a plurality of memory chips;

FIG. 6 is a diagram of one embodiment of a plurality of virtual block mapping tables of a plurality of memory chips;

FIG. 7 is a schematic flow chart diagram illustrating one embodiment of step S40 in FIG. 3;

FIG. 8A is a schematic diagram of one embodiment of intra block remapping for a selected super block;

FIG. 8B is a schematic diagram of one embodiment of intra block remapping for a selected super block;

FIG. 9A is a diagram of one embodiment of mapping relationships of inner blocks of a super block;

FIG. 9B is a diagram of one embodiment of the mapping relationship of the inner blocks of a super block after remapping the inner blocks for a selected super block; and

fig. 10 is a schematic flow chart of another embodiment of step S40 in fig. 3.

Reference numerals

10 host

100. 300 storage device controller

110 processing unit

120 buffer unit

130_1 ~ 130_ N memory channel

140 storage channel control unit

150 host interface unit

160 bus

200 memory

D1_ 1-D1 _ M, DN _ 1-DN _ M memory chips

310 host interface layer

320 flash memory translation layer

330 flash memory interface layer

CH0, CH1, CH2, CH3 memory channels

D0, D1-D31 memory chip

B _ D0, B _ D1-B _ D31 physical blocks

CE0, CE1 CE7 enable signals

SB, SB0, SBX, SBY, SBZ super-block

SB _ VT super Block valid Page count Table

SB0_ IT, SB1_ IT ~ SBP _ IT internal block valid page count table

L2PMT logical to entity mapping table

LBA logical Block Address

D0_ VMT, D1_ VMT DQ-1_ VMT virtual block mapping table

S10-S50

S41 and S45 steps

S110 to S170

Detailed Description

For the purpose of promoting an understanding of the objects, features and effects of the invention, embodiments for describing the invention in detail are provided together with the accompanying drawings.

Referring to fig. 1, which illustrates an embodiment of the memory device of the present invention, the memory device of fig. 1 may be used to implement the control method of fig. 3, 5 or 10 (which will be described in detail later, and is temporarily skipped here), and accordingly, when the memory device needs to perform garbage collection related to internal data movement, the effective number of pages of the super block is reduced by processing the update map of the selected super block to be subjected to garbage collection to reduce the effective number of pages of the super block, so as to improve the garbage collection performance. As shown in fig. 1, the storage device includes a storage device controller 100 and a memory 200. The memory device controller 100 includes a processing unit 110, a buffer unit 120, a plurality of memory channels 130_1 to 130_ N (e.g., N is an integer greater than 1), and a corresponding memory channel control unit 140. The buffer unit 120 may be implemented using a volatile memory or a nonvolatile memory. The memory 200 includes a plurality of memory chips D1_ 1-D1 _ M through DN _ 1-DN _ M (e.g., N, M is an integer greater than 1). For example, the memory chip is a flash memory, such as a NOR type memory or a NAND type memory, however, the implementation of the present invention is not limited by this example.

The storage device controller 100 may communicate with the host 10 through the host interface unit 150 to receive a read request or a write request from the host 10. The storage device controller 100 generates a corresponding read command or write command for a host read request or a host write request, and transmits the generated corresponding command to the storage channel control unit 140 of the corresponding storage channel (e.g., 130_1 to 130_ N). The memory channel control unit 140 is used for controlling at least one memory chip. For example, the memory channel control unit 140 transmits a data read command to a certain memory chip and transmits data read thereby to the memory device controller 100, such as the buffer unit 120. The storage device controller 100 transfers data requested by the host 10 to the host 10. For another example, the memory channel control unit 140 writes data to be written into the memory chip according to the data write command. When the storage device controller 100 controls the operation of the memory 200, the buffer unit 120 may store data used by the storage device controller 100 and the memory 200 for various operations such as a read operation, a write operation, a program operation, and an erase operation. In FIG. 1, a plurality of memory channel control units 140 operate read or write operations in parallel. In addition, the processing unit 110 can be electrically coupled to the memory channels (e.g., 130_1 to 130_ N) via the bus 160. However, the implementation of the present invention is not limited by the above examples. For example, the aforementioned respective memory channel control units may be implemented with logic circuits or programmable circuits, or implemented in a software manner and executed by the processing unit 110.

The host interface unit 150 may process commands and data provided from the host 10, and may communicate with the host 10 through at least one of various interface protocols, such as a Universal Serial Bus (USB), a multimedia card (MMC), a peripheral component interconnect-express (PCI-E), a serial attached SCSI (sas), a Serial Advanced Technology Attachment (SATA), a Parallel Advanced Technology Attachment (PATA), a Small Computer System Interface (SCSI), an Enhanced Small Disk Interface (ESDI), and an Integrated Drive Electronics (IDE).

Referring to fig. 1 and fig. 2 together, fig. 2 is a schematic block diagram of an embodiment of a storage device controller. Fig. 2 presents an architecture when the storage device controller 300 is implemented in firmware or software. For example, the storage device controller 300 includes a host interface layer 310, a flash memory translation layer 320, and a flash memory interface layer 330. The host interface layer 310 is used to communicate with the host 10 and serves as an interface between the host 10 and the storage device controller 300. The flash translation layer 320 is used to manage read, write, and erase operations. The flash translation layer 320 is further used for translating the logical address (e.g. logical block address or logical page address) into the physical address (e.g. physical block address or physical page address) corresponding to the memory chips (e.g. D1_ 1-D1 _ M-DN _ 1-DN _ M) of the memory 200. The flash interface layer 330 is used for handling communication between the flash translation layer 320 and the memory 200, such as transferring commands from the flash translation layer 320 to the memory 200.

The storage device controller 300 shown in FIG. 2 may be implemented using the hardware architecture of FIG. 1. The flash translation layer 320 needs to refer to and maintain the address mapping table when performing the logical address translation to the physical address. Because the address mapping table has a large amount of data, the flash memory translation layer 320 stores a partial section of the address mapping table in a cache (cache). When there is no mapping relationship between the logical address and the physical address required for translation in the cache, the flash translation layer 320 needs to update the contents of the segment of the address mapping table in the cache to generate the mapping table read command. Furthermore, in some memory product applications, such as an embedded multimedia card (eMMC) or other memory products, the address map is stored in the memory of the memory product, and the invention is not limited by this example.

The storage device controller 300 controls various operations with respect to the memory 200, such as a write operation, a read operation, a program operation, an erase operation. For example, the storage device controller may generate a write command under a write request of the host 10 and execute the generated write command. The storage device controller may use the command queue to store host write commands. The storage device controller can process the host write commands stored in the command queue in sequence to perform data write operations.

In particular, the storage device controller 300 controls firmware algorithms for the flash memory translation layer 320. For example, the storage device controller 300 may implement algorithms including Garbage Collection (GC), wear-leveling (WL), block reclamation (BC), and a failed block (RBB). Thus, for example, when performing any of garbage collection, wear leveling, block reclamation, and failing block algorithms, the memory device also has a need for internal data movement.

As the memory device performs internal data movement and host data writing, there is a possibility that write performance may be degraded or floated. If the storage device controller needs to handle a large amount of internal data movement, the efficiency of the execution of the write command from the host may be affected, resulting in a decrease in write performance for the electronic device. Conversely, if there is little or no internal data movement requirements of the storage device controller, the write performance increases. In order to promote stability or performance improvement of host data writing efficiency, embodiments of a control method for a storage device are provided below.

Please refer to fig. 3, which is a schematic flow chart diagram illustrating an embodiment of a method for controlling a storage device. The embodiment shown in FIG. 3 can be applied to a device with memory and can be used to achieve the purpose of increasing the garbage collection efficiency by reducing the effective number of pages of the super block to be garbage collected by processing the selected super block when the memory device needs to perform garbage collection related to internal data movement. Referring to fig. 1 and 3, an embodiment of a method for controlling the storage device of fig. 3 includes the following steps S10 to S50. The components in fig. 1 are referred to as an example for the purpose of assisting the description, however, the implementation of the control method is not limited by the example.

Providing, by the storage device controller 100, a super block valid page count table for a plurality of super blocks (superblocks) and a plurality of internal block valid page count tables for the plurality of super blocks as shown in step S10, wherein each super-block corresponds to a different, non-overlapping set of a plurality of physical blocks belonging to a plurality of memory chips (e.g., D1_ 1-D1 _ M-DN _ 1-DN _ M) of the memory device, each physical block corresponding to a portion of a plurality of pages of a corresponding one of the plurality of memory chips (e.g., one of D1_ 1-D1 _ M-DN _ 1-DN _ M), and the super block valid page count table includes a total valid page number of a plurality of physical blocks corresponding to respective ones of the plurality of super blocks, and each internal block valid page count table corresponds to a super block of the plurality of super blocks and includes a plurality of valid page numbers corresponding to the plurality of physical blocks of the super block.

In step S20, a plurality of virtual block mapping tables of the plurality of memory chips are provided by the storage controller 100 to map a first superblock of the plurality of superblocks associated with a physical block address to a second superblock of the plurality of superblocks.

In step S30, at least one selected super block of the super blocks to be processed for garbage collection is determined by the storage controller 100 based on the super block valid page count table. For example, the super block with the minimum or less total effective page number is determined as the at least one selected super block in the plurality of super blocks according to the total effective page number of each super block.

Reducing, by the storage device controller 100, the total effective number of pages of the selected super block by remapping the at least one selected super block based on the plurality of internal block effective page count tables and the plurality of virtual block mapping tables, as shown in step S40. For example,

in step S50, a garbage collection operation is performed on the at least one selected super block.

Accordingly, the embodiments described above provide a control method and a storage medium for a storage device, which can be used in a device having a memory, and can reduce the number of valid pages of a super block to be garbage collected by updating an internal block by updating a selected super block when the storage device needs to perform garbage collection related to internal data movement, thereby improving the efficiency of garbage collection. Therefore, the overall writing efficiency of the electronic device using the storage device can be promoted to be improved.

The following is exemplified with respect to steps S10 to S50 in fig. 3, respectively.

Regarding the super block (superblock) in step S10, please refer to fig. 4, which is a schematic diagram of an embodiment of the super block. As shown in FIG. 4, a super-block SB corresponds to a set of different, non-overlapping physical blocks (e.g., B _ D0, B _ D1-B _ D31) belonging to a plurality of memory chips (e.g., D0, D1-D31). Each physical block (e.g., B _ D0, B _ D1, or B _ D31) corresponds to a portion of a plurality of pages of a corresponding one of the plurality of memory chips (e.g., D0, D1, or D31). In other words, the super-block SB is a set of physical blocks (e.g., B _ D0, B _ D1-B _ D31) in each memory chip (e.g., D0, D1-D31). Then, another physical block which does not overlap with the physical blocks (e.g., B _ D0, B _ D1-B _ D31) of the super-block SB can be further selected from each memory chip (e.g., D0, D1-D31) to form another super-block. By analogy, a plurality of super-blocks are established, each super-block corresponding to a different, non-overlapping set of a plurality of physical blocks belonging to the plurality of memory chips (e.g., D0, D1-D31).

Furthermore, in some embodiments, for a storage device controller 300 implemented based on the flash memory translation layer 320 of fig. 2, the flash memory translation layer 320 may utilize the super block SB as a block allocation unit (block allocation unit). For example, in the example of implementing a memory device based on fig. 1, 2, and 4, the memory chips D0, D4 to D28 may correspond to the memory channel CH0 in the memory device, the memory chips D1, D5 to D29 may correspond to the memory channel CH1 in the memory device, the memory chips D2, D6 to D30 may correspond to the memory channel CH2 in the memory device, and the memory chips D3, D7 to D31 may correspond to the memory channel CH3 in the memory device. Furthermore, in the above example, a plurality of Chip Enable (CE) signals may be implemented in the memory device to control the corresponding memory chips, so that multiple memory channels may be applied to read from or write to the plurality of memory chips to increase the performance of reading and writing, wherein, for example, 8 corresponding relationships indicated by the enable signals represented by CE0 and CE1 to CE7 are shown in fig. 4, for example, the enable signal CE0 is indicated to be applicable to D0 to D3, and the like. However, the implementation of the present invention is not limited by this example.

In the control method shown in fig. 3, the super-partition is processed, so in steps S10 and S20, a look-up table (look-up table) associated with a plurality of super-partitions is proposed to facilitate the implementation of the control method, where the look-up tables include: a superblock valid page count table for a plurality of superblocks, a plurality of internal block valid page count tables, and a plurality of virtual block mapping tables for the plurality of memory chips.

In step S10, the super-block valid page count table includes a total valid page number of a plurality of physical blocks corresponding to each super-block of the plurality of super-blocks. For example, if there are 20 super blocks, the super block valid page count table may be configured with 20 corresponding fields, which respectively record the total valid page number of the corresponding super blocks. For example, based on the storage device controller of fig. 1 or fig. 2, the super-block valid page count table may be established, initial values thereof are set, and the total valid page number of each super-block is recorded, counted or updated during the operation of the storage device controller, which may be implemented by using the flash memory translation layer 320.

In the control method as shown in fig. 3, a plurality of internal block valid page count tables are further provided by the storage device controller (or flash memory translation layer). In detail, the physical blocks (e.g., B _ D0, B _ D1-B _ D31) formed in each super-block (e.g., SB of FIG. 4) can be referred to as internal blocks, so that for the super-block (e.g., SB of FIG. 4), the storage device controller (or flash memory translation layer) provides an internal block valid page count table corresponding to the super-block (e.g., SB of FIG. 4). For example, for the example of superblock SB in fig. 4, the internal block valid page count table includes corresponding and equal number (e.g. 32) of the multiple physical blocks (e.g. B _ D0, B _ D1-B _ D31) of the superblock SB, i.e. each field records the valid page number of the corresponding physical area.

Please refer to fig. 5, which is a diagram illustrating an embodiment of a plurality of internal block valid page count tables of a plurality of memory chips. In one example of a memory device based on fig. 1 and 2, a memory device controller of the memory device may be configured to provide P +1 super blocks (e.g., P is an integer greater than or equal to 1), where the super blocks may be represented by symbols SB0, SB 1-SBP, respectively), the super block valid page count table SB _ VT of the P +1 super blocks has P +1 fields, and each field records the total valid page number of all entity blocks of the corresponding super block, as shown in fig. 5. In addition, as shown in fig. 5, there are P +1 internal block valid page count tables SB0_ IT and SB1_ IT to SBP _ IT corresponding to the P +1 super blocks, and each internal block valid page count table records the valid page number of each physical block of the corresponding super block (e.g., SB0, SB1 to SBP). For example, the storageThe device has Q units (e.g.

Memory chip (e.g. chip)

N, M is an integer greater than 1), then each super block has Q physical blocks, so the internal block valid page count table corresponding to each super block also has Q columns, and the Q columns record the respective valid page numbers of all internal blocks of the super block (e.g., SB0, SB1 or SBP). For example, based on the storage device controller of fig. 1 or fig. 2, an internal block valid page count table corresponding to each super block may be established, an initial value thereof is set, and the number of individual valid pages of the internal block of each super block is recorded, counted, or updated during the operation of the storage device controller, which may be implemented by using the flash memory translation layer 320. However, the implementation of the present invention is not limited by the above examples.

Referring to fig. 6, a schematic diagram of an embodiment of a mapping table of a plurality of virtual blocks of a plurality of memory chips is shown in step S20. In one example of a memory device based on fig. 1, 2, the memory of the memory device comprises Q memory chips (as may be represented by the symbols D0, D1-DQ-1, respectively). The memory device controller may be configured to provide Q virtual block mapping tables D0_ VMT, D1_ VMT to DQ-1_ VMT, respectively corresponding to the Q memory chips, as shown in fig. 6. For example, the virtual block maps are used to map a first superblock of the superblocks associated with a physical block address obtained from the L2PMT, which corresponds to a Logical Block Address (LBA), to a second superblock of the superblocks, where the physical block address may represent a page (as indicated by a number) in the memory chip and the memory chip corresponding to a physical block, or represent a memory channel corresponding to a physical block, a memory chip of the memory channel, and a page (as indicated by a number) in the memory chip, or any other suitable way. For example, initially, the storage controller may be configured to record a plurality of pages of the memory chip D0 in the virtual block mapping table D0_ VMT according to values of the super blocks to which the respective pages are allocated, and set to correspond to the same super block; similar processing may be initially performed for other virtual block mappings. Thus, when step S40 of the control method of fig. 3 is executed, the initial virtual block mapping tables facilitate remapping the at least one selected super block to reduce the total effective number of pages of the selected super block. However, the implementation of the present invention is not limited by the above examples.

With respect to step S30, in one embodiment, the storage device controller determines the super block with the smallest total effective page number as the at least one selected super block according to the variation of the total effective page number of each super block. In another embodiment, the storage device controller determines at least one selected super block according to whether the total effective page number of each super block meets a judgment criterion. For example, the determination criterion is a threshold value of the total effective page number, and if the storage device controller determines that the total effective page number is a super block smaller than or equal to the threshold value of the total effective page number, the super block is taken as at least one selected super block.

Regarding step S40, please refer to fig. 7, which is a schematic flowchart of an embodiment of step S40 in fig. 3. In the illustrated embodiment, step S40 includes steps S41 and S45.

In step S41, it is determined whether the memory chip to which the first physical block of the plurality of physical blocks of the at least one selected super block belongs has a second physical block, and the effective page number of the second physical block is smaller than the effective page number of the first physical block, based on the internal block effective page count tables.

If it is determined that the memory chip to which the first physical block of the plurality of physical blocks of the at least one selected super block belongs has a second physical block with a valid page number smaller than that of the first physical block, at step S45, at least one of the plurality of virtual block pair maps is updated to remap the first physical block and the second physical block.

In some embodiments, if the number of selected super-blocks is two or more, the remapping operation may be performed for each selected super-block by using steps S41 and S45, wherein if a corresponding second physical block is not found in the execution of step S41 for a selected super-block, step S41 may be further continued for the remaining selected super-blocks.

Referring to fig. 8A, please refer to step S41, which is a diagram illustrating an embodiment of performing inner block remapping for a selected super block. As shown in fig. 8A, the selected super block (represented by SBX) is illustrated as a square matrix, and each grid in the square matrix represents an internal block of the selected super block, and a number is displayed in the grid to indicate the effective number of pages of the internal block. However, it should be noted that fig. 8A or other figures are merely schematic for convenience of illustration, and thus the implementation of the present invention is not limited by the examples or schematic herein, and may be implemented in various suitable software (e.g., data structures or databases), hardware or firmware.

For example, based on the internal block valid page count tables, the effective number of internal blocks (as represented by VPC) of the selected super-block SBX is 39, and in order to make the effective number of internal blocks of the selected super-block SBX smaller, the storage controller may be configured to select an appropriate number of physical blocks from the plurality of physical blocks (i.e., internal blocks) of the selected super-block SBX to perform steps S41 and S45, so as to achieve the effect of effectively reducing the effective number of internal blocks of the selected super-block SBX. For example, in one embodiment, the storage device controller may be configured to execute the step S41 when the number of valid pages found in the internal blocks of the selected super-block SBX is greater than or equal to the valid page number threshold (e.g., 10). For example, for fig. 8A, at least two internal blocks satisfy the threshold value of valid page number, wherein if the block naming manner in fig. 4 is used, the valid page numbers of the two internal blocks B _ D3 and B _ D10 are 15 and 12, respectively, and the memory chips of the two internal blocks B _ D3 and B _ D10 are D3 and D10, respectively. Thus, the threshold value of the number of valid pages can prevent finding an inappropriate number of internal blocks when implementing step S41, which can improve the performance efficiency of steps S41 and S45; conversely, if the step S41 is performed for the internal blocks with the valid page number of 1, 2 or 3, it is likely to cause waste of time and computational resources.

In addition, in step S41, it is determined whether there is an internal block with a smaller effective page number in the other super blocks, so as to remap the internal blocks B _ D3 and B _ D10 in step S45, i.e. perform an internal block swap, so that the remapped, selected super block SBX has a smaller total effective page number. For an internal block of the selected super-block SBX to be remapped, such as B _ D3 (or called the first physical block), it is necessary to find whether there is an internal block (or called the second physical block) with a smaller effective number of pages in the same memory chip D3 to which the internal block B _ D3 belongs, so as to maintain better performance.

In the example of fig. 8A, the internal block B _ D3 of another super-block SBZ belongs to the same memory chip D3 as the internal block B _ D3 of the selected super-block SBX, and the effective number of pages (e.g., 3) of the internal block B _ D3 of the block SBY is smaller than the effective number of pages (e.g., 15) of the internal block B _ D3 of the selected super-block SBX. Similarly, the internal block B _ D10 of another super-block SBY belongs to the same memory chip D10 as the internal block B _ D10 of the selected super-block SBX, and the effective number of pages (e.g., 0) of the internal block B _ D10 of the block SBY is smaller than the effective number of pages (e.g., 12) of the internal block B _ D10 of the selected super-block SBX. Thus, the inner block B _ D3 of the super block SBZ and the inner block B _ D10 of the super block SBY can be taken as the second physical block in step S41, and step S45 is further performed.

Referring to fig. 8B, in step S45, the first physical block (e.g., the internal block B _ D3 or B _ D10 of the super block SBX) and the second physical block (e.g., the internal block B _ D3 of the super block SBZ or the internal block B _ D10 of the super block SBY) are remapped by updating at least one of the plurality of virtual block mapping tables. In other words, the inner block B _ D3 of the super block SBX is exchanged with the inner block B _ D3 of the super block SBZ, and the inner block B _ D10 of the super block SBX is exchanged with the inner block B _ D10 of the super block SBY.

In one embodiment, in the step S45, the first physical block and the second physical block of the at least one selected super block (e.g., the internal block B _ D3 or B _ D10 of the super block SBX) and the virtual block map of the memory chip to which the second physical block of another super block (e.g., the internal block B _ D3 of the super block SBZ or the internal block B _ D10 of the super block SBY) belong are remapped. Referring to fig. 9A and 9B, fig. 9A is a schematic diagram of an embodiment of mapping relationship of internal blocks of a super block, and fig. 9B is a schematic diagram of an embodiment of mapping relationship of internal blocks of a super block after performing internal block remapping for a selected super block. In FIGS. 9A and 9B, each stripe pattern corresponds to a memory chip (e.g., D0-D16); the grid of each bar graph indicates the number of the super-block to which the block composed of at least one page in the corresponding memory chip belongs, if the value in the first grid of the bar graph corresponding to the memory chip D0 is 0, it indicates that the corresponding block belongs to the super-block SB0, and so on for the other blocks; for the convenience of understanding, the symbols of the super block corresponding to the original lattice, such as SB0, SBX, SBY, SBZ, etc., are shown at the leftmost side of the bar. Assume that the mapping relationship of the inner blocks of the super blocks SBX, SBY, SBZ at the beginning is as shown in fig. 9A, wherein the blocks respectively included in the super blocks SBX, SBY, SBZ (or the inner blocks of the super blocks) are illustrated by 3 horizontal straight lines crossing the plurality of bar patterns. After the remapping in step S45, the mapping relationship of the inner blocks of the remapped super-blocks SBX, SBY, SBZ is shown in fig. 9B, wherein the aforementioned 3 transversal lines directly changed into 3 transversal lines crossing the plurality of bar patterns indicate the blocks respectively included in the super-blocks SBX, SBY, SBZ (or the inner blocks of each super-block). Note that fig. 9A and 9B are schematic diagrams, and the implementation of the present invention is not limited by the above examples.

In one embodiment, the virtual block mapping table of the memory chip is updated to include data indicating mapping of the first physical block of the at least one selected super-block to a second physical block of another super-block. Referring to fig. 6 and fig. 9A and 9B again, the updated mapping relationship shown in fig. 9B can be realized by using the virtual block mapping table shown in fig. 6. For example, in the virtual block mapping table D3_ VMT corresponding to the memory chip D3, a page corresponding to the physical address of the internal block B _ D3 that can record the original superblock SBX of the memory chip D3 is mapped to SBZ, and a page corresponding to the physical address of the internal block B _ D3 that can record the original superblock SBZ is mapped to SBX; in the virtual block mapping table D10_ VMT corresponding to the memory chip D10, a page corresponding to the physical address of the internal block B _ D10 that can record the existing super block SBX of the memory chip D10 is mapped to the super block SBY, and a page corresponding to the physical address of the internal block B _ D10 that can record the existing super block SBY is mapped to the super block SBX. For example, the virtual block mapping table of each memory chip shown in fig. 6 may be configured to record the numbers of the memory chips, the numbers of the memory channels, the numbers of the super blocks corresponding to each physical page in the memory chips at the beginning, and the numbers of the super blocks corresponding to the memory chips after remapping, so as to facilitate the remapping. However, the implementation of the virtual block mapping table can be simplified or configured in other ways as appropriate, and thus the implementation of the present invention is not limited by the above examples.

Please refer to fig. 10, which is a schematic flowchart illustrating another embodiment of step S40 in fig. 3. As shown in step S110, determining a block (represented by block _ x) of the selected super block for a memory chip (represented by block _ x, starting from the memory chip D0, if the parameter DN is 0); for example, the corresponding block number (or block number) is looked up from the virtual block mapping table (as illustrated in fig. 6) corresponding to the memory chip D0. In step S120, determining whether the number of valid pages of the block _ x is greater than a threshold (e.g., 5, 10 or other threshold); if the number of valid pages of the block (e.g., block _ x) is greater than the threshold value, step S130 is performed. In step S130, a block (e.g., block _ y) with a smaller effective number of pages in the same memory chip is searched. In step S140, it is determined whether the block to be searched in step S130 can be found; if yes, go to step S150; if not, go to step S160. In step S150, block _ x and block _ y are remapped; such as the mapping shown in fig. 8B and 9B. As shown in step S160, the setting is directed to the next memory chip (e.g., the parameter DN is set to increment by one, such as by the virtual program code DN + +). As shown in step S170, it is determined whether all the memory chips have been processed, for example, whether the parameter DN is greater than the maximum number of memory chips (e.g., Q ═ 16 or 32, etc.); if yes, go to step S110; if not, stopping the process or executing other steps. Thus, step S40 based on the control method in fig. 4 can be implemented for the selected super block using the embodiment of fig. 10. If there are two or more super-blocks, step S40 can be performed repeatedly by using the embodiment of fig. 10.

Furthermore, in some embodiments, a non-transitory storage medium is provided, which records program codes for causing a computing device (such as the storage device shown in fig. 1 or 2) to execute a method for controlling the storage device by a storage device controller in the storage device, wherein the method includes any one or a combination of the embodiments of the method according to fig. 3. For example, the program code may be one or more programs or program modules, such as program code for implementing the steps S10-S50 of FIG. 3, steps S41 and S45 of FIG. 7, or steps S110-S170 of FIG. 10, that operate in conjunction and may be executed in any suitable order or in parallel. When the arithmetic device executes the program code, the arithmetic device can be caused to execute one embodiment of the control method based on the storage apparatus of fig. 3. The readable storage medium is, for example, firmware, ROM, RAM, memory card, optical information storage medium, magnetic information storage medium, or any other storage medium or memory, and the implementation manner of the present invention is not limited by this example.

In addition, in the above embodiments (fig. 1 and fig. 2) related to the memory device, at least one of the processing unit 110, the memory channel control unit 140, and the host interface unit 150, or a combination thereof, may be implemented by one or more circuits, such as a processor, a digital signal processor, or one or more circuits of a programmable integrated circuit (ic), such as a microcontroller, a Field Programmable Gate Array (FPGA), or an Application Specific Integrated Circuit (ASIC), or implemented by using a dedicated circuit or module. Furthermore, the memory channel control unit can also be implemented by software, such as a process, a thread, a program module, or other software. However, the implementation of the present invention is not limited by these examples. In addition, the aforementioned steps S41 and S45 in fig. 7 or the steps S130 and S140 in fig. 10 can also be implemented by hardware circuits, such as logic circuits or other suitable digital circuits, so as to improve the efficiency of searching other physical blocks with smaller effective number of pages.

Thus, the above embodiments provide a storage device, a control method of the storage device, and a storage medium, which can be used for an apparatus having a memory. Providing, by a storage device controller, a superblock valid page count table for a plurality of superblocks and a plurality of internal block valid page count tables for the plurality of superblocks, and providing a plurality of virtual block mapping tables for the plurality of memory chips to map a first superblock of the plurality of superblocks associated with a physical block address to a second superblock of the plurality of superblocks. And when the storage device needs to execute garbage collection, the effective number of pages of the super blocks is reduced by updating and mapping the selected super blocks to be subjected to garbage collection to the internal blocks, so that the garbage collection efficiency is improved.

Although the present invention has been described in terms of specific embodiments, numerous modifications, combinations, and variations can be made thereto by those of ordinary skill in the art without departing from the scope and spirit of the invention as set forth in the claims.

The above description is only an example of the present invention, and is not intended to limit the scope of the present invention.

Claims

1. A control method of a storage device including a storage device controller and a memory including a plurality of memory chips, characterized by comprising the steps of:

(a) providing, by the storage device controller, a super-block valid page count table for a plurality of super-blocks, wherein each super-block corresponds to a set of distinct, non-overlapping, plurality of entity blocks belonging to the plurality of memory chips, each entity block corresponds to a portion of a plurality of pages of a corresponding one of the plurality of memory chips, and the super-block valid page count table includes a total number of valid pages for the plurality of entity blocks corresponding to respective ones of the plurality of super-blocks, each internal block valid page count table corresponds to one of the plurality of super-blocks and includes a plurality of valid pages corresponding to the plurality of entity blocks of the super-block;

(b) providing, by the storage device controller, a plurality of virtual block mapping tables of the plurality of memory chips to map a first superblock of the plurality of superblocks associated with a physical block address to a second superblock of the plurality of superblocks;

(c) determining, by the storage device controller, at least one selected super block of the plurality of super blocks to be processed for a garbage collection operation based on the super block valid page count table;

(d) reducing, by the storage device controller, a total number of valid pages of the at least one selected super block by remapping the at least one selected super block based on the plurality of internal block valid page count tables and the plurality of virtual block mapping tables; and

(e) performing a garbage collection operation on the at least one selected super-block of the remap.

2. The method of controlling a storage device according to claim 1, wherein the step (d) includes:

(d1) determining whether a memory chip to which a first physical block of a plurality of physical blocks of the at least one selected super block belongs has a second physical block based on the internal block valid page count tables, wherein the valid page number of the second physical block is smaller than that of the first physical block; and

(d2) if it is determined that the memory chip to which the first physical block of the plurality of physical blocks of the at least one selected super block belongs has a second physical block with a valid page number less than that of the first physical block, remapping the first physical block and the second physical block by updating at least one of the plurality of virtual block mapping tables.

3. The method of claim 2, wherein said step (d1) is performed when the number of valid pages of said first physical block is greater than or equal to a valid page count threshold.

4. The method of controlling a storage apparatus according to claim 2, wherein in said step (d2),

remapping the first physical block and the second physical block of the at least one selected super-block by updating the virtual block mapping table of the memory chip to which the first physical block and the second physical block of another super-block belong.

5. The method of claim 4, wherein the virtual block mapping table of the memory chip is updated to include data indicating mapping of the first physical block of the at least one selected super-block to a second physical block of another super-block.

6. A storage medium characterized in that the storage medium records program codes for causing a storage device to execute the control method of the storage device according to any one of claims 1 to 5.

7. A storage device, comprising:

a memory comprising a plurality of memory chips; and

a storage device controller electrically connected to the memory and configured to control the memory to perform data access to the memory, wherein the storage device controller is configured to perform a plurality of operations comprising:

(a) providing, by the storage device controller, a superblock valid page count table for a plurality of superblocks, each superblock corresponding to a distinct, non-overlapping plurality of entity blocks belonging to a group of the plurality of memory chips, each entity block corresponding to a portion of a plurality of pages of a corresponding one of the plurality of memory chips, and including a total valid page count for the plurality of entity blocks corresponding to each of the plurality of superblocks, and a plurality of internal block valid page count tables for the plurality of superblocks, each internal block valid page count table corresponding to one of the plurality of superblocks and including a plurality of valid page counts corresponding to the plurality of entity blocks of the superblock;

8. The memory device of claim 7, wherein the act (d) comprises:

9. The memory device of claim 8, wherein said memory device controller performs said operation (d1) when the number of valid pages of said first physical block is greater than or equal to a valid page count threshold.

10. The memory device of claim 8, wherein in said operation (d2), the memory device controller remaps the first physical block and the second physical block of the at least one selected super-block by updating the virtual block mapping table of the memory chip to which the first physical block and the second physical block of another super-block belong.

11. The memory device of claim 10, wherein the memory device controller updates the virtual block mapping table of the memory chip to include data indicating mapping of the first physical block of the at least one selected super-block to a second physical block of another super-block.