CN114582298A - Gamma register configuration circuit for converting serial to parallel - Google Patents
Gamma register configuration circuit for converting serial to parallel Download PDFInfo
- Publication number
- CN114582298A CN114582298A CN202210262810.9A CN202210262810A CN114582298A CN 114582298 A CN114582298 A CN 114582298A CN 202210262810 A CN202210262810 A CN 202210262810A CN 114582298 A CN114582298 A CN 114582298A
- Authority
- CN
- China
- Prior art keywords
- value
- circuit
- critical value
- register
- configuration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 claims description 19
- 238000001914 filtration Methods 0.000 claims description 13
- 239000004065 semiconductor Substances 0.000 claims description 9
- 230000001747 exhibiting effect Effects 0.000 claims description 4
- 230000001360 synchronised effect Effects 0.000 claims description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 11
- 230000008569 process Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 238000006467 substitution reaction Methods 0.000 description 2
- 108010001267 Protein Subunits Proteins 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000010183 spectrum analysis Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/06—Adjustment of display parameters
- G09G2320/0673—Adjustment of display parameters for control of gamma adjustment, e.g. selecting another gamma curve
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention belongs to the technical field of circuits, and particularly relates to a gamma register configuration circuit for converting serial to parallel. It includes: an SR circuit and a configuration circuit; the SR circuit collects an initial pulse signal by a falling edge of a clock signal CLK and sequentially outputs 16 SR signals; the configuration circuit sequentially collects configuration buses DIN <6:0> based on 16 SR signals to obtain the configuration of different registers. The gamma registers are set by adopting serial input, namely configuration data of the registers are sequentially given by a configuration bus DIN <6:0>, the configuration bus is collected by a clock signal generated inside, different register configurations are obtained at different moments, the number of routing lines is reduced to 13, and the purpose of saving the layout area is achieved.
Description
Technical Field
The invention belongs to the technical field of circuits, and particularly relates to a gamma register configuration circuit for converting serial to parallel.
Background
The liquid crystal display, referred to as a liquid crystal panel for short, has the advantages of thin body, power saving, no radiation and the like, and is widely applied to liquid crystal televisions, smart phones, digital cameras, tablet computers, computer screens or notebook computer screens and the like, and is dominant in the field of flat panel display.
The liquid crystal panel has the working principle that liquid crystal molecules are filled between the thin film transistor array substrate and the color filter substrate, and driving voltage is applied to the two substrates to control the rotation direction of the liquid crystal molecules, so that light rays of the backlight module are refracted out to generate pictures. The manufacturing process of the liquid crystal panel generally includes a front-end array color film manufacturing process, a middle-end Cell manufacturing process, and a back-end module assembling process.
For the machine type that a circuit board (X/B) and a control circuit board (C/B) are separated and arranged along the transverse direction in a liquid crystal panel, the X/B and the C/B are separately delivered, errors exist in different C/B due to elements such as resistance and 1C, errors exist in analog power supply Voltage (VAA), reference Voltage (VREF), common voltage (VC0M) and the like of each C/B, and therefore the optimal VC0M voltage for matching different C/Bs in the same liquid crystal panel is different.
The related parameters of the optimal picture Flicker (Flicker) after the production line is adjusted to different C/Bs are stored in a Flash memory (Flash) of the X/B, different C/Bs are randomly matched during shipment, and the VAA voltage, the VREF voltage and the VC0M voltage of different C/Bs have differences, so that the picture Flicker conditions of the liquid crystal panel have differences due to the fact that different C/Bs are matched. When the liquid crystal cross voltage is changed at a frequency close to the response speed of human eyes, a viewer can feel the phenomenon of picture flicker due to the change of gray scale, and if the voltage is asymmetric seriously when the polarity is reversed, the picture flicker is more serious.
To eliminate flicker, the VC0M voltage needs to be regulated by a gamma circuit. Currently, registers in a gamma circuit are configured as parallel inputs, for example, 16 sets of gamma registers are configured, and all registers are configured as parallel inputs, and then the same number of level shifters as the number of the register sets are required to convert voltages into different voltage ranges.
Disclosure of Invention
In view of this, the main objective of the present invention is to provide a gamma register configuration circuit for serial-to-parallel conversion, in which the gamma registers are set by serial input, that is, the configuration data of the registers are sequentially given by a configuration bus DIN <6:0>, the configuration bus is collected by an internally generated clock signal, different register configurations are obtained at different times, the number of routing lines is reduced to 13, and the purpose of saving layout area is achieved.
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
a serial to parallel gamma register configuration circuit comprising: an SR circuit and a configuration circuit; the SR circuit collects an initial pulse signal by a falling edge of a clock signal CLK and sequentially outputs 16 SR signals; the configuration circuit collects configuration buses DIN <6:0> in sequence based on 16 SR signals to obtain the configuration of different registers.
Further, the circuit further comprises: a calibration device; the correcting device is respectively in signal connection with the configuration circuit and the SR circuit; the calibration device includes: the data acquisition part is used for acquiring register values of the registers in real time and acquiring the configuration of different registers acquired by the configuration circuit; the data adjusting part is configured to obtain a first critical value and a second critical value when the running value of the display and the color channel meet a standard threshold range based on the register value and the configuration; the operational values include: brightness, contrast, and saturation; the first critical value and the second critical value both comprise a running value and a register value, and the corresponding ranges of the first critical value and the second critical value are different; determining a connection relation expression in an operation value interval corresponding to the first critical value and the second critical value based on the first critical value and the second critical value; obtaining a register predicted value under a target operation value in a corresponding operation value interval based on the connection relation expression; correcting the predicted value of the register by adjusting the register value of the register to obtain a register ideal value and a corresponding third threshold point when the running value of the display reaches the target running value, wherein the third threshold point comprises the target running value and the register ideal value; dividing the operation value interval corresponding to the first critical value and the second critical value into two sections of new operation value intervals by using the third threshold value point, taking one threshold value point corresponding to two end points of the new operation value interval as a new first critical value, taking the other threshold value point as a new second critical value, returning to execute the linear prediction relational expression in the operation value interval corresponding to the first critical value and the second critical value based on the first critical value and the second critical value until obtaining the ideal register value of the operation value interval with preset quantity.
Further, the method for determining the connection relation expression in the operation value interval corresponding to the first critical value and the second critical value based on the first critical value and the second critical value includes: as a connection relation expression of the first critical value and the second critical value, the following formula is used:
(ii) a Where M is a first threshold, N is a second threshold, E is brightness, C is saturation, D is contrast, R is a red color channel value, G is a green color channel value, and B is a blue color channel value.
Further, the synchronous rectifier SR circuit includes: the SR switch is connected with the signal filtering circuit; the signal generating circuit is configured to generate an SR signal; the number of the SR switches is multiple, and each SR switch comprises a triode; the control circuit configured to generate a gate control signal to control the conduction state of the SR switch so as to minimize body diode conduction time and reduce or eliminate negative current across the SR switch; and the signal filtering circuit is configured to perform signal filtering on the generated gate control signal and eliminate the glitch of the gate control signal.
Further, the SR control circuit includes: a zero-crossing approximation circuit configured to generate an SR conduction signal indicative of the conduction state of the SR switch; and an Allowed Switching Window (ASW) circuit configured to generate an ASW signal based on a time difference between an off of a switch in the first stage and an end of the SR on signal.
Further, the signal filtering circuit includes: a low-pass filter, a current generator, an extended low-pass filter and a loop filter; the low-pass filter applies a primary voltage, and the extended low-pass filter applies a secondary voltage which is in a set proportion to the primary voltage; the loop filter applies a third voltage of the average value of the secondary voltage and the primary voltage; the gate control signal obtained by the low-pass filter passes through the loop filter and is output by the expansion low-pass filter; when the gate control signal passes through the low-pass filter, the high-pass filter and the loop filter, a first current is input to the current generator, and a second current is generated and acts on the low-pass filter, the extended low-pass filter and the loop filter.
Further, the set ratio is at least 1.5.
Further, the current generator is a current mirror circuit having a first semiconductor element showing a first conductivity at an input side and a second semiconductor element showing a second conductivity at the certain ratio to the first conductivity at an output side, the first current being an input and the second current being an output; the circuit element is the first semiconductor element.
Further, the frequency range of the clock signal CLK is: 144 Hz to 200 Hz.
Further, the frequency range of the clock signal CLK is: 500 Hz-800 Hz.
The gamma register configuration circuit for converting serial to parallel has the following beneficial effects: the gamma registers are set by adopting serial input, namely configuration data of the registers are sequentially given by a configuration bus DIN <6:0>, the configuration bus is collected by a clock signal generated inside, different register configurations are obtained at different moments, the number of routing lines is reduced to 13, and the purpose of saving the layout area is achieved.
Drawings
FIG. 1 is a schematic diagram of a prior art 16-bank gamma register;
FIG. 2 is a schematic structural diagram of an SR circuit of a gamma register configuration circuit for converting serial to parallel according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a configuration circuit of a gamma register configuration circuit for converting serial to parallel according to an embodiment of the present invention;
fig. 4 is a schematic diagram illustrating a layout area comparison between a gamma register configuration circuit for serial to parallel conversion and a gamma circuit for parallel input according to an embodiment of the present invention.
Detailed Description
The method of the present invention will be described in further detail below with reference to the accompanying drawings and embodiments of the invention.
Example 1
As shown in fig. 1, the registers in the current gamma circuit are configured as parallel inputs, and for example, with 16 sets of gamma registers, all registers are configured as parallel inputs, and the same number of level shifters as the number of register sets are required to convert the voltage into different voltage ranges.
The 16-bank gamma register configuration requires a large number of traces. On the basis, the same number of level shifters are needed to convert the voltage into different voltage ranges, so that the layout resource consumption is huge.
level shifter is a level shifter.
A serial to parallel gamma register configuration circuit comprising: an SR circuit and a configuration circuit; the SR circuit collects an initial pulse signal by a falling edge of a clock signal CLK and sequentially outputs 16 SR signals; the configuration circuit sequentially collects configuration buses DIN <6:0> based on 16 SR signals to obtain the configuration of different registers.
Example 2
On the basis of the above embodiment, the circuit further includes: a calibration device; the correcting device is respectively in signal connection with the configuration circuit and the SR circuit; the calibration device includes: the data acquisition part is used for acquiring register values of the registers in real time and acquiring the configuration of different registers acquired by the configuration circuit; the data adjusting part is configured to obtain a first critical value and a second critical value when the running value of the display and the color channel meet a standard threshold range based on the register value and the configuration; the operational values include: brightness, contrast, and saturation; the first critical value and the second critical value both comprise a running value and a register value, and the corresponding ranges of the first critical value and the second critical value are different; determining a connection relation expression in an operation value interval corresponding to the first critical value and the second critical value based on the first critical value and the second critical value; obtaining a register predicted value under a target operation value in a corresponding operation value interval based on the connection relation expression; correcting the predicted value of the register by adjusting the register value of the register to obtain a register ideal value and a corresponding third threshold point when the running value of the display reaches the target running value, wherein the third threshold point comprises the target running value and the register ideal value; dividing the operation value interval corresponding to the first critical value and the second critical value into two sections of new operation value intervals by using the third threshold value point, taking one threshold value point corresponding to two end points of the new operation value interval as a new first critical value, taking the other threshold value point as a new second critical value, returning to execute the linear prediction relational expression in the operation value interval corresponding to the first critical value and the second critical value based on the first critical value and the second critical value until obtaining the ideal register value of the operation value interval with preset quantity.
Example 3
On the basis of the above embodiment, the method for determining the connection relation expression in the operation value interval corresponding to the first critical value and the second critical value based on the first critical value and the second critical value includes: as a connection relational expression of the first critical value and the second critical value, the following formula is used:
(ii) a Where M is a first threshold, N is a second threshold, E is brightness, C is saturation, D is contrast, R is a red color channel value, G is a green color channel value, and B is a blue color channel value.
Example 4
On the basis of the above embodiment, the synchronous rectifier SR circuit includes: the SR switch is connected with the signal filtering circuit; the signal generating circuit is configured to generate an SR signal; the number of the SR switches is multiple, and each SR switch comprises a triode; the control circuit configured to generate a gate control signal to control the conduction state of the SR switch so as to minimize body diode conduction time and reduce or eliminate negative current across the SR switch; the signal filtering circuit is configured to perform signal filtering on the generated gate control signal and eliminate the glitch of the gate control signal.
Example 5
On the basis of the above embodiment, the SR control circuit includes: a zero-crossing approximation circuit configured to generate an SR conduction signal indicative of the conduction state of the SR switch; and an Allowed Switching Window (ASW) circuit configured to generate an ASW signal based on a time difference between an off of a switch in the first stage and an end of the SR on signal.
Example 6
On the basis of the above embodiment, the signal filtering circuit includes: a low-pass filter, a current generator, an extended low-pass filter and a loop filter; the low-pass filter applies a primary voltage, and the extended low-pass filter applies a secondary voltage which is in a set proportion to the primary voltage; the loop filter applies a third voltage of the average value of the secondary voltage and the primary voltage; the gate control signal obtained by the low-pass filter passes through the loop filter and is output by the expansion low-pass filter; when the gate control signal passes through the low-pass filter, the high-pass filter and the loop filter, a first current is input to the current generator to generate a second current, and the second current acts on the low-pass filter, the extended low-pass filter and the loop filter.
Specifically, the filter is a frequency-selective device that passes certain frequency components of the signal while significantly attenuating other frequency components. By using the frequency selection function of the filter, interference noise can be filtered out or spectrum analysis can be carried out. In other words, any device or system that can pass a specific frequency component of a signal and greatly attenuate or suppress other frequency components is called a filter. The filter is a device for filtering waves. "wave" is a very broad physical concept, and in the field of electronics, is narrowly limited to refer to a process that describes the fluctuation over time of values of various physical quantities. This process is converted into a time function of voltage or current, called time waveform of various physical quantities, or called signal, by the action of various sensors. Since the argument time is continuously valued, it is called a continuous time Signal, which is also conventionally called an Analog Signal (Analog Signal).
Example 7
On the basis of the above embodiment, the set ratio is at least 1.5.
Example 8
In the above embodiment, the current generator is a current mirror circuit having, on an input side, a first semiconductor element exhibiting a first conductivity and, on an output side, a second semiconductor element exhibiting a second conductivity at the certain ratio to the first conductivity, the first current being an input and the second current being an output; the circuit element is the first semiconductor element.
Example 9
On the basis of the previous embodiment, the frequency range of the clock signal CLK is: 144 Hz to 200 Hz.
Specifically, the Clock Signal (Clock Signal) is the basis of sequential logic, which is a Signal quantity having a fixed period and being independent of operation, and is used to determine when the state in the logic unit is updated. The clock signal has a fixed clock frequency, which is the inverse of the clock period. In electronic, especially synchronous digital circuits of signals, the clock signal is a high and low state between special signal oscillations of the signal, the digital circuit of the signal acts coordinately like a metronome, and the digital clock signal is basically a square wave voltage.
Example 10
On the basis of the previous embodiment, the frequency range of the clock signal CLK is: 500 Hz-800 Hz.
Referring to fig. 2, the SR circuit collects an initial pulse signal from a falling edge of the clock signal CLK, and sequentially outputs 16 SR signals.
Referring to fig. 3, 16 SR signals sequentially collect configuration buses DIN <6:0> to obtain configurations of different registers, thereby implementing serial-to-parallel conversion.
Referring to fig. 4, the invention aims to reduce the layout area, and according to the existing data, two circuits of the same gamma main body architecture are adopted, one circuit is used for parallel input of a register, the other circuit is used for serial-to-parallel input of the register, the layout areas of the two circuits are 1266.64umx296.81um and 1343.16umx205.748um respectively, the area of the latter circuit is reduced by about 25%, and the effect is obvious.
It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working process and related description of the system described above may refer to the corresponding process in the foregoing method embodiments, and will not be described herein again.
It should be noted that, the system provided in the foregoing embodiment is only illustrated by dividing the functional units, and in practical applications, the functions may be distributed by different functional units according to needs, that is, the units or steps in the embodiments of the present invention are further decomposed or combined, for example, the units in the foregoing embodiment may be combined into one unit, or may be further decomposed into multiple sub-units, so as to complete all or the functions of the units described above. The names of the units and steps involved in the embodiments of the present invention are only for distinguishing the units or steps, and are not to be construed as unduly limiting the present invention.
It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes and related descriptions of the storage device and the processing device described above may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
Those of skill in the art would appreciate that the various illustrative elements, method steps, described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that programs corresponding to the elements, method steps may be located in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. To clearly illustrate this interchangeability of electronic hardware and software, various illustrative components and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as electronic hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The terms "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.
The terms "comprises," "comprising," or any other similar term are intended to cover a non-exclusive inclusion, such that a process, method, article, or unit/apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or unit/apparatus.
So far, the technical solutions of the present invention have been described in connection with the preferred embodiments shown in the drawings, but it is easily understood by those skilled in the art that the scope of the present invention is obviously not limited to these specific embodiments. Equivalent changes or substitutions of related technical marks can be made by those skilled in the art without departing from the principle of the invention, and the technical scheme after the changes or substitutions can fall into the protection scope of the invention.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.
Claims (10)
1. A circuit for configuring a gamma register from serial to parallel, comprising: an SR circuit and a configuration circuit; the SR circuit collects an initial pulse signal by a falling edge of a clock signal CLK and sequentially outputs 16 SR signals; the configuration circuit sequentially collects configuration buses DIN <6:0> based on 16 SR signals to obtain the configuration of different registers.
2. The circuit of claim 1, wherein the circuit further comprises: a calibration device; the correcting device is respectively in signal connection with the configuration circuit and the SR circuit; the calibration device includes: the data acquisition part is used for acquiring register values of the registers in real time and acquiring the configuration of different registers acquired by the configuration circuit; the data adjusting part is configured to obtain a first critical value and a second critical value when the running value of the display and the color channel meet a standard threshold range based on the register value and the configuration; the operational values include: brightness, contrast, and saturation; the first critical value and the second critical value both comprise a running value and a register value, and the corresponding ranges of the first critical value and the second critical value are different; determining a connection relation expression in an operation value interval corresponding to the first critical value and the second critical value based on the first critical value and the second critical value; obtaining a register predicted value under a target operation value in a corresponding operation value interval based on the connection relation expression; correcting the predicted value of the register by adjusting the register value of the register to obtain a register ideal value and a corresponding third threshold point when the running value of the display reaches the target running value, wherein the third threshold point comprises the target running value and the register ideal value; dividing the operation value interval corresponding to the first critical value and the second critical value into two sections of new operation value intervals by using the third threshold value point, taking one threshold value point corresponding to two end points of the new operation value interval as a new first critical value, taking the other threshold value point as a new second critical value, returning to execute the linear prediction relational expression in the operation value interval corresponding to the first critical value and the second critical value based on the first critical value and the second critical value until obtaining the ideal register value of the operation value interval with preset quantity.
3. The circuit of claim 2, wherein the method for determining the connection relation expression within the operation value interval corresponding to the first critical value and the second critical value based on the first critical value and the second critical value comprises: as a connection relational expression of the first critical value and the second critical value, the following formula is used:
where M is a first threshold, N is a second threshold, E is brightness, C is saturation, D is contrast, R is a red color channel value, G is a green color channel value, and B is a blue color channel value.
4. The circuit of claim 3, wherein the synchronous rectifier SR circuit comprises: the SR switch is connected with the signal filtering circuit; the signal generating circuit is configured to generate an SR signal; the number of the SR switches is multiple, and each SR switch comprises a triode; the control circuit configured to generate a gate control signal to control the conduction state of the SR switch so as to minimize body diode conduction time and reduce or eliminate negative current across the SR switch; and the signal filtering circuit is configured to perform signal filtering on the generated gate control signal and eliminate the glitch of the gate control signal.
5. The circuit of claim 4, wherein the SR control circuit comprises: a zero-crossing approximation circuit configured to generate an SR conduction signal indicative of the conduction state of the SR switch; and an Allowed Switching Window (ASW) circuit configured to generate an ASW signal based on a time difference between an off of a switch in the first stage and an end of the SR on signal.
6. The circuit of claim 5, wherein the signal filtering circuit comprises: a low-pass filter, a current generator, an extended low-pass filter and a loop filter; the low-pass filter applies a primary voltage, and the extended low-pass filter applies a secondary voltage which is in a set proportion to the primary voltage; the loop filter applies a third voltage of the average value of the secondary voltage and the primary voltage; the gate control signal obtained by the low-pass filter passes through the loop filter and is output by the expansion low-pass filter; when the gate control signal passes through the low-pass filter, the high-pass filter and the loop filter, a first current is input to the current generator to generate a second current, and the second current acts on the low-pass filter, the extended low-pass filter and the loop filter.
7. The circuit of claim 6, wherein the set ratio is at least 1.5.
8. The circuit according to claim 7, wherein the current generator is a current mirror circuit having a first semiconductor element exhibiting a first conductivity on an input side and a second semiconductor element exhibiting a second conductivity in the certain ratio to the first conductivity on an output side, the first current being an input and the second current being an output; the circuit element is the first semiconductor element.
9. The circuit of claim 8, wherein the frequency range of the clock signal CLK is: 144 Hz to 200 Hz.
10. The circuit of claim 8, wherein the frequency range of the clock signal CLK is: 500 Hz-800 Hz.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210262810.9A CN114582298A (en) | 2022-03-17 | 2022-03-17 | Gamma register configuration circuit for converting serial to parallel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210262810.9A CN114582298A (en) | 2022-03-17 | 2022-03-17 | Gamma register configuration circuit for converting serial to parallel |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114582298A true CN114582298A (en) | 2022-06-03 |
Family
ID=81780857
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210262810.9A Pending CN114582298A (en) | 2022-03-17 | 2022-03-17 | Gamma register configuration circuit for converting serial to parallel |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114582298A (en) |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56145426A (en) * | 1980-04-11 | 1981-11-12 | Sanyo Electric Co Ltd | Serial data transferring method |
| CN1613185A (en) * | 2002-05-22 | 2005-05-04 | 松下电器产业株式会社 | Low-pass filter,feedback system and semiconductor integrated circuit |
| CN101257756A (en) * | 2008-04-07 | 2008-09-03 | 杭州华三通信技术有限公司 | Lighting system and method |
| CN102893478A (en) * | 2011-04-25 | 2013-01-23 | 快捷半导体(苏州)有限公司 | Synchronous rectifier control techniques for a resonant converter |
| CN103888147A (en) * | 2014-04-09 | 2014-06-25 | 龙迅半导体科技(合肥)有限公司 | Serial-to-parallel conversion circuit, serial-to-parallel converter and serial-to-parallel conversion system |
| CN107222219A (en) * | 2017-06-28 | 2017-09-29 | 中国电子科技集团公司第五十八研究所 | Possesses the high speed serial parallel exchange circuit of frame alignment function |
| CN108337582A (en) * | 2017-12-29 | 2018-07-27 | 武汉船舶通信研究所（中国船舶重工集团公司第七二二研究所） | Time division multiplex switching system based on field programmable gate array |
| CN109062836A (en) * | 2018-08-17 | 2018-12-21 | 苏州易德龙科技股份有限公司 | A kind of the data serial-parallel convertor and method of low cost |
| CN111223437A (en) * | 2020-03-11 | 2020-06-02 | 昆山国显光电有限公司 | Gamma register calibration method, gamma register calibration device and display device |
| CN113282531A (en) * | 2021-05-28 | 2021-08-20 | 福州大学 | Two-port serial data receiving and transmitting circuit and method based on pulse triggering |
-
2022
- 2022-03-17 CN CN202210262810.9A patent/CN114582298A/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56145426A (en) * | 1980-04-11 | 1981-11-12 | Sanyo Electric Co Ltd | Serial data transferring method |
| CN1613185A (en) * | 2002-05-22 | 2005-05-04 | 松下电器产业株式会社 | Low-pass filter,feedback system and semiconductor integrated circuit |
| CN101257756A (en) * | 2008-04-07 | 2008-09-03 | 杭州华三通信技术有限公司 | Lighting system and method |
| CN102893478A (en) * | 2011-04-25 | 2013-01-23 | 快捷半导体(苏州)有限公司 | Synchronous rectifier control techniques for a resonant converter |
| CN103888147A (en) * | 2014-04-09 | 2014-06-25 | 龙迅半导体科技(合肥)有限公司 | Serial-to-parallel conversion circuit, serial-to-parallel converter and serial-to-parallel conversion system |
| CN107222219A (en) * | 2017-06-28 | 2017-09-29 | 中国电子科技集团公司第五十八研究所 | Possesses the high speed serial parallel exchange circuit of frame alignment function |
| CN108337582A (en) * | 2017-12-29 | 2018-07-27 | 武汉船舶通信研究所（中国船舶重工集团公司第七二二研究所） | Time division multiplex switching system based on field programmable gate array |
| CN109062836A (en) * | 2018-08-17 | 2018-12-21 | 苏州易德龙科技股份有限公司 | A kind of the data serial-parallel convertor and method of low cost |
| CN111223437A (en) * | 2020-03-11 | 2020-06-02 | 昆山国显光电有限公司 | Gamma register calibration method, gamma register calibration device and display device |
| CN113282531A (en) * | 2021-05-28 | 2021-08-20 | 福州大学 | Two-port serial data receiving and transmitting circuit and method based on pulse triggering |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9377915B2 (en) | Capacitive touch sensor | |
| KR102277072B1 (en) | GOA circuit driving architecture | |
| US8446354B2 (en) | Liquid crystal display capable of compensating common voltage signal thereof | |
| US20140168044A1 (en) | Shift register unit, gate driving circuit and display device | |
| EP1304791A1 (en) | Source voltage conversion circuit and its control method, display, and portable terminal | |
| US20140015819A1 (en) | Method for Driving Display Device and Display Device | |
| KR20030017430A (en) | A driving circuit of electrooptic panel, driving method, electrooptic apparatus and electronic equipment | |
| CN106875890A (en) | Array base palte, display panel, display device and driving method | |
| GB2495607A (en) | Liquid crystal display device driving circuitry with reduced area PCB | |
| CN103714774B (en) | Ramp generator and signal generator, array base palte and display device | |
| JP2008065333A (en) | Array panel and its driving method | |
| US10522065B2 (en) | Transmitting electrode scan driving unit, driving circuit, driving method and array substrate | |
| GB2188471A (en) | L C D devices | |
| CN1224279A (en) | Low power liquid-crystal display driver | |
| CN104123918B (en) | Shift register and liquid crystal indicator | |
| CN105448269A (en) | Shift register unit, grid driving circuit and display apparatus | |
| JP2005326812A (en) | Reference data generation apparatus and method for correcting video signal | |
| CN104240661A (en) | Polarity inversion driving method, polarity inversion driving device and display device | |
| CN110660370A (en) | Signal adjusting circuit and display device | |
| US11379079B2 (en) | Touch drive method, touch display device, and electronic equipment | |
| US8106863B2 (en) | Common voltage generating circuit having square wave generating unit and liquid crystal display using same | |
| US8300003B2 (en) | Driver for reducing a noise, display device having the driver, and method thereof | |
| CN105913055B (en) | Fingerprint detection unit and its driving method, display device | |
| CN103700334B (en) | Ramp signal generation circuit, signal generator, array substrate and display device | |
| KR20100006320A (en) | Apparatus and method for driving light source in back light unit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20220603 |