CN114579329A

CN114579329A - Data processing method and device applied to server

Info

Publication number: CN114579329A
Application number: CN202210114212.7A
Authority: CN
Inventors: 蒋小安
Original assignee: Alibaba China Co Ltd
Current assignee: Alibaba China Co Ltd
Priority date: 2022-01-30
Filing date: 2022-01-30
Publication date: 2022-06-03

Abstract

The embodiment of the specification provides a data processing method and a data processing device applied to a server, wherein the data processing method applied to the server comprises the following steps: determining attribute information of a management control module in the server; determining attribute information of a data sharing area according to the attribute information of the management control module; dividing the data sharing area from the video memory space of the management control module based on the attribute information of the data sharing area; and exchanging data with the management control module according to the data sharing area, thereby avoiding the problems of low communication efficiency, poor stability and the like caused by adopting a synchronous transmission mode.

Description

Data processing method and device applied to server

Technical Field

The embodiment of the specification relates to the technical field of computers, in particular to a data processing method applied to a server.

Background

With the continuous development of computer technology, in the field of servers, a synchronous transmission mode is mainly adopted for communication between a CPU and a management control module, such as a BMC chip, in a server, and the synchronous transmission mode has low communication efficiency and poor stability.

Disclosure of Invention

In view of this, the embodiments of the present specification provide a data processing method applied to a server. One or more embodiments of the present specification also relate to a data processing apparatus, a computing device, a computer-readable storage medium, and a computer program applied to a server, so as to solve technical deficiencies in the prior art.

According to a first aspect of embodiments of the present specification, there is provided a data processing method applied to a server, including:

determining attribute information of a management control module in the server;

determining attribute information of a data sharing area according to the attribute information of the management control module;

dividing the data sharing area from the video memory space of the management control module based on the attribute information of the data sharing area;

and exchanging data with the management control module according to the data sharing area.

According to a second aspect of embodiments herein, there is provided a data processing apparatus applied to a server, including:

a first determination module configured to determine attribute information of a management control module in the server;

a second determination module configured to determine attribute information of a data sharing area according to the attribute information of the management control module;

a dividing module configured to divide the data sharing area from a video memory space of the management control module based on attribute information of the data sharing area;

and the data exchange module is configured to exchange data with the management control module according to the data sharing area.

According to a third aspect of embodiments herein, there is provided a data processing method applied to a server, including:

acquiring current state information of a video memory space;

under the condition that a data sharing area is determined to exist based on the current state information, exchanging data with an operation control module in the server according to the data sharing area;

the data sharing area is an area which is divided from the video memory space by the operation control module based on the attribute information of the data sharing area.

According to a fourth aspect of embodiments herein, there is provided a data processing apparatus applied to a server, including:

the acquisition module is configured to acquire current state information of the video memory space;

the data exchange module is configured to exchange data with the operation control module in the server according to the data sharing area under the condition that the existence of the data sharing area is determined based on the current state information;

According to a fifth aspect of the embodiments of the present specification, there is provided a data processing system applied to a server, the system including an arithmetic control module in the server, a management control module in the server, wherein,

the operation control module is configured to determine attribute information of the management control module, determine attribute information of a data sharing area according to the attribute information of the management control module, divide the data sharing area from a video memory space of the management control module based on the attribute information of the data sharing area, and exchange data with the management control module according to the data sharing area;

the management control module is configured to exchange data with the operation control module according to the data sharing area.

According to a sixth aspect of embodiments herein, there is provided a computing device comprising:

a memory and a processor;

the memory is used for storing computer-executable instructions, and the processor is used for executing the computer-executable instructions, and the computer-executable instructions realize the steps of the data processing method applied to the server when being executed by the processor.

According to a seventh aspect of embodiments herein, there is provided a computer-readable storage medium storing computer-executable instructions that, when executed by a processor, implement the steps of the data processing method applied to a server.

According to an eighth aspect of embodiments herein, there is provided a computer program, wherein the computer program, when executed in a computer, causes the computer to perform the steps of the data processing method applied to a server.

The data processing method applied to the server comprises the steps of determining attribute information of a management control module in the server; determining attribute information of a data sharing area according to the attribute information of the management control module; dividing the data sharing area from the video memory space of the management control module based on the attribute information of the data sharing area; and exchanging data with the management control module according to the data sharing area.

Specifically, the method divides a data sharing area in a video memory space of a management control module, and performs asynchronous data exchange with the management control module based on the data sharing area, so that the problems of low communication efficiency, poor stability and the like caused by a synchronous transmission mode are solved, and when a large amount of information needs to be transmitted between the management control module and the management control module, the information needing to be transmitted can be written into the data sharing area in advance in an asynchronous transmission mode, so that the required information can be quickly acquired from the data sharing area subsequently, the problem of long communication time is solved, and the negative influence of long communication time consumption on the starting speed is further reduced.

Drawings

Fig. 1 is a flowchart of a data processing method applied to a server according to an embodiment of the present specification;

fig. 2 is a schematic diagram of memory mapping in a data processing method applied to a server according to an embodiment of the present disclosure;

FIG. 3 is a flowchart illustrating a processing procedure of a data processing method applied to a server according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of a data processing apparatus applied to a server according to an embodiment of the present specification;

FIG. 5 is a flow chart of another data processing method applied to a server according to one embodiment of the present disclosure;

fig. 6 is a schematic structural diagram of another data processing apparatus applied to a server according to an embodiment of the present disclosure;

FIG. 7 is a block diagram of a data processing system implemented on a server according to one embodiment of the present disclosure;

fig. 8 is a block diagram of a computing device according to an embodiment of the present disclosure.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present description. This description may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein, as those skilled in the art will be able to make and use the present disclosure without departing from the spirit and scope of the present disclosure.

The terminology used in the description of the one or more embodiments is for the purpose of describing the particular embodiments only and is not intended to be limiting of the description of the one or more embodiments. As used in one or more embodiments of the present specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used in one or more embodiments of the present specification refers to and encompasses any and all possible combinations of one or more of the associated listed items.

It will be understood that, although the terms first, second, etc. may be used herein in one or more embodiments to describe various information, these information should not be limited by these terms. These terms are only used to distinguish one type of information from another. For example, a first can be termed a second and, similarly, a second can be termed a first without departing from the scope of one or more embodiments of the present description. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.

First, the noun terms referred to in one or more embodiments of the present specification are explained.

BMC: a Baseboard Management Controller (BMC), also called a BMC chip.

BIOS: basic Input Output System (BIOS).

KCS: style of Keyboard Controller (Keyboard Controller Style).

Pci (peripheral Component interconnect): peripheral component interconnect standards.

Agp (accelererate graphic port): the graphics interface is accelerated.

With the continuous development of computer technology, the current CPU and BMC communication in the server field is mainly based on the KCS mode, and this communication mode adopts synchronous transmission, resulting in low transmission efficiency and poor stability of the mode, and when a large amount of log information needs to be transmitted, the transmission consumes a long time, which may cause a large impact on the startup speed.

In this case, data exchange may be performed between the BMC and the BIOS having a P2Abridge (P2A bridge) interface, but the P2Abridge interface is a debug interface reserved for development and debugging, and then when the BMC and the BIOS access the memory space of the BMC through the P2Abridge interface, a great potential safety hazard may exist. In addition, the scheme only aims at data exchange between the CPU and the BMC, and after the BIOS is executed, the CPU and the BMC cannot exchange data through the memory space of the BMC, so that the problem of communication between the CPU and the BMC cannot be solved.

In view of this, in the present specification, there are provided two data processing methods applied to a server, and the present specification relates to two data processing apparatuses applied to a server, a data processing system applied to a server, a computing device, a computer-readable storage medium, and a computer program, which are described in detail one by one in the following embodiments.

Fig. 1 is a flowchart illustrating a data processing method applied to a server according to an embodiment of the present specification, which includes the following steps.

Step 102: determining attribute information of a management control module in the server.

In practical applications, the data processing method applied to the server provided in the present specification can be applied to an arithmetic control module that needs to exchange data with a management control module in the server, for example, the arithmetic control module may be a CPU (central processing unit), and the CPU may be a CPU in the server. The operation control module may be a module in a server, the server includes a management control module and an operation control module, and the system may be understood as a system capable of exchanging data between the control module and the operation control module.

The management control module can be understood as a module capable of dividing a data sharing area from a video memory space of the management control module; for example, a BMC chip in a server, a graphics card in a server; in an embodiment provided in this specification, the management control module may be a BMC chip. In order to avoid redundant description, the data processing method applied to the server provided by the present application is explained by taking the management control module as the BMC chip, the display card, and the operation control module in the server as an example of the CPU that needs to exchange data with the management control module. In practical application, the display card of the server can be integrated in the BMC chip, and the BMC chip allocates an area for the display card from its own memory space as a display memory area. Based on this, the subsequent CPU can isolate a part of memory from the video memory space of the BMC chip for the CPU and the BMC to perform data sharing.

The attribute information of the management control module can be understood as information such as specification and model of the management control module. When the management control module is a BMC chip, the attribute information of the management control module may be information such as a specification and a model of the BMC chip. The specification of the BMC chip includes, but is not limited to, a memory size of the BMC chip, an interface type of the BMC chip, and the like. In the case that the management control module is a display card, the attribute information of the management control module may be information such as specification and model of the display card. The specification of the video card includes, but is not limited to, a video memory size of the video card, an interface type of the video card, and the like.

Specifically, the CPU can determine attribute information of the control management module. The mode of determining the attribute information of the control management module by the CPU may be set according to an actual application scenario, which is not specifically limited in this specification, for example, the CPU may read the attribute information of the control management module from an information storage module storing the attribute information of the control management module. The information storage module may be a module capable of storing attribute information of the control management module, such as a register and a Cache (Cache).

The following takes the application of the data processing method applied to the server provided in the present specification to the division of the data sharing area as an example, and further description is made for determining the attribute information of the management control module in the server. And when the management control module is a BMC chip, the CPU can acquire the model information of the BMC chip. And under the condition that the management control module is the display card, the CPU can acquire the model information of the display card.

In practical application, the operation of acquiring the model information of the BMC chip or the model information of the graphics card by the CPU is realized by running the BIOS running in the CPU. That is, the BIOS running in the CPU can acquire the model information of the BMC chip or acquire the model information of the graphics card.

Step 104: and determining the attribute information of the data sharing area according to the attribute information of the management control module.

The data sharing area may be understood as an area capable of asynchronous data communication with the management control module. For example, the area where data interaction is performed between the CPU and the BMC chip.

The attribute information of the data sharing area may be understood as information such as the size of the data sharing area to be divided, the position in the video memory, and the like. In practical applications, the area design object can design the attribute information of the data sharing area in advance based on the attribute information of the management control module. For example, when the attribute information of the management control module is the model of the BMC chip, the area design object can design the data interaction area (for example, 32MB, 64MB, and the like) with different sizes and set the position of the data interaction area in the video memory of the BMC chip based on the chips with different models. The area design object may be understood as an object capable of designing attribute information of the data sharing area, for example, an artificial intelligence model, an intelligent robot, or the like.

Specifically, after determining the attribute information of the management control module, the CPU can determine the attribute information of the data sharing area corresponding to the management control module based on the attribute information of the management control module, and subsequently partition the data sharing area from the video memory space of the management control module based on the attribute information of the data sharing area.

In practical application, the manner in which the CPU determines the attribute information of the data sharing area may be set according to a practical application scenario, which is not specifically limited in this specification, for example, the CPU may read the attribute information of the control management module from an information storage module that stores the attribute information of the data sharing area. The information storage module may be a module capable of storing attribute information of the data sharing area, such as a register and a Cache (Cache). Alternatively, the CPU may request acquisition of attribute information of the data sharing area corresponding to the management control module from the area design object based on the attribute information of the management control module.

Along the above example, the BIOS operating in the CPU can acquire the attribute information of the data interaction area to be divided, which corresponds to the BMC chip, after acquiring the model of the BMC chip, or the BIOS operating in the CPU can acquire the attribute information of the data interaction area, which corresponds to the display card, after acquiring the model of the display card, where the attribute information of the data interaction area may be the size (32MB) of the data interaction area, the position of the data interaction area in the display memory space, and the like.

Step 106: and based on the attribute information of the data sharing area, dividing the data sharing area from the video memory space of the management control module.

Specifically, the CPU can partition a block of area as the data sharing area from the memory space in the management control module based on the attribute information when determining the attribute information of the data sharing area.

Along with the above example, in the case that the management control module is a video card, after determining the attribute information of the information interaction area, the BIOS running in the CPU can partition a data interaction area with a size of 32MB from a specific position of the video memory space of the video card based on the attribute information.

Under the condition that the management control module is a BMC chip, after determining the attribute information of the information interaction area, the BIOS running in the CPU can divide a data interaction area with the size of 32MB from the specific position in the video memory space of the BMC chip based on the attribute information.

In practical application, the display card of the server may be integrated in the BMC chip, and based on this, before the data interaction region is partitioned from the memory space of the BMC chip, the BMC chip needs to allocate a storage region as a display memory space for the display card from the memory space of the BMC chip. Therefore, the data interaction area can be subsequently divided from the video memory space of the BMC chip.

In an embodiment provided in this specification, the step of dividing the data sharing area based on the attribute information of the data sharing area to be divided may also be implemented based on a space management submodule in the management control module, and a specific implementation manner is as follows.

The dividing the data sharing area from the video memory space of the management control module based on the attribute information of the data sharing area includes:

determining a space management submodule in the management control module based on the attribute information of the management control module;

and based on the attribute information of the data sharing area and the space management submodule, the data sharing area is divided from the video memory space of the management control module.

The space management submodule may be understood as a module capable of performing management operation on the video memory space, for example, a register disposed on the management control module.

Specifically, the CPU needs to determine a space management submodule in the management control module based on the attribute information of the management control module before dividing the data sharing area. In practical application, when the management control module is a BMC chip, the registers deployed on the BMC chip are different due to the difference between the BMC chips, and based on this, the model of the BMC chip needs to be determined, and the registers deployed on the BMC chip is determined based on the model.

After the space management submodule is determined, the CPU can divide an area from the video memory space of the management control module as a data sharing area based on the attribute information of the data sharing area and the space management submodule. For example, when the space management submodule is a register, a block of area can be divided as a data interactive area from the video memory space of the BMC chip based on the register and the attribute information of the data interactive area.

In a specific implementation process, the dividing the data sharing area from the video memory space of the management control module based on the attribute information of the data sharing area and the space management submodule includes:

determining the operating state of the space management submodule;

when the running state is closed, adjusting the running state of the space management submodule to be opened based on the attribute information of the data sharing area;

and based on the space management submodule with the operating state of being opened, the data sharing area is divided from the video memory space.

In the case that the space management submodule is a register, the operating state of the space management submodule may be understood as an on state or an off state of the register.

Specifically, in the process of dividing the data sharing area, the CPU needs to obtain the operating state of the space management submodule in the management control module, adjust the operating state of the space management submodule to be on based on the attribute information of the data sharing area when the operating state of the space management submodule is off, and divide the data sharing area from the video memory space based on the space management submodule whose operating state is on.

Along with the above example, the BIOS operating in the CPU can acquire one or more registers in the BMC chip that are responsible for the shared memory function, and acquire the operating state of the register. And under the condition that the running state of the register is determined to be closed, selecting to open a specific register from a plurality of registers according to the attribute information of the data interaction area. The specific register is determined based on attribute information such as the size of the data interaction area and/or the position of the data interaction area in the video memory.

In a specific implementation process, the BMC chip can support a shared memory function of dividing a plurality of types of data interaction areas from a video memory space of the BMC chip, where the plurality of types of data interaction areas may be a data interaction area with a size of 32MB, a data interaction area with a size of 64MB, and a data interaction area with a size of 128 MB. The memory sharing function is realized by a register which is arranged in the BMC chip and is responsible for the memory sharing function, and the memory sharing function can be understood as a function of dividing a part of space from a video memory space of the BMC chip as a data interaction area. For example, the BMC chip supports three types of data interaction areas, namely 32MB, 64MB and 128MB, which are divided from the video memory. And support three types of data interaction area to realize, 4 registers configured on the BMC chip. When 1 register is started, the video memory is divided into a data interaction area with the size of 32MB, and the subsequent CPU can communicate with the BMC chip based on the data interaction area with the size of 32 MB. Similarly, when 2 registers are opened, the video memory is divided into a data interaction area with the size of 64 MB; when 4 registers are turned on, the video memory is divided into a data exchange area with a size of 128 MB.

Or, the BMC chip supports three types of data interaction areas which are divided from the video memory and have the sizes of 32MB, 64MB and 128 MB. And the data interaction area supporting three types is realized by 3 registers (register A, register B and register C) configured on the BMC chip. When the register A is started, the video memory is divided into a data interaction area with the size of 32 MB; when the register B is started, the video memory is divided into a data interaction area with the size of 64 MB; when the register C is turned on, the video memory is divided into a data interactive area with a size of 128 MB.

Based on this, after the BIOS running in the CPU determines the register in the BMC chip that is responsible for sharing the memory function, 1 register in the BMC chip can be started based on the size (32MB) of the data interaction area, or the register a in the BMC chip can be started based on the size (32MB) of the data interaction area.

Starting 1 register in the BMC chip or starting the register A in the BMC chip based on the size of the data interaction area (32 MB). A space with the size of 32MB can be divided from a video memory space in the BMC chip based on the started register to serve as a data interaction area.

In practical applications, the mode that the register divides the data interaction area from the video memory of the BMC chip may be that, through the opening of the register, the opened register declares that the area corresponding to the data interaction area in the video memory is set as unavailable to other objects that can also use the video memory. Therefore, other objects capable of using the video memory do not use the area corresponding to the data interaction area in the video memory, and the division of the data interaction area is realized. The other objects capable of using the video memory can be set according to the actual application scene, such as a video card driver, a video card BIOS, and the like, and do not include objects such as a CPU, a BIOS, a BMC chip, and the like.

Similarly, in the case that the management control module is a graphics card, the BIOS running in the CPU can acquire one or more registers in the graphics card that are responsible for the shared memory function, and acquire the running state of the register; and under the condition that the running state of the register is determined to be closed, selecting to open a specific register from a plurality of registers according to the attribute information of the data interaction area. The specific register is determined based on attribute information such as the size of the data interaction area and/or the position of the data interaction area in the video memory.

In addition, in another scheme, the attribute information of the data sharing area may also be an identifier of a register. When the area design objects are different BMC chips or display cards and different types of data sharing areas are designed, corresponding registers can be directly determined for the different types of data sharing areas, namely, corresponding register identifications are distributed for the same type of data sharing areas, and after the models of the BMC chips or the display cards are determined, a subsequent CPU can determine the corresponding registers from the BMC chips or the display cards and start the registers, so that the division of the data sharing areas is realized.

In the embodiment of the specification, the operating state of the space management submodule is determined; and under the condition that the operation state is closed, adjusting the operation state of the space management submodule to be opened based on the attribute information of the data sharing region, and dividing the data sharing region from the video memory space based on the space management submodule of which the operation state is opened. Therefore, the follow-up realization of pre-writing the information to be transmitted into the data sharing area in advance in an asynchronous transmission mode is facilitated, the required information can be further rapidly acquired from the data sharing area, the problem that the communication consumes a long time is avoided, and the negative influence of the communication consuming a long time on the starting speed is further reduced.

In an embodiment provided in this specification, in order to facilitate a subsequent CPU to achieve a data exchange target with the management control module based on the data sharing area, before dividing the data sharing area from the video memory space of the management control module, the CPU establishes an object relationship between its own memory address code and the video memory space. That is, the CPU integrates a part of the address segment of the memory decoding address space into the memory of the BMC chip, and the CPU reads and writes the address segment subsequently, that is, actually reads and writes the memory space located in the BMC chip. The specific implementation is as follows.

Before the data sharing region is partitioned from the video memory space of the management control module based on the attribute information of the data sharing region, the method further includes:

determining a corresponding video memory address code for the video memory space of the management control module from the memory address codes;

and establishing a corresponding relation between the video memory address code and the video memory space of the management control module.

The storage address code can be understood as a memory decoding address space of the CPU, for example, a memory address space of the CPU; correspondingly, the video memory address code can be understood as an address segment allocated by the CPU for the video memory space. In practical applications, the CPU may allocate address segments of the memory address space to different devices, for example, the CPU may allocate address segments of 1GB to 3GB to a memory (memory bank). And allocating the address field of 4GB-5GB to the video memory space, actually accessing the memory when the CPU accesses the address field of 1GB-3GB, and actually accessing the video memory when the CPU accesses the address field of 4GB-5 GB. Where the memory of the CPU may be referred to as memory banks (DIMMs) which are only part of the CPU memory decode address space.

Specifically, the CPU determines a corresponding video memory address code for the video memory space of the management control module from the storage address codes, and establishes a correspondence between the video memory address code and the video memory space of the management control module.

In the above example, the BIOS running in the CPU decodes the address field of the memory of the CPU to determine the corresponding address field for the video memory of the BMC chip, where the address field may be an address field of 4GB to 5 GB; and then allocating the 4GB-5GB address segment to a video memory of the BMC chip, and establishing a mapping relation between the CPU and the BMC chip. Referring to fig. 2, fig. 2 is a schematic diagram of a memory map applied to a data processing method of a server according to an embodiment of the present disclosure; wherein, the left dashed line frame in fig. 2 represents the decoding address space of the CPU, and the right dashed line frame in fig. 2 represents the memory space of the BMC chip; in this embodiment, the BIOS running in the CPU may determine a corresponding address segment for the video memory in the BMC chip based on the decoded address space of the CPU, and decode the address segment into the video memory integrated into the BMC chip, thereby completing memory mapping between the CPU and the video memory in the BMC chip.

See the right dashed box of fig. 2, where 4GB is the memory size of the BMC chip; the memory of the BMC chip is a Synchronous Dynamic Random Access Memory (SDRAM), and in the starting process of the BMC chip, an area is divided from the SDRAM to be used as a video memory for a video card integrated in the BMC chip; and part of the space in the video memory can be divided into information interaction areas.

Referring to the dashed box on the left side of fig. 2, 4GB/16EB refers to the size of the memory decoding address space, and the BIOS running in the CPU may determine corresponding address segments for a plurality of storage devices based on the memory decoding address space of the CPU, and decode the address segments to be integrated on the corresponding storage devices, for example, the storage devices may include storage devices such as PCI memory, expansion memory, mask rom, expansion rom, regular video memory, regular memory, and dynamic random access memory boundary. Thereby facilitating access to the plurality of memory devices by a subsequent CPU based on the address field.

In the embodiment of the specification, a corresponding video memory address code is determined for the video memory space of the management control module from the storage address codes; and establishing the corresponding relation between the video memory address code and the video memory space of the management control module. And the subsequent CPU reads and writes the data in the information interaction area based on the corresponding relation.

Step 108: and exchanging data with the management control module according to the data sharing area.

Specifically, after obtaining the data sharing area, the CPU and the management control module can perform data exchange based on the data sharing area.

In the above example, after the BIOS running in the CPU completes the division of the information interaction area, the CPU can perform data exchange with the BMC chip or the graphics card in an asynchronous manner in the information interaction area.

The data processing method applied to the server provided by the specification is characterized in that a data sharing area is divided in a video memory space of a management control module, asynchronous data exchange is carried out with the management control module based on the data sharing area, so that the problems of low communication efficiency, poor stability and the like caused by a synchronous transmission mode are solved, and when a large amount of information is required to be transmitted between the data sharing area and the management control module, the information required to be transmitted can be written into the data sharing area in advance in an asynchronous transmission mode, so that the required information can be acquired quickly from the data sharing area subsequently, the problem of long communication time is solved, and the negative influence of long communication time consumption on the starting speed is further reduced.

In an embodiment provided in this specification, in a process of exchanging data with the management control module by the CPU according to the data sharing area, the CPU and the management control module exchange data in an asynchronous manner, the CPU or the management control module writes data into the data sharing area according to a predetermined rule, and a subsequent CPU or the management control module also identifies and reads required data from the data sharing area according to the predetermined rule, where a specific implementation manner of writing data according to the predetermined rule is as follows.

The exchanging data with the management control module according to the data sharing area includes:

determining a preset data exchange rule based on the attribute information of the management control module;

and writing the data to be shared into the data sharing area based on a preset data exchange rule.

In practical application, the data written into the data sharing area by the CPU and the specific position where the data is written into the data sharing area can be predetermined.

The data interaction rule can be understood as a preset rule for data interaction between the CPU and the management control module. The data interaction rule may stipulate that the CPU needs to write the data in the data sharing area, and that the data needs to be written to a specific location in the data sharing area. The subsequent CPU can write the appointment data into the appointment location in the data sharing area based on the data interaction rule. And the management control module can also identify and acquire required data from the data sharing area based on the data interaction rule.

Specifically, the CPU determines a preset data exchange rule between the CPU and the management control module according to the attribute information of the management control module, and writes the data to be shared into the data sharing area based on the preset data exchange rule. The subsequent management control module can identify and acquire the data to be shared from the data sharing area based on the same preset data exchange rule.

Following the above example, the preset data exchange rule can be seen in table 1.

TABLE 1

As shown in table 1, the preset data exchange rule specifies the data that the CPU needs to write into the data interaction area and the location of the data written into the data interaction area, where the name can be understood as the name of the data that the CPU needs to write into the data interaction area, the length is the length of the data that the CPU needs to write into the data interaction area, and the description is the description information of the data that needs to be written into the data interaction area. The offset value can be understood as an offset relative to the base address (pointer), and the base address + the offset value can determine the storage location of the data corresponding to the offset value in the data interaction area. For example, the base address is 0x1000, the offset value of the checksum is 04h, 100 (binary code of the offset value 04 h) +0x1000 is 0x1100, the 0x1100 is the storage address of the checksum in the data exchange area, and the CPU writes the checksum into the address 0x 1100.

In practical applications, when the BMC chip needs to obtain the checksum after the CPU writes the checksum into the address 0x1100, the checksum can be read from the address 0x1100 based on the same predetermined data exchange rule.

In the embodiment of the present specification, a preset data exchange rule is determined based on attribute information passing through a management control module, and data to be shared is written into a data sharing area in an asynchronous manner. Therefore, the problems of low communication efficiency, poor stability and the like caused by the adoption of a synchronous transmission mode are avoided.

The specific implementation manner of writing data by the CPU according to the preset rule is as follows.

and reading the shared data written by the management control module from the data sharing area based on a preset data exchange rule.

The shared data is data written by the management control module based on the preset data exchange rule, for example, a checksum in table 1.

Along with the above example, when the CPU needs to obtain the sum check code, it is necessary to determine a preset data exchange rule between the CPU and the BMC chip or the graphics card, that is, the preset data exchange rule shown in table 1, according to the model of the BMC chip or the graphics card, and based on the preset data exchange rule, the CPU can read the sum check code from the address 0x1100 of the information interaction area. The sum check code is data written into the data exchange area by the BMC chip based on the same preset data exchange rule.

In the embodiments provided in this specification, the shared data written by the management control module is read from the data sharing area based on the preset data exchange rule determined by the attribute information of the management control module. Therefore, the problems of low communication efficiency, poor stability and the like caused by the adoption of a synchronous transmission mode are avoided.

The following describes the data processing method applied to the server by taking the application of the data processing method applied to the server provided in this specification in data processing as an example, with reference to fig. 3. Fig. 3 shows a processing flow chart of a data processing method applied to a server according to an embodiment of the present specification, and specifically includes the following steps.

Step 302: and in the boot process of the BMC chip, a display memory space is divided from a memory space.

In the data processing method applied to the server provided by the present specification, the display card of the server may be integrated in the BMC chip, and based on this, in the power-on process of the BMC chip, an area is allocated to the display card from its own memory space as a display memory space.

Step 304: and the BIOS running in the CPU determines the address field of the display card in the memory decoding address space and decodes the address field of the display card into the display memory integrated in the BMC chip.

The BIOS running in the CPU can determine a corresponding address segment for the video memory of the BMC chip in the memory decoding address space of the CPU, wherein the address segment can be an address segment of 4GB-5GB, and then the address segment of 4GB-5GB is allocated to the video memory of the BMC chip, so that the memory mapping (memory map) relationship between the CPU and the BMC chip is established.

In practical application, after the BIOS running in the CPU allocates the 4GB-5GB address field to the video memory space, when the CPU accesses the 4GB-5GB address field, it actually accesses the video memory.

Step 306: the BIOS running in the CPU divides an information interaction area from the video memory space of the BMC chip.

The BMC chip is provided with a register which is responsible for sharing the memory function, and based on the register, the BIOS running in the CPU can acquire the running state of the register in the BMC chip; and under the condition that the running state of the register is determined to be closed, the register in the BMC chip is opened according to the preset size (32MB) of the data interaction area. Therefore, a space with the size of 32MB is divided from the video memory space in the BMC chip based on the started register to be used as a data interaction area (share memory).

In practical application, the operation of the BIOS dividing the information interaction area from the video memory space of the BMC chip is performed when the BIOS initializes from the video card in the BMC chip. In addition, the data processing method applied to the server provided by the specification advances the initialization process of the graphics card, and improves the time coverage.

The time coverage can be understood as the time when the data interaction area can be used, for example, the BIOS start is a linear process, if the start time is 60S, and the time point when the data interaction area is successfully divided is 20S, then in the time period of 0 to 20S, the CPU cannot use the data interaction area, so that the step of initializing the graphics card is advanced in the linear process of the whole BIOS start, so that the data interaction area that the CPU can use as soon as possible exchanges data with the BMC chip.

In addition, after a partial space in the graphics memory is divided into data interaction areas, when the VBIOS (graphics card BIOS) and the graphics card driver of the graphics card are used for the graphics memory, it is necessary to observe the on/off state of a register in the BMC chip that is responsible for the shared memory function. Under the condition that the register is opened, the VBIOS and the display card driver of the display card can know that the video memory is divided into the data interaction area, so that the VBIOS and the display card driver of the display card cannot use the area which is divided into the data interaction area in the video memory.

Step 308: and the CPU reads and writes the information in the information interaction area according to the convention format.

The agreed format may be understood as the preset data exchange rule in the above embodiments.

Specifically, after the information interaction area is divided from the video memory, the CPU can read and write information in the information interaction area according to an agreed format. The CPU can acquire newly written information in the information interaction area in a polling mode.

Step 310: and the BMC chip reads and writes information in the information interaction area according to the agreed format.

Specifically, after the memory is divided from the video memory, the BMC chip can also read and write information in the information interaction area according to the agreed format. The BMC chip can also acquire newly written information in the information interaction area in a polling mode.

In a specific implementation process, the data processing method applied to the server provided by this specification adopts a way that the BMC shares a video memory channel, avoids technical defects caused by using the anticipated P2A in the above way of data exchange between the BMC and the BIOS, and implements high-speed information communication between the CPU and the BMC chip, where the range of the information interaction area (shared memory) is fixed and has no particular potential safety hazard. In addition, the data processing method applied to the server provided by the specification is not limited to the use in the BIOS stage; after the work execution of the BIOS is finished, the CPU can also perform data interaction with the BMC chip based on the information interaction area, so that in the mode of data exchange between the BMC and the BIOS, the CPU can perform data interaction with the BMC chip in the information interaction area only in the work execution process of the BIOS, the high-speed information communication between the CPU and the BMC chip is further improved, and the high-speed and asynchronous information exchange between the BMC chip and the CPU is realized.

Corresponding to the above method embodiment, the present specification further provides an embodiment of a data processing apparatus applied to a server, and fig. 4 shows a schematic structural diagram of a data processing apparatus applied to a server according to an embodiment of the present specification. As shown in fig. 4, the apparatus includes:

a first determination module 402 configured to determine attribute information of a management control module in the server;

a second determining module 404 configured to determine attribute information of the data sharing area according to the attribute information of the management control module;

a dividing module 406 configured to divide the data sharing area from the video memory space of the management control module based on the attribute information of the data sharing area;

a data exchange module 408 configured to exchange data with the management control module according to the data sharing area.

Optionally, the data processing apparatus applied to the server further includes a relationship building module configured to:

Optionally, the dividing module 406 is further configured to:

determining the operating state of the space management submodule;

Optionally, the data exchange module 408 is further configured to:

and reading shared data written by the management control module from the data sharing area based on a preset data exchange rule, wherein the shared data is the data written by the management control module based on the preset data exchange rule.

The data processing device applied to the server provided by the specification is used for marking out the data sharing area in the video memory space of the management control module and exchanging asynchronous data with the management control module based on the data sharing area, so that the problems that when a synchronous transmission mode is adopted, the communication efficiency is low, the stability is poor and the like are solved, when a large amount of information is required to be transmitted between the data sharing area and the management control module, the information required to be transmitted can be written into the data sharing area in advance in the asynchronous transmission mode, the required information can be acquired quickly from the data sharing area in the follow-up process, the problem that the communication time consumption is long is solved, and the negative influence of long communication time consumption on the starting speed is further reduced.

The foregoing is an illustrative scheme of a data processing apparatus applied to a server according to the present embodiment. It should be noted that the technical solution of the data processing apparatus applied to the server and the technical solution of the data processing method applied to the server belong to the same concept, and details that are not described in detail in the technical solution of the data processing apparatus applied to the server can be referred to the description of the technical solution of the data processing method applied to the server.

Fig. 5 is a flowchart illustrating another data processing method applied to a server according to an embodiment of the present disclosure, which includes the following steps.

Step 502: and acquiring the current state information of the video memory space.

In practical application, another data processing method applied to a server provided by the specification can be applied to a management control module of a data processing system; for the description of the management control module, reference may be made to the description of the management control module in the data processing method applied to the server, which is not described in detail herein in this embodiment.

The current state information of the video memory space may be understood as information indicating a current operating state of the video memory space, for example, the current state information may be understood as a size in the video memory space. In practical applications, the current state information of the video memory space may also be understood as the opening or closing information of the register in the BMC chip that is responsible for sharing the memory function.

Specifically, the management control module can acquire the current state information of the video memory space in real time.

Step 504: and under the condition that the existence of the data sharing area is determined based on the current state information, exchanging data with an operation control module in the server according to the data sharing area.

The data sharing area is an area which is divided from the video memory space by the operation control module based on the attribute information of the data sharing area. The description of the area divided from the video memory space by the data sharing area, the operation control module, and the operation control module based on the attribute information of the data sharing area may refer to the corresponding description content in the data processing method applied to the server, which is not described herein in detail.

Specifically, when the management control module determines that the data sharing area exists based on the current state information, the management control module may perform data exchange with the operation control module in an asynchronous manner according to the data sharing area. When the current state information is the size of the video memory space, the management control module determines that an area of the video memory space is divided as a data sharing area when determining that the size (for example, 96MB) of the video memory space is smaller than a preset size (128MB) of the video memory space.

In an embodiment provided in this specification, the performing, according to the data sharing area, data exchange with the operation control module includes:

writing data to be shared into the data sharing area based on a preset data exchange rule; and/or

Based on a preset data exchange rule, reading shared data written in by an operation control module from the data sharing area, wherein the shared data is the data written in by the operation control module based on the preset data exchange rule.

The preset data exchange rule may refer to the description of the data processing method applied to the server, which is not described herein in any greater detail.

Taking another data processing method applied to the server as an example in a scenario of data exchange with the CPU, writing data to be shared into the data sharing area based on a preset data exchange rule is further described below. The management control module is a BMC chip, and the operation management module is a CPU.

The preset data exchange rule stipulates the data which needs to be written into the data interaction area by the BMC chip and the position of the data written into the data interaction area. Based on this, under the condition that the BMC chip determines to store the data exchange area, the data that needs to be written into the data exchange area is determined based on the data name in the preset data exchange rule, and the position where the data needs to be written into the data exchange area is determined based on the offset number provided by the preset data exchange rule for each data written into the data exchange area. Referring to table 1, for example, the base address is 0x1000, the offset value of the checksum is 04h, 100 (binary code of the offset value 04 h) +0x1000 is 0x1100, where 0x1100 is the storage address of the checksum in the data interaction area, and the BMC chip writes the checksum into the address 0x 1100. When the CPU chip needs to acquire the checksum after the BMC chip writes the checksum into the address 0x1100, the checksum can be read from the address 0x1100 based on the same preset data exchange rule.

In addition, when the BMC chip needs to obtain the checksum, the BMC chip can read the checksum from the address 0x1100 of the information interaction area based on the preset data exchange rule with the CPU, that is, the preset data exchange rule shown in table 1. The checksum is data that the CPU writes into the data exchange area based on the same predetermined data exchange rule.

Another data processing method applied to the server provided in this specification exchanges data with the arithmetic control module according to the data sharing area when it is determined that the data sharing area exists according to the current state information of the video memory space. Therefore, the problems of low communication efficiency, poor stability and the like caused by a synchronous transmission mode are solved, when a large amount of information is required to be transmitted between the operation control module and the operation control module, the information required to be transmitted can be written into the data sharing area in advance in an asynchronous transmission mode, the required information can be acquired quickly from the data sharing area in the follow-up process, the problem of long communication time consumption is solved, and the negative influence of long communication time consumption on the starting speed is further reduced.

The above is an illustrative scheme of another data processing method applied to the server according to the embodiment. It should be noted that the technical solution of the other data processing method applied to the server belongs to the same concept as the technical solution of the one data processing method applied to the server, and details of the technical solution of the other data processing method applied to the server, which are not described in detail, can be referred to the description of the technical solution of the one data processing method applied to the server.

Corresponding to the above method embodiment, the present specification also provides another data processing apparatus embodiment applied to a server, and fig. 6 shows a schematic structural diagram of another data processing apparatus applied to a server provided in an embodiment of the present specification. As shown in fig. 6, the apparatus includes:

an obtaining module 602 configured to obtain current state information of a video memory space;

a data exchange module 604 configured to exchange data with an operation control module in the server according to the data sharing area in a case where it is determined that the data sharing area exists based on the current state information;

Optionally, the data exchange module 604 is further configured to write data to be shared into the data sharing area based on a preset data exchange rule; and/or

Another data processing apparatus applied to a server provided in this specification exchanges data with an arithmetic control module according to a data sharing area when it is determined that a data sharing area exists based on current state information of a video memory space. Therefore, the problems that the communication efficiency is low and the stability is poor when a synchronous transmission mode is adopted are solved, and when a large amount of information is required to be transmitted between the operation control module and the operation control module, the information required to be transmitted can be written into the data sharing area in advance through an asynchronous transmission mode, the required information can be acquired quickly from the data sharing area in the follow-up process, the problem that the communication consumes a long time is avoided, and the negative influence of the communication consuming a long time on the starting speed is further reduced.

The above is another schematic configuration of the data processing apparatus applied to the server according to the present embodiment. It should be noted that the technical solution of the other data processing apparatus applied to the server and the technical solution of the other data processing method applied to the server belong to the same concept, and details of the other technical solution applied to the data processing apparatus applied to the server, which are not described in detail, can be referred to the description of the technical solution of the other data processing method applied to the server.

Fig. 7 is a schematic diagram illustrating a data processing system applied to a server according to an embodiment of the present disclosure, and as shown in fig. 7, the system includes an arithmetic control module 702 in the server and a management control module 704 in the server, wherein,

the operation control module 702 is configured to determine attribute information of the management control module 704, determine attribute information of a data sharing area according to the attribute information of the management control module 704, partition the data sharing area from the video memory space of the management control module 704 based on the attribute information of the data sharing area, and exchange data with the management control module 704 according to the data sharing area;

the management control module 704 is configured to exchange data with the operation control module 702 according to the data sharing area.

In the above example, the management control module 704 is a BMC chip in the server, and the calculation control module 702 is a CPU in the server. Based on the information, the CPU can acquire the model information of the BMC chip and determine the attribute information of the data interaction area to be divided, which corresponds to the BMC chip, based on the model information of the BMC chip, wherein the attribute information can be that the size of the data interaction area to be divided is 32 MB; then, the CPU can divide a data interaction area with the size of 32MB from a specific position of the display memory space of the BMC chip based on the attribute information.

After the CPU completes the division of the data interaction area, the CPU can exchange data with the BMC chip or the display card in an asynchronous mode in the information interaction area; the BMC core can exchange data with the CPU in an asynchronous mode in the information interaction area.

In the data processing system applied to the server, the operation management model is used for dividing a data sharing area in the video memory space of the management control module 704, and asynchronous data exchange is performed with the management control module 704 based on the data sharing area, so that the problems of low communication efficiency, poor stability and the like caused by a synchronous transmission mode are solved, and when a large amount of information needs to be transmitted between the operation management model and the management control module 704, the information needing to be transmitted can be written into the data sharing area in advance in an asynchronous transmission mode, so that the needed information can be rapidly acquired from the data sharing area subsequently, the problem of long communication time consumption is solved, and the negative influence of long communication time consumption on the starting speed is further reduced.

The above is an illustrative scheme of a data processing system applied to a server according to the present embodiment. It should be noted that, the technical solution of the data processing system applied to the server and the technical solution of the data processing method applied to the server and the other technical solution applied to the server belong to the same concept, and details of the technical solution of the data processing system applied to the server, which are not described in detail, can be referred to the description of the technical solution of the data processing method applied to the server and the other technical solution applied to the data processing method of the server.

FIG. 8 illustrates a block diagram of a computing device 800, according to one embodiment of the present description. The components of the computing device 800 include, but are not limited to, a memory 810 and a processor 820. The processor 820 is coupled to the memory 810 via a bus 830, and the database 850 is used to store data.

Computing device 800 also includes access device 840, access device 840 enabling computing device 800 to communicate via one or more networks 860. Examples of such networks include the Public Switched Telephone Network (PSTN), a Local Area Network (LAN), a Wide Area Network (WAN), a Personal Area Network (PAN), or a combination of communication networks such as the internet. Access device 840 may include one or more of any type of network interface (e.g., a Network Interface Card (NIC)) whether wired or wireless, such as an IEEE802.11 Wireless Local Area Network (WLAN) wireless interface, a worldwide interoperability for microwave access (Wi-MAX) interface, an ethernet interface, a Universal Serial Bus (USB) interface, a cellular network interface, a bluetooth interface, a Near Field Communication (NFC) interface, and so forth.

In one embodiment of the present description, the above-described components of computing device 800, as well as other components not shown in FIG. 8, may also be connected to each other, such as by a bus. It should be understood that the block diagram of the computing device architecture shown in FIG. 8 is for purposes of example only and is not limiting as to the scope of the description. Those skilled in the art may add or replace other components as desired.

Computing device 800 may be any type of stationary or mobile computing device, including a mobile computer or mobile computing device (e.g., tablet, personal digital assistant, laptop, notebook, netbook, etc.), a mobile phone (e.g., smartphone), a wearable computing device (e.g., smartwatch, smartglasses, etc.), or other type of mobile device, or a stationary computing device such as a desktop computer or PC. Computing device 800 may also be a mobile or stationary server.

Wherein the processor 820 is configured to execute computer-executable instructions, which when executed by the processor 820, implement the steps of the data processing method applied to the server.

The above is an illustrative scheme of a computing device of the present embodiment. It should be noted that the technical solution of the computing device and the technical solution of the data processing method applied to the server belong to the same concept, and details that are not described in detail in the technical solution of the computing device can be referred to the description of the technical solution of the data processing method applied to the server.

An embodiment of the present specification also provides a computer-readable storage medium storing computer-executable instructions, which when executed by a processor, implement the steps of the data processing method applied to the server.

The above is an illustrative scheme of a computer-readable storage medium of the present embodiment. It should be noted that the technical solution of the storage medium belongs to the same concept as the technical solution of the data processing method applied to the server, and details that are not described in detail in the technical solution of the storage medium can be referred to the description of the technical solution of the data processing method applied to the server.

An embodiment of the present specification further provides a computer program, wherein when the computer program is executed in a computer, the computer program causes the computer to execute the steps of the data processing method applied to the server.

The above is an illustrative scheme of a computer program of the present embodiment. It should be noted that the technical solution of the computer program is the same as the technical solution of the data processing method applied to the server, and details that are not described in detail in the technical solution of the computer program can be referred to the description of the technical solution of the data processing method applied to the server.

The foregoing description has been directed to specific embodiments of this disclosure. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may also be possible or may be advantageous.

The computer instructions comprise computer program code which may be in the form of source code, object code, an executable file or some intermediate form, or the like. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, usb disk, removable hard disk, magnetic disk, optical disk, computer Memory, Read-Only Memory (ROM), Random Access Memory (RAM), electrical carrier wave signals, telecommunications signals, software distribution medium, and the like. It should be noted that the computer readable medium may contain content that is subject to appropriate increase or decrease as required by legislation and patent practice in jurisdictions, for example, in some jurisdictions, computer readable media does not include electrical carrier signals and telecommunications signals as is required by legislation and patent practice.

It should be noted that, for the sake of simplicity, the foregoing method embodiments are described as a series of acts, but those skilled in the art should understand that the present embodiment is not limited by the described acts, because some steps may be performed in other sequences or simultaneously according to the present embodiment. Further, those skilled in the art should also appreciate that the embodiments described in this specification are preferred embodiments and that acts and modules referred to are not necessarily required for an embodiment of the specification.

In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

The preferred embodiments of the present specification disclosed above are intended only to aid in the description of the specification. Alternative embodiments are not exhaustive and do not limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the embodiments and the practical application, and to thereby enable others skilled in the art to best understand the specification and utilize the specification. The specification is limited only by the claims and their full scope and equivalents.

Claims

1. A data processing method applied to a server comprises the following steps:

determining attribute information of a management control module in the server;

2. The data processing method applied to a server according to claim 1, wherein before the data sharing area is partitioned from a video memory space of the management control module based on the attribute information of the data sharing area, the method further comprises:

3. The data processing method applied to a server according to claim 1, wherein the dividing the data sharing area from the video memory space of the management control module based on the attribute information of the data sharing area comprises:

4. The data processing method applied to the server according to claim 3, wherein the dividing the data sharing area from the video memory space of the management control module based on the attribute information of the data sharing area and the space management sub-module comprises:

determining the operating state of the space management submodule;

under the condition that the running state is closed, the running state of the space management submodule is adjusted to be opened based on the attribute information of the data sharing area;

5. The data processing method applied to the server according to claim 1, wherein the exchanging data with the management control module according to the data sharing area includes:

6. The data processing method applied to the server according to claim 1, wherein the exchanging data with the management control module according to the data sharing area includes:

7. The data processing method applied to the server according to claim 1, wherein the management control module is a BMC chip.

8. A data processing method applied to a server comprises the following steps:

acquiring current state information of a video memory space;

9. The data processing method applied to the server according to claim 8, wherein the exchanging data with the operation control module in the server according to the data sharing area comprises:

10. A data processing system applied to a server, the system comprising an arithmetic control module in the server, a management control module in the server, wherein,

11. A data processing apparatus applied to a server, applied to the server, comprising:

12. A data processing apparatus applied to a server, comprising:

13. A computing device, comprising:

a memory and a processor;

the memory is used for storing computer-executable instructions, and the processor is used for executing the computer-executable instructions, and the computer-executable instructions when executed by the processor realize the steps of the data processing method applied to the server in any one of claims 1 to 6 or claims 7 to 9.

14. A computer-readable storage medium storing computer-executable instructions which, when executed by a processor, implement the steps of the data processing method of any one of claims 1 to 6 or claims 7 to 9 applied to a server.