CN114567317A - Coarse delay phase-locked loop circuit and delay control circuit - Google Patents

Coarse delay phase-locked loop circuit and delay control circuit Download PDF

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Publication number
CN114567317A
CN114567317A CN202210156529.7A CN202210156529A CN114567317A CN 114567317 A CN114567317 A CN 114567317A CN 202210156529 A CN202210156529 A CN 202210156529A CN 114567317 A CN114567317 A CN 114567317A
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delay
phase
signal
control
module
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杨灿美
李文嘉
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Xinsiyuan Microelectronics Co ltd
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Xinsiyuan Microelectronics Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0818—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter comprising coarse and fine delay or phase-shifting means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop

Abstract

The invention provides a coarse delay phase-locked loop circuit and a delay control circuit, wherein the delay control circuit comprises a coarse delay phase-locked loop circuit, and the coarse delay phase-locked loop circuit comprises a phase frequency detector, a first delay module, a delay link module, a charge pump and a control module; the signal input end of the first delay module is connected with a reference frequency, and the first delay module outputs a first delay signal and a second delay signal under the action of control voltage output by the charge pump; the delay link module delays the first delay signal again under the action of the control voltage output by the charge pump to output a delay feedback signal; the control module generates an enable control signal for controlling the phase frequency detector according to the power supply voltage signal and the enable signal; based on the control action of the enabling control signal, the phase frequency detector outputs a phase difference signal according to the second delay signal and the delay feedback signal; and the charge pump obtains the control voltage according to the phase difference signal. The invention can accurately control the delay range.

Description

Coarse delay phase-locked loop circuit and delay control circuit
Technical Field
The invention relates to the technical field of control, in particular to a coarse delay phase-locked loop circuit and a delay control circuit.
Background
Delay Locked LOOPs (DLL), which are commonly used in integrated circuit multiphase clock generation or in order to obtain high-precision Delay control circuits, can better overcome Delay variation caused by inherent process deviation, voltage fluctuation and temperature variation (PVT) of CMOS semiconductors in a closed-LOOP manner, such as high-precision digital control Delay chips, time-to-digital conversion circuits, all-digital phase Locked LOOPs and the like. Because the intrinsic delay of the CMOS circuit is larger, the control of the delay precision exceeding the intrinsic delay amount is achieved by adopting a thick-thin two-stage delay circuit in a general practical chip; the coarse and fine two-stage delay circuits are respectively a coarse delay phase-locked loop circuit and a fine delay circuit; the adjusting precision of the coarse delay phase-locked loop circuit is smaller than that of the fine delay circuit, namely, the delay interval of the coarse delay is large, and the delay interval of the fine delay is small. The delay control circuit consists of a coarse delay phase-locking unit (coarse DLL), a fine delay phase-locking unit (fine DLL), a coarse delay link unit and a fine delay link unit, and control voltages output by the coarse delay phase-locking unit and the fine delay phase-locking unit respectively control the corresponding delay links. The coarse delay phase-locked loop circuit mainly provides a bias voltage for the coarse delay link unit to ensure the normal and stable work of the coarse delay link unit, and the fine delay phase-locked loop unit changes the size of the load to change the time of the fine delay, thereby obtaining higher resolution.
However, the delay circuit of the current coarse delay phase-locked loop circuit is complex in design, and when the input pulse width is very narrow, pulse loss, electric leakage, logic output errors and the like may be caused, so that the control of the coarse delay phase-locked loop circuit is inaccurate, and further, the accuracy degree of the high-precision delay control circuit is poor.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, it is an object of the present invention to provide a coarse delay phase-locked loop circuit and a delay control circuit, which are used to solve the problem of inaccurate control in the prior art.
In order to achieve the above and other related objects, the present invention provides a coarse delay phase-locked loop circuit, which includes a phase frequency detector, a first delay module, a delay link module, a charge pump, and a control module;
the signal input end of the first delay module is connected with a reference frequency, and the control end of the first delay module is connected with the output end of the charge pump; the first delay module outputs a first delay signal from a first output end of the first delay module and outputs a second delay signal from a second output end of the first delay module under the action of the control voltage output by the charge pump;
the signal input end of the delay link module is connected with the first output end of the first delay module, and the control end of the delay link module is connected with the output end of the charge pump; the delay link module delays the first delay signal again under the action of the control voltage output by the charge pump to output a delay feedback signal;
the input end of the control module is connected with a power supply voltage signal and an enabling signal, and the output end of the control module is connected with the enabling end of the phase frequency detector; the control module generates an enable control signal for controlling the phase frequency detector according to the power supply voltage signal and the enable signal;
a first input end of the phase frequency detector is connected with a first output end of the first delay module, and a second input end of the phase frequency detector is connected with an output end of the delay link module; based on the control action of the enabling control signal, the phase frequency detector outputs a phase difference signal according to the second delay signal and the delay feedback signal;
the input end of the charge pump is connected with the output end of the phase frequency detector; and the charge pump obtains the control voltage according to the phase difference signal.
Preferably, the control module comprises a first switch, a second switch, a first and gate, a first inverter, a second inverter and a nor gate;
the input end of the first switch is connected with the output end of the first phase inverter, the output end of the first switch is connected with the input end of the first phase inverter and the first input end of the first AND gate, the first source end of the first switch is connected with a power supply voltage, and the second source end of the first switch is connected with the output end of the charge pump;
the input end of the second switch is connected with the output end of the second phase inverter, the output end of the second switch is connected with the input end of the second phase inverter, the first source end of the second switch is connected with the chip pin voltage, and the second source end of the second switch is connected with the output end of the charge pump;
a first input end of the NOR gate is connected with an output end of the first phase inverter, a second input end of the NOR gate is connected with a second input end of the first AND gate, and an output end of the NOR gate is connected with an input end of the second phase inverter; the output end of the first AND gate is connected with the enabling end of the phase frequency detector.
Preferably, the first delay module includes two delay units, an input end of each delay unit is connected to the reference frequency through a buffer, and a control end of each delay unit is connected to an output end of the charge pump; the output end of each delay unit is also connected with a buffer.
Preferably, the delay link module includes N delay units, the N delay units are cascaded, and a control end of each delay unit is connected to an output end of the charge pump; wherein N is more than or equal to 3.
Preferably, the delay unit includes two identical delay subunits, and the delay subunits are cascaded; the delay subunit comprises a half-side current starvation type inverter and a buffer circuit;
the half-side current starvation type phase inverter comprises a first PMOS tube, a first NMOS tube, a second NMOS tube and a third NMOS tube; the grid electrode of the first PMOS tube and the grid electrode of the first NMOS tube are input ends of the delay unit, the source electrode of the first PMOS tube is connected with a power supply voltage, and the drain electrode of the first PMOS tube is connected with the drain electrode of the third NMOS tube; the grid electrode of the third NMOS tube is the control end of the delay unit, and the drain electrode of the third NMOS tube is connected with the source electrode of the first NMOS tube and the drain electrode of the second NMOS tube; the grid electrode of the second NMOS tube is connected with a power supply voltage, and the drain electrode of the second NMOS tube and the drain electrode of the third NMOS tube are grounded; the half-side current starvation type inverter is used for outputting a discharge current according to a control voltage;
the buffer circuit comprises a Schmitt inverter and a third inverter; the input end of the Schmidt inverter is connected with a connection point formed by connecting the drain electrode of the first PMOS tube and the drain electrode of the third NMOS tube; the output end of the Schmitt phase inverter is connected with the input end of the third phase inverter; and the buffer circuit is used for buffering the discharge current and then outputting the discharge current.
Preferably, the mobile terminal further comprises a second delay module, a first input end of the second delay module is connected to a second output end of the first delay module, and is configured to receive the first delay signal; a second input end of the second delay module is connected with an output end of the delay link module and is used for receiving the delay feedback signal; the control end of the second delay module is connected with the output end of the charge pump; and the second delay module delays the second delay signal again and delays the delay feedback signal again under the action of the control voltage output by the charge pump.
Preferably, the phase frequency detector PFD includes a first flip-flop, a second flip-flop, a third flip-flop, a fourth flip-flop, and an enable control unit;
the clock end of the first trigger is a first input end of the phase frequency detector; the input end of the first trigger is connected with a power supply voltage, and the output end of the first trigger is connected with the input end of the second trigger; the clock end of the second trigger is connected with the clock end of the first trigger; the clock end of the third trigger is a second input end of the phase frequency detector; the input end of the third trigger is connected with a power supply voltage, and the output end of the third trigger is connected with the input end of the fourth trigger; the clock end of the fourth trigger is connected with the clock end of the third trigger; the reset end of the third trigger is grounded;
the output of the enabling control unit is connected with the reset end of the first trigger, the reset end of the second trigger and the reset end of the fourth trigger; the input end of the enabling control unit is connected with the output end of the control module;
and the phase frequency detector outputs a phase difference signal through the output end of the second trigger and the output end of the fourth trigger according to the enabling control signal.
Preferably, the first flip-flop and the third flip-flop are of the same structure, the second flip-flop and the fourth flip-flop are of the same structure, the first flip-flop and the second flip-flop form a first trigger branch for processing the third delay signal, and the third flip-flop and the fourth flip-flop form a second trigger branch for processing the fourth delay signal.
Preferably, the enable control unit includes a fourth inverter, a second and gate and an or gate;
the input end of the fourth phase inverter is connected with the output end of the control module, the output end of the fourth phase inverter is connected with the reset end of the first phase inverter and the first input end of the OR gate, the first input end of the second AND gate is connected with the output end of the second phase inverter, the second input end of the second AND gate is connected with the output end of the fourth phase inverter, the output end of the second AND gate is connected with the second input end of the OR gate, and the output end of the OR gate is connected with the reset end of the second phase inverter and the reset end of the fourth phase inverter.
To achieve the above and other related objects, the present invention provides a delay control circuit, which includes a coarse delay circuit and a fine delay circuit; the coarse delay circuit is the coarse delay phase-locked loop circuit; the adjacent clock signals output by the coarse delay circuit are connected with the input end of the fine delay circuit; the coarse delay circuit is used for controlling the delay range of the delay control circuit, and the fine delay circuit controls the output delay size based on the delay range.
As described above, the coarse delay phase-locked loop circuit and the delay control circuit of the present invention have the following advantages:
the coarse delay phase-locked loop circuit respectively inputs the reference frequency to the delay link module and the phase frequency detector under the same environment through the first delay module, and can ensure that the paths of a third delay signal and a delay feedback signal are completely consistent under the action of the second delay module; the coarse delay phase-locked loop circuit can accurately control the range of the first control voltage; the accuracy of delay range control is improved.
Drawings
Fig. 1 is a schematic diagram illustrating the structural principle of the delay control circuit according to the present invention.
FIG. 2 is a schematic circuit diagram of a coarse delay PLL circuit according to the present invention.
Fig. 3 is a schematic circuit diagram of the delay unit according to the present invention.
FIG. 4 is a timing diagram illustrating the operation of the delay unit according to the embodiment of the present invention.
Fig. 5 shows a schematic structural diagram of the phase frequency detector of the present invention.
Fig. 6 is a schematic circuit diagram of the first flip-flop and the third flip-flop of the present invention.
Fig. 7 is a schematic circuit diagram of a second flip-flop and a fourth flip-flop of the present invention.
Fig. 8 is a schematic circuit diagram of the charge pump of the present invention.
Description of the element reference numerals
1 first time delay module
2 second delay module
3 phase frequency detector
4-time-delay link module
5 control module
6 inverter chain
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1-7. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
As shown in fig. 2, which is a schematic diagram of a structural principle of the coarse delay control circuit of the present invention, a coarse delay phase-locked loop circuit includes a phase frequency detector 3, a first delay module 1, a delay link module 4, a charge pump and a control module 5;
the signal input end of the first delay module 1 is connected with a reference frequency, and the control end of the first delay module 1 is connected with the output end of the charge pump; under the action of the control voltage output by the charge pump, the first delay module 1 outputs a first delay signal from a first output end of the first delay module 1, and outputs a second delay signal from a second output end of the first delay module 1;
the signal input end of the delay link module 4 is connected with the first output end of the first delay module 1, and the control end of the delay link module 4 is connected with the output end of the charge pump; the delay link module 4 delays the first delay signal again under the action of the control voltage output by the charge pump to output a delay feedback signal;
the input end of the control module 5 is connected with a power supply voltage signal and an enabling signal, and the output end of the control module 5 is connected with the enabling end of the phase frequency detector 3; the control module 5 generates an enable control signal for controlling the phase frequency detector 3 according to the power supply voltage signal and the enable signal;
a first input end of the phase frequency detector 3 is connected with a first output end of the first delay module 1, and a second input end of the phase frequency detector 3 is connected with an output end of the delay link module 4; based on the control action of the enable control signal, the phase frequency detector 3 outputs a phase difference signal according to the second delay signal and the delay feedback signal;
the input end of the charge pump is connected with the output end of the phase frequency detector 3; and obtaining the control voltage according to the phase difference signal.
The coarse delay phase-locked loop circuit inputs reference frequency to the delay link module 4 and the phase frequency detector 3 respectively under the same environment through the first delay module 1, and the range of the first control voltage can be accurately controlled through the coarse delay phase-locked loop circuit; the accuracy of delay range control is improved.
In the present invention, the control module 5 includes a first switch M1, a second switch M2, a first and gate Y1, a first inverter N1, a second inverter N2, and an nor gate H1;
the input end of the first switch is connected with the output end of the first phase inverter, the output end of the first switch is connected with the input end of the first phase inverter and the first input end of the first AND gate, the first source end of the first switch is connected with a power supply voltage, and the second source end of the first switch is connected with the output end of the charge pump;
the input end of the second switch is connected with the output end of the second phase inverter, the output end of the second switch is connected with the input end of the second phase inverter, the first source end of the second switch is connected with the chip pin voltage, and the second source end of the second switch is connected with the output end of the charge pump;
a first input end of the NOR gate is connected with an output end of the first phase inverter, a second input end of the NOR gate is connected with a second input end of the first AND gate, and an output end of the NOR gate is connected with an input end of the second phase inverter; the output end of the first AND gate is connected with the enabling end of the phase frequency detector 3.
The control module 5 of the present invention is connected to the power supply voltage through the first switch, obtains the detection signal PWR _ DET _1P2 of the power supply voltage through the first input terminal of the first and gate, and obtains the enable signal through the second input terminal of the first and gate, i.e. internally generates the enable control signal to control the phase frequency detector 3 after the detection signal PWR _ DET _1P2 of the power supply voltage and the enable signal EN _ CDLL are combined. Specifically, during the power-on period of the power supply voltage, the control voltage VCTL is connected to VDD through the transmission gate (M1) to minimize the delay, after the power supply is stabilized, the detection signal PWR _ DET _1P2 jumps, the first switch M1 is turned off, and the voltage of the control voltage VCTL is determined by the coarse delay phase-locked loop. If the coarse delay phase-locked loop cannot work normally, the enable signal EN _ CDLL is configured to be low level through numbers, the coarse delay phase-locked loop DLL is closed, the second switch M2 is conducted, and the external chip pin voltage START _ VC can be directly supplied to the control voltage VCTL.
In the invention, a first delay module 1 comprises two delay units, wherein the input end of each delay unit is connected with a reference frequency through a buffer, the input end of the buffer is connected with a reference frequency Fref, and the output end of the buffer is connected with the input end of the delay unit; the control end of each delay unit is connected with the output end of the charge pump; the output end of each delay unit is connected with the buffer, and each delay unit delays the reference frequency under the action of the control voltage output by the charge pump and then outputs a first delay signal and a second delay signal; the output end of the buffer is suspended, and the buffer arranged at the output end can reduce the influence of the load on the delay unit.
The input end of each delay unit in the first delay module 1 is provided with a buffer to ensure the consistency of input environments, the buffer matched with the output end of the delay unit is actually arranged in the delay unit, and the consistency of the environments output to the delay link module 4 and the phase frequency detector 3 can be ensured under the buffer action of the buffer, so that the uniformity of delay is ensured.
In the invention, a delay link module 4 is formed by cascading N voltage-controllable delay units, wherein the control end of each delay unit is connected with the output end of the charge pump; wherein N is more than or equal to 3, and in the embodiment of the invention, N is 16; each stage of delay unit realizes 312.5ps delay, and the total delay is 5 ns. The high 4 bits of the delay control word are digitally decoded and then control the multiplexer to select corresponding delay output to generate corresponding delay time. Under the action of the control voltage output by the charge pump, the environment consistency and the time delay uniformity of each stage of time delay unit can be ensured.
Because the number of the stages of the delay units connected in series on the delay chain is large, if the delay of each stage of delay unit to the rising edge and the falling edge of the input signal is inconsistent, the duty ratio of the output signal is greatly changed. When the input signal frequency is high (up to 1.5GHz) and the pulse width is narrow (333ps), the output signal may disappear after multi-stage delay, and become constant high or constant low. In order to avoid this, when designing the delay unit, it is necessary to ensure that the delays of the rising edge and the falling edge of the input signal are consistent, and keep the duty ratio of the output signal unchanged.
Therefore, the delay unit comprises two identical delay subunits, the two delay subunits are cascaded, and each delay subunit comprises a half-edge current starvation type inverter and a buffer circuit;
the half-side current starvation type inverter includes first PMOS tubes (P1_ a and P1_ b), first NMOS tubes (N1_ a and N1_ b), second NMOS tubes (N2_ a and N2_ b), and third NMOS tubes (Nc _ a and Nc _ b); the grid electrode of the first PMOS tube and the grid electrode of the first NMOS tube are input ends of the delay unit, the source electrode of the first PMOS tube is connected with a power supply voltage, and the drain electrode of the first PMOS tube is connected with the drain electrode of the third NMOS tube; the grid electrode of the third NMOS tube is the control end of the delay unit, and the drain electrode of the third NMOS tube is connected with the source electrode of the first NMOS tube and the drain electrode of the second NMOS tube; the grid electrode of the second NMOS tube is connected with a power supply voltage, and the drain electrode of the second NMOS tube and the drain electrode of the third NMOS tube are grounded; the half-side current starvation type inverter is used for outputting a discharge current according to a control voltage;
the buffer circuit comprises Schmitt inverters (SMT _ a and SMT _ b) and third inverters (INV _ a and INV _ b); the input end of the Schmidt inverter is connected with a connection point formed by connecting the drain electrode of the first PMOS tube and the drain electrode of the third NMOS tube; the output end of the Schmitt phase inverter is connected with the input end of the third phase inverter; and the buffer circuit is used for buffering the discharge current and then outputting the discharge current.
In the embodiment of the present invention, a schematic circuit structure diagram of the delay unit is shown in fig. 3, specifically, two delay sub-units are half delaycell a pair of rising edge sub-unitsEdge delay and half delaycell B delay the falling edge. Taking half-edge current starvation inverter a as an example, the half-edge current starvation inverter is composed of four transistors, i.e. a first PMOS transistor P1_ a, a first NMOS transistor N1_ a, a third NMOS transistor Nc _ a and a second NMOS transistor N2_ a, wherein the gates of the first PMOS transistor P1_ a and the first NMOS transistor N1_ a are connected with the input signal IN, and the source of the first NMOS transistor N1_ a is connected to the ground through the third NMOS transistor Nc _ a and the second NMOS transistor N2_ a; the gate of the third NMOS transistor Nc _ a is the control terminal of the delay unit, whichIs connected withConnected with a control voltage VCTL, the control voltage VCTL signal is delayed roughlyTime of flightThe phase-locked loop DLL loop is generated to control the magnitude of the discharge current of the half-side current starved inverter to the output node nd1_ a thereof.
When the input signal IN goes from high to low, the node nd1_ a goes from high to low, the falling time is controlled by the control voltage VCTL, and the voltage of the control voltage VCTL is changed, so that different delays can be realized. Since the control voltage VCTL signal is generated by DLL, its voltage variation range is large in order to ensure the total delay of the delay unit is not changed under different process, voltage, temperature (PVT) conditions.
When the voltage of the control voltage VCTL is lower than the threshold of the third NMOS transistor Nc _ a, the discharge current is small, and the low-level voltage of the node nd1_ a is high, which may cause the next stage circuit to fail to flip normally. To avoid this, a second NMOS transistor N2_ a is added, which is much smaller in size than the third NMOS transistor Nc _ a. The gate of the second NMOS transistor N2_ a is connected to VDD, and the second NMOS transistor N2_ a is always turned on, which can provide the basic discharge current of the half-edge current starved inverter, so that when the control voltage VCTL is lower than the threshold voltage of the third NMOS transistor Nc _ a, the delay unit still has a signal output. Then, through the buffering output action of the schmitt inverter SMT _ a and the third inverter INV _ a, the intermediate signal OUT _ a is output, and the intermediate signal OUT _ a is connected to a buffer BUF _ a in addition to being used as an input signal of the half delaycell B. The circuit structure of the delay subunit half delaycell B is completely consistent with that of the delay subunit half delaycell a, the two constitute a complete coarse delay unit, and the output end OUT of the coarse delay unit is directly connected with the input end of the next-stage delay unit.
In order to prevent the later-stage circuit from influencing the delay of the delay unit and ensure that the load environment of each stage of delay unit in the delay link is completely consistent, thereby realizing the uniformity of delay, the signal of the output end OUT passes through the buffer BUF _ b and then is output to the later-stage multiplexer circuit from the (rising edge or falling edge) end O _ BUF.
Only the input rising edge causes nd1_ a to discharge, which is converted back to a steep falling edge by the second stage schmitt trigger. And for the input falling edge, there is no discharge process, passing through time delay t 2. Thus nd2_ a is opposite to the input phase, and the input and output phases are consistent through the third stage inverter, thereby completing half the delay. Referring specifically to fig. 4, which is an operation timing diagram of the delay cell of the present invention, after the input signal IN passes through half delaycell a, its output OUT _ a is IN opposite phase to the input signal, and the rising edge of the input signal IN is delayed by t1, and the falling edge of the input signal IN is delayed by t 2. Since the control voltage VCTL controls the discharge current of the half-side current starving inverter, the transmission time of the high level to low level conversion
Figure BDA0003512921350000081
Greater than the transit time for a low to high transition
Figure BDA0003512921350000082
Therefore, the delay t1 for the rising edge of the input signal is longer than the delay t2 for the falling edge of the input signal in half delaycell a. Similarly, the output signal OUT _ a of half delaycell a is used as the input signal of the second stage half delaycell B, and half delaycell B will delay the rising edge and the falling edge of the input signal OUT _ a by t1 and t2, respectively, so that the total delay of the whole coarse delay unit for the rising edge and the falling edge of the input signal IN is equal to t1+ t2, thereby ensuring that the duty ratios of the final output signal OUT and the input signal IN are kept unchanged.
The delay unit is divided into two parts which are completely the same and cascaded, the rising edge and the falling edge of each signal are delayed respectively, and the delay difference of the rising edge and the falling edge is reduced as much as possible, so that the pulse width of each signal can be kept unchanged.
In the coarse delay phase-locked loop circuit, in order to ensure that the paths of a third delay signal and a delay feedback signal, which reach a phase frequency detector 3PFD, of the coarse delay phase-locked loop are completely consistent, the coarse delay phase-locked loop circuit further comprises a second delay module 2, wherein a first input end of the second delay module 2 is connected with a second output end of the first delay module 1 and is used for receiving the first delay signal; a second input end of the second delay module 2 is connected to an output end of the delay link module 4, and is configured to receive the delay feedback signal; the control end of the second delay module 2 is connected with the output end of the charge pump; and under the action of the control voltage output by the charge pump, the second delay module 2 delays the second delay signal again to output a third delay signal and delays the delay feedback signal again to output a fourth delay signal. Correspondingly, a first input end of the phase frequency detector 3 is connected to a first output end of the second delay module 2, and a second input end of the phase frequency detector 3 is connected to a second output end of the second delay module 2, and is configured to output a phase difference signal according to the third delay signal CLK _ REF and the fourth delay signal CLK _ FB.
In the embodiment of the present invention, as shown in fig. 5, a schematic structural diagram of the phase frequency detector 3 of the present invention is shown; the phase frequency detector 3PFD includes a first flip-flop DFF1, a second flip-flop DFF2, a third flip-flop DFF3, a fourth flip-flop DFF4, and an enable control unit;
the clock end of the first trigger is a first input end of the phase frequency detector 3; the input end of the first trigger is connected with a power supply voltage VDD, and the output end of the first trigger is connected with the input end of the second trigger; the clock end of the second trigger is connected with the clock end of the first trigger;
the clock end of the third trigger is a second input end of the phase frequency detector 3; the input end of the third trigger is connected with a power supply voltage VDD, and the output end of the third trigger is connected with the input end of the fourth trigger; the clock end of the fourth trigger is connected with the clock end of the third trigger; the reset end of the third trigger is grounded VSS;
the output of the enabling control unit is connected with the reset end of the first trigger, the reset end of the second trigger and the reset end of the fourth trigger; the input end of the enabling control unit is connected with the output end of the control module 5;
and the phase frequency detector 3PFD outputs a phase difference signal through the output end of the second trigger and the output end of the fourth trigger according to the enabling control signal.
In the embodiment of the invention, the first flip-flop DFF1, the second flip-flop DFF2, the third flip-flop DFF3 and the fourth flip-flop DFF4 are all D-type flip-flops, and output results are changed according to the state of the input end D under the action of a clock signal.
In the embodiment of the present invention, the enable control unit includes a fourth inverter, a second and gate and an or gate;
the input end of the fourth phase inverter is connected with the output end of the control module 5, the output end of the fourth phase inverter is connected with the reset end of the first phase inverter and the first input end of the or gate, the first input end of the second and gate is connected with the output end of the second phase inverter, the second input end of the second and gate is connected with the output end of the fourth phase inverter, the output end of the second and gate is connected with the second input end of the or gate, and the output end of the or gate is connected with the reset end of the second phase inverter and the reset end of the fourth phase inverter.
The phase frequency detector 3PFD of the present invention compares the phase relationship between the reference clock signal (third delay signal) and the feedback signal (delay feedback signal), and outputs a phase difference signal indicating the phase relationship between the two signals. The phase difference signal is converted by the charge pump CP and the loop low pass filter LPF (loop low pass filter consisting of the charge pump CP output impedance and the capacitor C1) into a change in the VCDL control voltage. Under the action of the loop, the reference clock signal and the feedback signal are in phase by continuously adjusting the control voltage of the VCDL.
In the embodiment of the present invention, the first flip-flop and the third flip-flop have the same structure, the second flip-flop and the fourth flip-flop have the same structure, the first flip-flop and the second flip-flop form a first trigger branch for processing the third delay signal, and the third flip-flop and the fourth flip-flop form a second trigger branch for processing the fourth delay signal; the first triggering branch and the second triggering branch are symmetrical, so that the loads of the reference clock signal (third delay signal) and the feedback signal (delay feedback signal) are the same, the same environment is achieved, and the effect is better.
In the embodiment of the invention, the first trigger and the second trigger have the same structure; fig. 6 is a schematic circuit diagram of the first flip-flop and the third flip-flop;
the first trigger structure comprises a second PMOS tube P2, a third PMOS tube P3, a fourth NMOS tube N4, a fifth NMOS tube N5, a sixth NMOS tube N6, a fourth PMOS tube P4, a fifth PMOS tube P5, a seventh NMOS tube N7, a sixth PMOS tube P6, an eighth NMOS tube N8, a ninth NMOS tube N9, a seventh PMOS tube P7 and a tenth NMOS tube N10;
the source electrode of the second PMOS transistor P2 is connected to the power supply voltage VDD, the drain electrode of the second PMOS transistor P2 is connected to the source electrode of the third PMOS transistor P3, and the drain electrode of the third PMOS transistor P3 is connected to the drain electrode of the fourth NMOS transistor N4; the source electrode of the fourth NMOS transistor N4 is grounded, and the connection point of the gate electrode of the second PMOS transistor P2 and the gate electrode of the fourth NMOS transistor N4 is the input end of the first trigger structure; the gate of the third PMOS transistor P3 is connected to the third delay signal CLK _ REF;
a connection point of the drain of the third PMOS transistor P3 and the drain of the fourth NMOS transistor N4 is connected to the gate of the sixth NMOS transistor N6, the source of the sixth NMOS transistor N6 is connected to the drain of the fifth NMOS transistor N5, the source of the fifth NMOS transistor N5 is grounded, and the gate of the fifth NMOS transistor N5 is connected to the third delay signal CLK _ REF; the drain of the sixth NMOS transistor N6 is connected to the drain of the fourth PMOS transistor P4, the gate of the fourth PMOS transistor P4 is connected to the output of the fourth inverter N4, the source of the fourth PMOS transistor P4 is connected to the drain of the fifth PMOS transistor P5, the source of the fifth PMOS transistor P5 is connected to the supply voltage VDD, and the gate of the fifth PMOS transistor P5 is connected to the third delay signal CLK _ REF;
a connection point of the drain electrode of the fourth PMOS transistor P4 and the drain electrode of the sixth NMOS transistor N6 is a middle point, and the middle point is connected with the drain electrode of the seventh NMOS transistor N7, the gate electrode of the sixth PMOS transistor P6 and the gate electrode of the ninth NMOS transistor N9; the gate of the seventh NMOS transistor N7 is connected to the output terminal of the fourth inverter N4, the source of the sixth PMOS transistor P6 is connected to the power supply voltage VDD, the drain of the sixth PMOS transistor P6 is connected to the drain of the eighth NMOS transistor N8, the drain of the eighth NMOS transistor N8 is connected to the drain of the ninth NMOS transistor N9, the source of the ninth NMOS transistor N9 is grounded, and the gate of the eighth NMOS transistor N8 is connected to the output terminal of the fourth inverter N4;
a connection point of the drain of the sixth PMOS transistor P6 and the drain of the eighth NMOS transistor N8 is connected to the gate of the seventh PMOS transistor P7 and the gate of the tenth NMOS transistor N10, the source of the seventh PMOS transistor P7 is connected to the power supply voltage, the source of the tenth NMOS transistor N10 is grounded, and the drain of the seventh PMOS transistor P7 and the drain of the tenth NMOS transistor N10 are the output Q of the first flip-flop.
According to the invention, under the drive of a reset signal, when RST is high, the connected sixth NMOS tube N6 and fifth NMOS tube N5 are conducted, so that the voltage of the middle point A is reduced, at the moment, if CLK _ REF becomes low, because the fourth PMOS tube is closed, the high level when CLK _ REF becomes low is isolated and connected to the middle point A, thereby eliminating the intermediate state which possibly occurs at the point A, avoiding the logic error of the first trigger, causing the result of output error, and improving the accuracy of the control result of the coarse delay phase-locked loop circuit.
The second flip-flop and the fourth flip-flop of the present invention have the same structure, and fig. 7 is a schematic circuit structure diagram of the second flip-flop and the fourth flip-flop; take the second flip-flop as an example for a detailed description.
The second flip-flop is different from the first flip-flop in that an inverter chain 6 is added, an input end of the inverter chain 6 is connected with a drain electrode of the eleventh PMOS transistor and a drain electrode of the fifteenth NMOS transistor N15, and an output end of the inverter chain 6 is connected with a gate electrode of the twelfth PMOS transistor P12 and a gate electrode of the eighteenth NMOS transistor N18; the phase inverter chain 6 comprises four same phase inverter branches, each phase inverter branch comprises a PMOS (P-channel metal oxide semiconductor) tube and an NMSO (N-channel metal oxide semiconductor) tube which are connected in series, the grid electrode of the NMSO tube and the grid electrode of the PMOS tube are connected to be the input end of the phase inverter branch, the drain electrode of the NMSO tube and the drain electrode of the PMOS tube are connected to be the output end of the phase inverter branch, the source electrode of the PMOS tube is connected with the power supply voltage, the source electrode of the NMOS tube is grounded, and the phase inverter branches are cascaded through the input end and the output end.
Under the drive of a reset signal, when RST is high, a thirteenth NMOS tube N13 and a twelfth NMOS tube N12 which are connected, so that the voltage of an intermediate point A is reduced, and at the moment, if CLK _ REF becomes low, because the tenth PMOS tube is closed, the high level when CLK _ REF becomes low is isolated and connected to the intermediate point A, thereby eliminating the intermediate state which possibly occurs at the point A, avoiding the logic error of the second trigger, outputting the wrong result by the second trigger, and further improving the accuracy of the control result of the coarse delay phase-locked loop circuit.
The phase frequency detector can avoid leakage and intermediate level, and controls the fourth trigger through logic gate control.
The structure schematic diagram of the charge pump of the invention is shown in fig. 8, the charge pump adopts a drain terminal switch type, and in order to reduce the influence of channel length effect on the mismatch of charge and discharge current, a nested current source structure is adopted; in order to reduce charge injection and clock feed-through caused by a switching tube, a dummy tube is designed to prevent etching failure of a chip caused by excessive or insufficient exposure in the manufacturing process; in order to inhibit charge sharing, a charge pump with a differential structure is adopted, and the common-mode voltage of the two branches is the same by using an operational amplifier with a unit gain. The unit gain operational amplifier adopts a two-stage operational amplifier with common N-tube input.
Example two:
in order to achieve the above technical object, the present invention further provides a delay control circuit, which includes a coarse delay circuit and a fine delay circuit; the coarse delay circuit is the coarse delay phase-locked loop circuit; the adjacent clock signals output by the coarse delay circuit are connected with the input end of the fine delay circuit; the coarse delay circuit is used for controlling the delay range of the delay control circuit, and the fine delay circuit controls the output delay size based on the delay range. The coarse delay pll circuit is described in detail in the first embodiment, and is not described herein again.
In summary, the coarse delay phase-locked loop circuit and the delay control circuit of the invention can accurately control the delay range. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (10)

1. A coarse delay phase-locked loop circuit is characterized by comprising a phase frequency detector, a first delay module, a delay link module, a charge pump and a control module;
the signal input end of the first delay module is connected with a reference frequency, and the control end of the first delay module is connected with the output end of the charge pump; the first delay module outputs a first delay signal from a first output end of the first delay module and outputs a second delay signal from a second output end of the first delay module under the action of the control voltage output by the charge pump;
the signal input end of the delay link module is connected with the first output end of the first delay module, and the control end of the delay link module is connected with the output end of the charge pump; the delay link module delays the first delay signal again under the action of the control voltage output by the charge pump to output a delay feedback signal;
the input end of the control module is connected with a power supply voltage signal and an enabling signal, and the output end of the control module is connected with the enabling end of the phase frequency detector; the control module generates an enable control signal for controlling the phase frequency detector according to the power supply voltage signal and the enable signal;
a first input end of the phase frequency detector is connected with a first output end of the first delay module, and a second input end of the phase frequency detector is connected with an output end of the delay link module; based on the control action of the enabling control signal, the phase frequency detector outputs a phase difference signal according to the second delay signal and the delay feedback signal;
the input end of the charge pump is connected with the output end of the phase frequency detector; and the charge pump obtains the control voltage according to the phase difference signal.
2. The coarse delay phase-locked loop circuit of claim 1, wherein the control module comprises a first switch, a second switch, a first and gate, a first inverter, a second inverter, and a nor gate;
the input end of the first switch is connected with the output end of the first phase inverter, the output end of the first switch is connected with the input end of the first phase inverter and the first input end of the first AND gate, the first source end of the first switch is connected with a power supply voltage, and the second source end of the first switch is connected with the output end of the charge pump;
the input end of the second switch is connected with the output end of the second phase inverter, the output end of the second switch is connected with the input end of the second phase inverter, the first source end of the second switch is connected with the chip pin voltage, and the second source end of the second switch is connected with the output end of the charge pump;
a first input end of the NOR gate is connected with an output end of the first phase inverter, a second input end of the NOR gate is connected with a second input end of the first AND gate, and an output end of the NOR gate is connected with an input end of the second phase inverter; the output end of the first AND gate is connected with the enabling end of the phase frequency detector.
3. The coarse delay phase-locked loop circuit of claim 1, wherein the first delay module comprises two delay units, an input terminal of each delay unit is connected to the reference frequency through a buffer, and a control terminal of each delay unit is connected to an output terminal of the charge pump; the output end of each delay unit is also connected with a buffer.
4. The coarse delay phase-locked loop circuit of claim 3, wherein the delay chain module comprises N delay units, the N delay units are cascaded, and a control terminal of each delay unit is connected to the output terminal of the charge pump; wherein N is more than or equal to 3.
5. The coarse delay phase-locked loop circuit of claim 4, wherein the delay unit comprises two identical delay sub-units, the delay sub-units being cascaded; the delay subunit comprises a half-side current starvation type inverter and a buffer circuit;
the half-side current starvation type phase inverter comprises a first PMOS tube, a first NMOS tube, a second NMOS tube and a third NMOS tube; the grid electrode of the first PMOS tube and the grid electrode of the first NMOS tube are input ends of the delay unit, the source electrode of the first PMOS tube is connected with a power supply voltage, and the drain electrode of the first PMOS tube is connected with the drain electrode of the third NMOS tube; the grid electrode of the third NMOS tube is the control end of the delay unit, and the drain electrode of the third NMOS tube is connected with the source electrode of the first NMOS tube and the drain electrode of the second NMOS tube; the grid electrode of the second NMOS tube is connected with a power supply voltage, and the drain electrode of the second NMOS tube and the drain electrode of the third NMOS tube are grounded; the half-side current starvation type inverter is used for outputting a discharge current according to a control voltage;
the buffer circuit comprises a Schmitt inverter and a third inverter; the input end of the Schmidt phase inverter is connected with a connection point formed by connecting the drain electrode of the first PMOS tube and the drain electrode of the third NMOS tube; the output end of the Schmitt phase inverter is connected with the input end of the third phase inverter; and the buffer circuit is used for buffering the discharge current and then outputting the discharge current.
6. The coarse delay phase-locked loop circuit of claim 5, further comprising a second delay module, a first input of the second delay module being connected to a second output of the first delay module for receiving the first delay signal; a second input end of the second delay module is connected with an output end of the delay link module and is used for receiving the delay feedback signal; the control end of the second delay module is connected with the output end of the charge pump; and the second delay module delays the second delay signal again and delays the delay feedback signal again under the action of the control voltage output by the charge pump.
7. The coarse-delay phase-locked loop circuit of claim 6, wherein the phase frequency detector comprises a first flip-flop, a second flip-flop, a third flip-flop, a fourth flip-flop and an enable control unit;
the clock end of the first trigger is a first input end of the phase frequency detector; the input end of the first trigger is connected with a power supply voltage, and the output end of the first trigger is connected with the input end of the second trigger; the clock end of the second trigger is connected with the clock end of the first trigger; the clock end of the third trigger is a second input end of the phase frequency detector; the input end of the third trigger is connected with a power supply voltage, and the output end of the third trigger is connected with the input end of the fourth trigger; the clock end of the fourth trigger is connected with the clock end of the third trigger; the reset end of the third trigger is grounded;
the output of the enabling control unit is connected with the reset end of the first trigger, the reset end of the second trigger and the reset end of the fourth trigger; the input end of the enabling control unit is connected with the output end of the control module;
and the phase frequency detector outputs a phase difference signal through the output end of the second trigger and the output end of the fourth trigger according to the enabling control signal.
8. The coarse delay phase locked loop circuit of claim 7, wherein said first flip-flop and said third flip-flop are identical in structure, said second flip-flop and said fourth flip-flop are identical in structure, said first flip-flop and said second flip-flop forming a first trigger branch for processing said third delay signal, said third flip-flop and said fourth flip-flop forming a second trigger branch for processing said fourth delay signal.
9. The coarse delay phase-locked loop circuit of claim 8, wherein the enable control unit comprises a fourth inverter, a second and gate, and an or gate;
the input end of the fourth phase inverter is connected with the output end of the control module, the output end of the fourth phase inverter is connected with the reset end of the first phase inverter and the first input end of the OR gate, the first input end of the second AND gate is connected with the output end of the second phase inverter, the second input end of the second AND gate is connected with the output end of the fourth phase inverter, the output end of the second AND gate is connected with the second input end of the OR gate, and the output end of the OR gate is connected with the reset end of the second phase inverter and the reset end of the fourth phase inverter.
10. A time delay control circuit is characterized by comprising a coarse time delay circuit and a fine time delay circuit; the coarse delay circuit as recited in any one of claims 1-9; the adjacent clock signals output by the coarse delay circuit are connected with the input end of the fine delay circuit; the coarse delay circuit is used for controlling the delay range of the delay control circuit, and the fine delay circuit controls the output delay size based on the delay range.
CN202210156529.7A 2022-02-21 2022-02-21 Coarse delay phase-locked loop circuit and delay control circuit Pending CN114567317A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116232317A (en) * 2023-03-03 2023-06-06 芯动微电子科技(武汉)有限公司 High-speed frequency and phase discrimination circuit based on TSPC and phase-locked loop
CN116915243A (en) * 2023-09-12 2023-10-20 思特威(上海)电子科技股份有限公司 Phase-locked loop circuit and image sensor

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116232317A (en) * 2023-03-03 2023-06-06 芯动微电子科技(武汉)有限公司 High-speed frequency and phase discrimination circuit based on TSPC and phase-locked loop
CN116232317B (en) * 2023-03-03 2024-02-27 芯动微电子科技(武汉)有限公司 High-speed frequency and phase discrimination circuit based on TSPC and phase-locked loop
CN116915243A (en) * 2023-09-12 2023-10-20 思特威(上海)电子科技股份有限公司 Phase-locked loop circuit and image sensor
CN116915243B (en) * 2023-09-12 2023-12-26 思特威(上海)电子科技股份有限公司 Phase-locked loop circuit and image sensor

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