CN114566195A

CN114566195A - Reset system and method of hard disk controller, logic controller and voltage monitor

Info

Publication number: CN114566195A
Application number: CN202210179459.7A
Authority: CN
Inventors: 刘福东
Original assignee: Suzhou Inspur Intelligent Technology Co Ltd
Current assignee: Suzhou Inspur Intelligent Technology Co Ltd
Priority date: 2022-02-25
Filing date: 2022-02-25
Publication date: 2022-05-31

Abstract

The application discloses a reset system and method of a hard disk controller, a logic controller and a voltage monitor. The method comprises the following steps: receiving PG signals output to a logic controller after each power supply is electrified; inputting the PG signal to each diode in a logic controller, and determining the initial level output by each diode; determining a target level output to the voltage monitor by the logic controller according to the initial level output by each diode; and sending the target level to the voltage monitor so that the voltage monitor determines whether to execute the reset operation on the hard disk controller according to the target level. According to the method and the device, the logic controller is used for outputting the target level according to the PG signals output by each power supply, the target level is transmitted to the voltage monitor, and the voltage monitor determines the output condition of each power supply through the target level so as to determine whether to reset the hard disk controller. Therefore, the real-time monitoring of the power supply module is realized, and the effective operation of the hard disk controller is ensured.

Description

Reset system and method of hard disk controller, logic controller and voltage monitor

Technical Field

The present application relates to the field of hard disk control technologies, and in particular, to a reset system and method for a hard disk controller, a logic controller, and a voltage monitor.

Background

In the SSD collocation server/storage device, how to ensure the reliable operation of the SSD is important for the reliable hardware circuit design. For example: the power supply power-on time sequence and the reset signal power-on time sequence of some SSD controller chips are crucial, if the power-on time sequence hardware is unreasonable in design, the SSD controller is abnormal in power-on initialization and the initialization configuration parameters are abnormal in operation, the abnormal state of the SSD controller can cause the SSD controller to have an error without reason, the SSD disk can not be normally identified, and the SSD disk cannot be reliably operated and normally store user data.

Disclosure of Invention

To solve the above technical problem or at least partially solve the above technical problem, the present application provides a reset system, method, logic controller and voltage monitor for a hard disk controller.

According to an aspect of an embodiment of the present application, there is provided a reset system of a hard disk controller, the system including: the output end of the power supply module is connected with the input end of the logic controller, the output end of the logic controller is connected with the input end of the voltage monitor, and the voltage monitor is connected with the hard disk controller;

the power supply module is used for outputting a plurality of paths of PG signals to the logic controller by utilizing each power supply;

the logic controller is used for inputting the PG signal to each diode in the logic controller, determining the initial level output by each diode, and determining the target level output to the voltage monitor by the logic controller according to the initial level output by each diode; sending the target level to the power supply monitor, wherein the diodes correspond to the power supplies one to one;

and the power supply monitor is used for determining whether to execute reset operation on the hard disk controller according to the target level.

Furthermore, the logic controller comprises a plurality of branches, each branch is respectively connected with the power supply in the power supply module, and each branch comprises a resistor and a diode.

Further, the power supply monitor includes: the circuit comprises a SENSE input end, a SENSE output end, a CT end, a comparator and a delay, wherein the SENSE input end is connected with a positive input end of the comparator, a negative input end of the comparator is grounded, an output end of the comparator and the CT end are both connected with an input end of the delay, and an output end of the delay is connected with the SENSE output end.

According to another aspect of the embodiments of the present application, there is also provided a reset method of a hard disk controller, applied to a logical controller, the method including:

receiving PG signals output to the logic controller after each power supply is powered on;

inputting the PG signal to each diode in the logic controller, and determining an initial level output by each diode, wherein the diodes correspond to the power supplies one by one;

determining a target level output to a voltage monitor by the logic controller according to the initial level output by each diode;

and sending the target level to the voltage monitor so that the voltage monitor determines whether to execute a reset operation on the hard disk controller according to the target level.

Further, the inputting the PG signal to each diode in the logic controller and determining an initial level state of an output level of each diode includes:

inputting the PG signal to each diode in the logic controller, and determining the target output state of the corresponding power supply according to the PG signal through the diode;

and determining an initial level corresponding to the target output state based on a corresponding relation between a preset output state and a level, wherein the initial level is a low level when the target output state is an abnormal state, or the initial level is a high level when the target output state is a normal state.

Further, the determining the target level output by the logic controller to the voltage monitor according to the initial level output by each diode includes:

determining that a target level output to the voltage controller by the logic controller is a low level if at least one low level exists in initial levels output by the respective diodes;

or the like, or, alternatively,

and determining that the target level output to the voltage controller by the logic controller is a high level in the case that a low level does not exist in the initial levels output by the respective diodes.

According to another aspect of the embodiments of the present application, there is also provided a method for resetting a hard disk controller, applied to a voltage monitor, the method including:

receiving a target level output by the logic controller;

inputting the target level into a comparator inside the voltage monitor, and determining the level type of the target level through the comparator;

determining a delay time for controlling a hard disk controller to delay entering a reset state under the condition that the level type is used for indicating that the target level is a high level;

and sending a first control signal to the hard disk controller under the condition that the delay time is reached, wherein the first control signal is used for controlling the hard disk controller to enter a reset state.

Further, the method further comprises:

and sending a second control signal to the hard disk controller under the condition that the level type is used for indicating that the target level is a low level, wherein the second control signal is used for controlling the hard disk controller to enter a reset state.

According to another aspect of the embodiments of the present application, there is also provided a logic controller, including:

the receiving module is used for receiving PG signals output to the logic controller after each power supply is powered on;

the input module is used for inputting the PG signal to each diode in the logic controller and determining the initial level output by each diode, wherein the diodes correspond to the power supplies one by one;

the determining module is used for determining a target level output to the voltage monitor by the logic controller according to the initial level output by each diode;

and the sending module is used for sending the target level to the monitor so that the monitor determines whether to execute reset operation on the hard disk controller according to the target level.

According to another aspect of the embodiments of the present application, there is also provided a voltage monitor, including:

the receiving module is used for receiving the target level output by the logic controller;

the input module is used for inputting the target level into a comparator inside the voltage monitor, and the comparator is used for determining the level type of the target level;

a determining module, configured to determine a delay time for controlling a hard disk controller to delay entering a reset state when the level type is used to indicate that the target level is a high level;

and the sending module is used for sending a first control signal to the hard disk controller under the condition that the delay time is reached, wherein the first control signal is used for controlling the hard disk controller to enter a reset state.

According to another aspect of the embodiments of the present application, there is also provided a storage medium including a stored program that executes the above steps when the program is executed.

According to another aspect of the embodiments of the present application, there is also provided an electronic apparatus, including a processor, a communication interface, a memory, and a communication bus, where the processor, the communication interface, and the memory complete communication with each other through the communication bus; wherein: a memory for storing a computer program; a processor for executing the steps of the method by running the program stored in the memory.

Embodiments of the present application also provide a computer program product containing instructions, which when run on a computer, cause the computer to perform the steps of the above method.

Compared with the prior art, the technical scheme provided by the embodiment of the application has the following advantages: according to the embodiment of the application, the logic controller is used for outputting the target level according to the PG signals output by each power supply, the target level is transmitted to the voltage monitor, and the voltage monitor determines the output condition of each power supply through the target level so as to determine whether to reset the hard disk controller. Therefore, the real-time monitoring of the power supply module is realized, and the effective operation of the hard disk controller is ensured.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application.

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.

Fig. 1 is a schematic diagram of a reset system of a hard disk controller according to an embodiment of the present disclosure;

FIG. 2 is a timing diagram of delay times provided by an embodiment of the present application;

fig. 3 is a flowchart of a reset method of a hard disk controller according to an embodiment of the present disclosure;

FIG. 4 is a flowchart illustrating a method for resetting a hard disk controller according to another embodiment of the present application;

fig. 5 is a block diagram of a logic controller according to an embodiment of the present application;

fig. 6 is a block diagram of a voltage monitor apparatus according to an embodiment of the present application;

fig. 7 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application, it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments, and the illustrative embodiments and descriptions thereof of the present application are used for explaining the present application and do not constitute a limitation to the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another similar entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The embodiment of the application provides a reset system and method of a hard disk controller, a logic controller and a voltage monitor. The method provided by the embodiment of the invention can be applied to any required electronic equipment, for example, the electronic equipment can be electronic equipment such as a server and a terminal, and the method is not particularly limited herein, and is hereinafter simply referred to as electronic equipment for convenience in description.

According to an aspect of an embodiment of the present application, a reset system of a hard disk controller is provided, and fig. 1 is a schematic diagram of the reset system of the hard disk controller provided in the embodiment of the present application, as shown in fig. 1, the system includes: the power supply system comprises a power supply module 100, a logic controller 200, a voltage monitor 300 and a hard disk controller 400, wherein the output end of the power supply module 100 is connected with the input end of the logic controller 200, the output end of the logic controller 200 is connected with the input end of the voltage monitor 300, and the voltage monitor 300 is connected with the hard disk controller 400;

a power supply module 100 for outputting a plurality of PG signals to the logic controller by using each power supply;

the logic controller 200 is used for inputting the PG signal to each diode in the logic controller, determining the initial level output by each diode, and determining the target level output to the voltage monitor by the logic controller according to the initial level output by each diode; and sending the target level to a power supply monitor, wherein the diodes correspond to the power supplies one to one.

The power supply monitor 300 determines whether to perform a reset operation on the hard disk controller 400 according to the target level.

In the embodiment of the present application, the logic controller 200 includes a plurality of branches, each branch is connected to a power supply in the power supply module, and each branch includes a resistor and a diode.

As an example, as shown in fig. 1, the power module includes: P2V5_ NAND _ VCC power supply, P0V9 power supply, P1V2_ DRAM power supply, P1V8_ NAND _ IO power supply, P2V5_ DRAM _ VPP power supply, P0V6_ VREFCA power supply, P0V6_ DARM _ VTT power supply, P0V0_ VREF power supply, P3V3 power supply. Each power supply outputs a PG signal to the logic controller.

In this embodiment, the logic controller includes a plurality of branches, each branch is configured to receive a PG signal output by each power supply in the power supply module, each branch includes a resistor and a diode, each diode is configured to output a corresponding initial level according to the PG signal, and then the logic controller sums the initial levels output by the diodes to obtain a total target level.

As an example, as shown in FIG. 1, diode D1 is used to receive the PG signal output by the P2V5_ NAND _ VCC power supply, diode D2 is used to receive the PG signal output by the P0V9 power supply, diode D3 is used to receive the PG signal output by the P1V2_ DRAM power supply, diode D4 is used to receive the PG signal output by the P2V5_ DRAM _ VPP power supply, and so on, diode D8 is used to receive the PG signal output by the P3V3 power supply. The method is realized by an AND gate circuit formed by combining pure diodes, and the diodes need to select materials with small forward conduction voltage drop and small junction capacitance.

In the embodiment of the present application, each diode is used to detect a PG signal, and if a certain power supply does not output or the output is unstable, the corresponding PG signal outputs a low level. For example: the P2V5_ NAND _ VCC voltage is not output normally, and other 7 circuits are normal; then the cathode level of the diode D1 is low, and according to the unidirectional conductivity of the diode, the anode voltage of the diode D1 is also low, i.e. the overall target level after the diodes are combined is low, and the signal RST _ n passing through the voltage monitor delay logic control unit is low.

In this embodiment of the application, when the outputs of all the 8 power supplies are normal after being powered on, the overall PG signal after the diodes are combined outputs a high level, and the RST _ n signal passing through the voltage monitor delay logic control unit is a high level.

In the embodiment of the present application, the power supply monitor 300 includes: the circuit comprises a SENSE input end, a SENSE output end, a CT end, a comparator and a delayer, wherein the SENSE input end is connected with a positive input end of the comparator, a negative input end of the comparator is grounded, the output end of the comparator and the CT end are both connected with the input end of the delayer, and the output end of the delayer is connected with the SENSE output end.

In the embodiment of the present application, the power supply monitor is mainly used for controlling the time relationship between the power supply voltage of the system and the "RST _ n" signal of the hard disk controller. The power supply monitor may be implemented using an integrated IC chip. The C1 capacitance at CT is used to adjust the delay time between SENSE and SENSE _ OUT terminals, tdelay(s) [ cct (uf) x4] +40us, such as C1 capacitance selection 470pf, and in the case of high level, the delay time is about 1.92 ms.

In the embodiment of the application, in a scene where the power supply voltage in the system is not normally output in the power-on process, when the SENSE end (corresponding to the target level of the combining diode) is at a low level, the SENSE OUT end of the power supply monitor outputs the low level after passing through the comparator, and at this time, the hardware controller is reset, and the hard disk cannot be started.

For a scene that the power supply voltage in the hard disk is normally output in the power-on process, when the SENSE end is at a high level, the SENSE OUT end outputs the high level after the high level passes through the internal comparator and the Delay delayer, at the moment, the hard disk controller is reset, and the SSD is normally started. Specifically, when the SENSE terminal is at a high level, the Delay receives the high level input by the SENSE terminal and a capacitance value input by the C1 capacitor, then determines a Delay time according to the high level and the capacitance value, and after the Delay time is reached, the Delay outputs a signal to the hard disk controller, so that the hard disk controller resets.

It should be noted that different types of hard disk controllers have different requirements for time. The Delay timer may be set according to the ttinit time required by the hard disk controller (as shown in fig. 2), for example, after the power of the hardware controller is normal for at least 500us, the reset signal of the master is in "high level, unset state".

According to the system, on one hand, the logic controller is used for outputting the target level according to the PG signals output by each power supply, and the target level is transmitted to the voltage monitor, and the voltage monitor determines the output condition of each power supply through the target level, so that whether the hard disk controller is reset or not is determined. Therefore, the real-time monitoring of the power supply module is realized, and the effective operation of the hard disk controller is ensured. On the other hand, when the reset operation is determined to be executed on the hard disk controller, the reset delay time can be adjusted, the requirement of the power-on time sequence of the reset signal of the hard disk controller is met, and the power-on initialization success and the reliable operation after the power-on of the controller are guaranteed.

In addition, the application circuit and the device provided by the embodiment of the application have the advantages of simple design, convenience in application, small occupied PCB space and adjustable power-on time relation between the power supply in the hard disk mainboard and the reset signal of the controller. Fig. 3 is a flowchart of a reset method of a hard disk controller according to an embodiment of the present application, and as shown in fig. 3, the method includes:

in step S11, PG signals output to the logic controller after each power supply is powered on are received.

In step S12, the PG signal is input to each diode in the logic controller, and the initial level output by each diode is determined, where the diodes correspond to the power supplies one to one.

In the embodiment of the present application, the step S12 of inputting the PG signal to each diode in the logic controller and determining the initial level state of the output level of each diode includes the following steps a1-a 2:

step A1, the PG signal is input to each diode in the logic controller, and the target output state of the corresponding power supply is determined by the diode according to the PG signal.

In the embodiment of the application, the diode determines that the target output state of the corresponding power supply can be a normal state or an abnormal state according to the PG signal. The normal state is used for indicating that the power supply can normally output, and the abnormal state is used for indicating that the power supply does not output or the output is unstable.

Step a2, determining an initial level corresponding to the target output state based on the corresponding relationship between the preset output state and the level, wherein the initial level is a low level when the target output state is an abnormal state, or the initial level is a high level when the target output state is a normal state.

In step S13, the target level output by the logic controller to the voltage monitor is determined according to the initial level output by each diode.

In the embodiment of the present application, determining the target level output by the logic controller to the voltage monitor according to the initial level output by each diode includes: and determining that the target level output to the voltage controller by the logic controller is a low level when at least one low level exists in the initial levels output by the diodes.

In the embodiment of the present application, determining the target level output by the logic controller to the voltage monitor according to the initial level output by each diode includes: in the case where there is no low level among the initial levels output from the respective diodes, it is determined that the target level output from the logic controller to the voltage controller is a high level.

In step S14, the target level is sent to the voltage monitor, so that the voltage monitor determines whether to perform a reset operation on the hard disk controller according to the target level.

In the embodiment of the application, after receiving the target level, the logic controller sends the target level to the voltage monitor, and then the voltage monitor determines whether to perform a reset operation on the hardware controller according to the target level. For example: when the target level is low level, the voltage monitor performs reset operation on the hardware controller. When the target level is high level, the voltage monitor performs a reset operation on the hardware controller.

An embodiment of the present application further provides a reset method for a hard disk controller, and fig. 4 is a flowchart of the reset method for a hard disk controller provided in the embodiment of the present application, and as shown in fig. 4, the method includes:

in step S21, the target level output by the logic controller is received.

In step S22, the target level is input to a comparator inside the voltage monitor, and the level type of the target level is determined by the comparator.

In step S23, in the case where the level type is used to indicate that the target level is high, a delay time for controlling the hard disk controller to delay entering the unset state is determined.

In step S24, when the delay time is reached, a first control signal is sent to the hard disk controller, where the first control signal is used to control the hard disk controller to enter a reset state.

In this embodiment, in the case that the level type is used to indicate that the target level is a high level, the voltage monitor may perform a reset operation on the hard disk controller, and the voltage monitor may determine a delay time for the hard disk controller to delay entering the reset state, where the delay time may be determined according to a C1 capacitor at the CT end. And when the delay time is reached, sending a first control signal to the hard disk controller, wherein the first control signal is used for controlling the hard disk controller to enter a reset state.

In an embodiment of the present application, the method further comprises: and under the condition that the level type is used for indicating that the target level is low level, sending a second control signal to the hard disk controller, wherein the second control signal is used for controlling the hard disk controller to enter a reset state.

In the embodiment of the application, in a scene that the power supply voltage in the SSD board is not normally output in the power-on process, when the SENSE end (corresponding to the target level of the combining diode) is at a low level, the SENSE OUT end of the internal comparator outputs the low level, and at this time, the controller is reset, and the SSD cannot be started.

For a scene that the power supply voltage in the SSD board is normally output in the power-on process, when the SENSE end is at a high level, the high level outputs the high level through the SENSE OUT end of the internal comparator and the Delay delayer, at the moment, the controller is reset, the SSD is normally started, and the setting of the Delay delayer needs to be determined according to the tINIT time required by the SSD controller.

Fig. 5 is a block diagram of a logic controller provided in an embodiment of the present application, where the logic controller may be implemented as part of or all of an electronic device through software, hardware, or a combination of the software and the hardware.

As shown in fig. 5, the apparatus includes:

a receiving module 41, configured to receive PG signals output to the logic controller after each power supply is powered on;

an input module 42, configured to input the PG signal to each diode in the logic controller, and determine an initial level output by each diode, where the diodes correspond to the power supplies one to one;

a determining module 43, configured to determine a target level output by the logic controller to the voltage monitor according to the initial level output by each diode;

and a sending module 44, configured to send the target level to the voltage monitor, so that the voltage monitor determines whether to perform a reset operation on the hard disk controller according to the target level.

In the embodiment of the present application, the input module 42 is configured to input the PG signal to each diode in the logic controller, and determine a target output state of its corresponding power supply according to the PG signal through the diode; and determining an initial level corresponding to the target output state based on the corresponding relation between the preset output state and the level, wherein the initial level is a low level when the target output state is an abnormal state, or the initial level is a high level when the target output state is a normal state.

In the embodiment of the present application, the determining module 43 is configured to determine that the target level output to the voltage controller by the logic controller is a low level if at least one low level exists in the initial levels output by the respective diodes;

or the like, or, alternatively,

in this embodiment, the determining module 43 is configured to determine that the target level output to the voltage controller by the logic controller is a high level if there is no low level in the initial levels output by the respective diodes.

Fig. 6 is a block diagram of a voltage monitor provided in an embodiment of the present application, where the voltage monitor may be implemented as part of or all of an electronic device through software, hardware, or a combination of the software and the hardware.

As shown in fig. 6, the apparatus includes:

a receiving module 51, configured to receive a target level output by the logic controller;

an input module 52, configured to input the target level into a comparator inside the voltage monitor, and determine a level type of the target level through the comparator;

a determining module 53, configured to determine a delay time for controlling the hard disk controller to delay entering the reset state if the level type is used to indicate that the target level is a high level;

a sending module 54, configured to send a first control signal to the hard disk controller when the delay time is reached, where the first control signal is used to control the hard disk controller to enter a reset state.

An embodiment of the present application further provides an electronic device, as shown in fig. 7, the electronic device may include: the system comprises a processor 1501, a communication interface 1502, a memory 1503 and a communication bus 1504, wherein the processor 1501, the communication interface 1502 and the memory 1503 complete communication with each other through the communication bus 1504.

A memory 1503 for storing a computer program;

the processor 1501 is configured to implement the steps of the above embodiments when executing the computer program stored in the memory 1503.

The communication bus mentioned in the above terminal may be a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is shown, but this does not mean that there is only one bus or one type of bus.

The communication interface is used for communication between the terminal and other equipment.

The Memory may include a Random Access Memory (RAM) or a non-volatile Memory (non-volatile Memory), such as at least one disk Memory. Optionally, the memory may also be at least one memory device located remotely from the processor.

The Processor may be a general-purpose Processor, and includes a Central Processing Unit (CPU), a Network Processor (NP), and the like; the Integrated Circuit may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, a discrete Gate or transistor logic device, or a discrete hardware component.

In another embodiment provided by the present application, there is also provided a computer-readable storage medium having stored therein instructions, which when run on a computer, cause the computer to execute the method for resetting a hardware controller according to any of the above embodiments.

In yet another embodiment provided by the present application, there is also provided a computer program product containing instructions which, when run on a computer, cause the computer to perform the method for resetting a hardware controller as described in any of the above embodiments.

In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the application to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire (e.g., coaxial cable, fiber optic, digital subscriber line) or wirelessly (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that incorporates one or more of the available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., Solid State Disk), among others.

The above description is only for the preferred embodiment of the present application, and is not intended to limit the scope of the present application. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application are included in the protection scope of the present application.

The above description is merely exemplary of the present application and is presented to enable those skilled in the art to understand and practice the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A reset system for a hard disk controller, the system comprising: the output end of the power supply module is connected with the input end of the logic controller, the output end of the logic controller is connected with the input end of the voltage monitor, and the voltage monitor is connected with the hard disk controller;

2. The system of claim 1, wherein the logic controller comprises a plurality of branches, each branch being connected to a respective power supply in the power module, each branch comprising a resistor and a diode.

3. The system of claim 1, wherein the power supply monitor comprises: the circuit comprises a SENSE input end, a SENSE output end, a CT end, a comparator and a delay, wherein the SENSE input end is connected with a positive input end of the comparator, a negative input end of the comparator is grounded, an output end of the comparator and the CT end are both connected with an input end of the delay, and an output end of the delay is connected with the SENSE output end.

4. A reset method of a hard disk controller is applied to a logic controller, and is characterized by comprising the following steps:

5. The method of claim 4, wherein inputting the PG signal to each diode in the logic controller and determining an initial level state of the output level of each diode comprises:

inputting the PG signal into each diode in the logic controller, and determining the target output state of the corresponding power supply according to the PG signal through the diode;

6. The method of claim 4, wherein determining the target level output by the logic controller to the voltage monitor based on the initial level output by each diode comprises:

or the like, or, alternatively,

7. A method for resetting a hard disk controller, the method being applied to a voltage monitor, the method comprising:

receiving a target level output by the logic controller;

and sending a first control signal to the hard disk controller when the delay time is reached, wherein the first control signal is used for controlling the hard disk controller to enter a reset state.

8. The method of claim 7, further comprising:

9. A logic controller, comprising:

10. A voltage monitor, comprising: