CN114553194A

CN114553194A - Fusion logic-based static RS trigger with multiple layers of priorities

Info

Publication number: CN114553194A
Application number: CN202210183663.6A
Authority: CN
Inventors: 李强; 杨光亮; 王银浩
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2022-02-28
Filing date: 2022-02-28
Publication date: 2022-05-27

Abstract

The digital circuit is used as a basic stone of the integrated circuit, high-reliability logic operation is achieved by the logic tightness and reliability of the digital circuit, the boundary of human consciousness is greatly expanded, and an advanced logic operation unit becomes a key for opening the AI era. Digital systems have good robustness and can implement various complex and delicate operations, however, standard digital design flows are not satisfactory for digital-to-analog hybrid systems such as power supplies and data converters. These systems may not have a clock, require self-timed logic events triggered by delays or states, generate asynchronous clocks, and perform different work schedules at various stages of the asynchronous clock, asynchronous sequential systems have a number of reliability issues that differ from sequential logic. The invention provides a static RS trigger with multiple layers of priorities based on fusion logic, which is characterized in that a set function and a reset function with high priority and a low-priority enabling function are innovatively added on the basis of conventional set and reset, so that the problem of priority among complex time sequences is solved, the reliability is greatly improved, and the static RS trigger with multiple layers of priorities based on fusion logic has high device use efficiency.

Description

Fusion logic-based static RS trigger with multiple layers of priorities

Technical Field

The invention provides a static RS trigger with multiple layers of priorities based on fusion logic, which is characterized in that a set function and a reset function with high priority and a low-priority enabling function are innovatively added on the basis of conventional set and reset, so that the problem of priority among complex asynchronous time sequences is solved, the reliability is greatly improved, and the static RS trigger with multiple layers of priorities based on fusion logic has high device use efficiency.

Background

Digital circuits have been regarded as a fundamental stone of integrated circuits, and have been developed. The digital circuit enables high-reliability logic operation due to the tightness and reliability of the logic, the boundary of human consciousness is greatly expanded, and an advanced logic operation unit becomes a key for opening the AI era. The digital integrated circuit design has a series of standard units and tools, and further has programmable logic devices such as FPGA, CPLD and the like, and a digital system designed based on the resources has good robustness, can realize various complex and delicate operations, and can obtain huge benefits in the progress of the manufacturing process. Everything that is perfect always involves some drawbacks, no exception is given to digital integrated circuits, which are the pet in the semiconductor industry, and standard digital design flows are not satisfactory for digital-to-analog hybrid systems such as power supplies, data converters, etc. These systems may not have a clock, require self-timed logic events to be triggered by delays or states, generate asynchronous clocks, and perform different work schedules at various stages of the asynchronous clocks, asynchronous sequential systems have a number of reliability issues that are different from sequential logic.

Such circuits often require custom digital logic to implement, lack of standard tools, great time and effort to develop their functionality and reliability, and increased requirements related to the efficiency of use and structural robustness of the logic devices. A large amount of memories can be used in the design of a customized digital circuit, wherein RS triggering can be realized only by 8 switching elements, the advantages of definite function and simple structure are favored, but the RS trigger is used as a level trigger storage unit, and the setting and resetting functions are simultaneously used for self-timing logic and have metastable state and resetting risks. More complex functions can be realized only by matching with certain basic logic units, such as a JK trigger, which is often low in logic efficiency and occupies a large layout area.

Disclosure of Invention

The invention relates to a static RS trigger with multi-level priority based on fusion logic, which adopts two three-level fusion static logic gates to efficiently realize a target logic function. The pin diagram of the static RS flip-flop of the present invention is shown in fig. 1, which comprises a set of high priority set and reset inputs (SN, RN) and a medium priority low priority set and reset Enable (EN) in addition to the standard output (Q, QN) and the set of low priority set and reset terminals (S, R).

The logic structure of the invention is divided into three levels, the three levels respectively correspond to the priorities of different functions, and the logic block diagram is shown on the right of figure 1. The first level is the common setting and resetting function, which is high level effective and low level no action and corresponds to S, R pin in the figure; the second level is input enabling, the priority is higher than the common setting and resetting functions, the high level is effective, the low level shields the common setting and resetting functions, and the common setting and resetting functions correspond to an EN pin in the drawing; the third level is a high-priority setting and resetting function, the output is directly modified in the positive feedback, the priority is highest and higher than that of a common setting, resetting and enabling end, the low level is effective, the high level is invalid, and the high level corresponds to SN and RN pins in the graph.

The operation waveform of the logic signal is shown in fig. 3, wherein the level fluctuation indicates that the signal level changes all the time in the interval to represent the signal priority, the bottom of the trapezoid indicates the default inactive level polarity, and the top of the trapezoid indicates the active level polarity. The priority of the signal is clear at a glance in the figure, but the signal does not contain a metastable state characteristic, and in principle, any pair of set and reset limited positive feedback competition cannot be simultaneously invalid.

The circuit structure of the invention uses two three-level fusion static logic gates, the gate logic is actually single-level static gate logic, only one-time non-logic can realize multi-level positive logic function, the power consumption and the delay are close to the single-level gate logic, and simultaneously, the device efficiency is very high. The logic function of each three-level fusion static logic gate is formed by cascading an AND gate, an OR gate and an NAND gate, as shown in the right side of the figure 1, the first-level AND gate is connected with low-priority logic, the second-level AND gate is connected with positive feedback logic, and the third-level AND gate is connected with high-priority logic input. This way the conversion of nand gates to nor gates is achieved, the low priority logic passing through the nor gates and the high priority logic action passing through one nand gate, the high priority being achieved by the logic locking that occurs interleaved with the nand or nor positive feedback.

The switching stage of the invention is realized as shown in fig. 2, and the three-stage fusion static logic gate is formed by 8 switching devices of MP1-MP4(PMOS) and MN1-MN4(NMOS), and only consumes less than 3 devices per logic operation corresponding to six logic input ends. The MOS tube circled in the figure is related to the enabling of the low-priority setting and resetting, and can be deleted if not needed, the source drain of the device in the real coil is short-circuited (MN3), and the source drain of the device in the dotted circle is open-circuited (MP 1). Of course, the setting function and the resetting function of the high priority can also select shielding, the MP4 is disconnected, the MN4 is short-circuited, the resetting function of the high priority can be deleted, and the setting function of the high priority is the same as the setting function of the high priority. The traditional logic implementation of the invention needs 32 switching devices, the fusion logic of the invention only consumes 16 switching devices, and the gate-level series connection is shortened, thus obtaining better speed performance. In application, not all functions are necessary, 2 switching devices can be saved by deleting the single-side enabling function, and 2 switching devices can be saved by deleting any one set-reset function. The invention can obtain the RS trigger with forced reset or set only by ten switching elements, has great application value in the double-delay line asynchronous clock circuit, and the excessive high-priority control ends can reliably reset the system at any time without paying attention to the input state of the low-priority port.

The innovative multi-level priority structure has strong reliability and controllability, the hierarchical management of control signals is realized by fusing logic frameworks, the traditional logic short and flat control process is broken through, and the signals of all priorities are fused together through the conversion of the NAND gate and the NOR gate.

Drawings

FIG. 1 is a pin block diagram and a logic gate level block diagram of the present invention.

FIG. 2 is a tube level block diagram of the present invention.

FIG. 3 is a timing diagram of the present invention.

Detailed Description

The invention relates to a static RS trigger with multi-layer priority based on fusion logic, which can be formed by combining any controllable switch units, wherein the specific switch units can be relays, transistors, mechanical valves and the like.

The logic structure of the invention comprises 4 and, 2 or, 2 non-static logic operation functional units, the input ports of all the units are 12 in total, each static logic input signal end corresponds to a group of alternately conducted switches, and the switches are distributed in a pull-up logic switch unit and a pull-down logic switch unit in a logic dual mode. The whole structure of the invention adopts two three-level fusion static logic gates, the connection line of the fusion logic gate is shown on the right of figure 1, and the circuit has 5 input ends and 2 output ends. The five input ends comprise a group of low priority setting and resetting functions, a medium priority enabling function and a group of high priority setting and resetting functions, and the two output ends are inverted ports which are all arranged in a group of conventional memories.

The design of the invention is verified through standard 28nm process simulation, a circuit is manufactured by adopting a complementary MOS tube with a standard threshold, and the specific devices are arranged as shown in figure 2, so that 8 PMOS and 8 NMOS are consumed totally. A simplified diagram of the waveform of the logic function is shown in FIG. 3, which can clearly see the enabling of medium priority and the setting and resetting of high priority.

Claims

1. A static RS trigger with multi-layer priorities based on fusion logic is characterized in that the switching and locking characteristics of the logic conversion of a NAND gate and a NOR gate realize the setting and resetting control of different priorities, and directly link signals of different layers; meanwhile, a logic fusion structure is adopted, the integration of logic functions is realized, the utilization rate of a switch logic device is greatly improved, a shortened gate-level structure is realized, and the delay characteristic is also greatly reduced.

2. The static RS flip-flop with multi-layer priority based on fusion logic as described in claim 1, wherein the flip-flop and lock characteristics of the NAND gate and the NOR gate logic conversion are the core of the design and the basis of the implementation of the high-priority function; the low-priority working path is positively fed back through two NOR gates, the difference between the low-priority working path and a traditional RS trigger is avoided, the high-priority working path converts one NOR gate into a NAND gate to be coupled with the positive feedback of the other NOR gate, the forced control of the output state is realized, and the setting and resetting of the high priority are possible.

3. The static RS flip-flop with multi-level priority based on fusion logic as claimed in claim 1, wherein the different priority set/reset control ports comprise a set of low priority set/reset ports, a medium priority low priority enable port, and a set of important high priority set/reset ports in the full functional structure; the low-priority setting and resetting function has normal setting and resetting functions, and the low-priority enabling port can disable the low-priority setting and resetting functions; the high-priority setting and resetting port can cover the functions of the low-priority setting and resetting port and the enabling port thereof, and forcibly realizes the setting and resetting functions; the non-full-function structure takes a high-priority setting or resetting port as a core, and setting, resetting and enabling ports with different priorities can be reduced.

4. The fusion logic-based static RS flip-flop with multi-layer priority described in claim 1, wherein two three-level fusion static logic gates are adopted for logic implementation, so that the integration of logic functions is realized, the number of 32 switches in the traditional logic implementation is reduced by one time, and single-side logic is fused into one level, so that the logic delay of the low-medium priority function port is greatly reduced, and the working speed is improved.