CN114553159A - Operational amplifier and sampling and amplifying circuit - Google Patents

Operational amplifier and sampling and amplifying circuit Download PDF

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Publication number
CN114553159A
CN114553159A CN202210137368.7A CN202210137368A CN114553159A CN 114553159 A CN114553159 A CN 114553159A CN 202210137368 A CN202210137368 A CN 202210137368A CN 114553159 A CN114553159 A CN 114553159A
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signal
switch
transistor
pole
bias
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詹明韬
揭路
孙楠
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Tsinghua University
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Tsinghua University
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
    • H03F3/45484—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with bipolar transistors as the active amplifying circuit
    • H03F3/45488—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with bipolar transistors as the active amplifying circuit by using feedback means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/34—Negative-feedback-circuit arrangements with or without positive feedback
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/42—Amplifiers with two or more amplifying elements having their dc paths in series with the load, the control electrode of each element being excited by at least part of the input signal, e.g. so-called totem-pole amplifiers

Abstract

The disclosure relates to an operational amplifier and a sampling and amplifying circuit, wherein the operational amplifier comprises a first-stage circuit, a second-stage circuit and a third-stage circuit, wherein the first-stage circuit is used for obtaining a first output signal according to a first input signal and a common-mode feedback signal, and the first output signal generates a first bias signal and a second bias signal when being output to a split capacitor; a second stage circuit for generating a third bias signal and a fourth bias signal according to the first bias signal and the second bias signal; and the third-stage circuit is used for obtaining a second output signal according to the third bias signal and the fourth bias signal, and the common-mode feedback signal is obtained according to the second output signal. According to the operational amplifier disclosed by the invention, high speed and high gain can be ensured, and meanwhile, the operational amplifier is manufactured by adopting an advanced process and has higher robustness so as to improve the application range of the operational amplifier.

Description

Operational amplifier and sampling and amplifying circuit
Technical Field
The present disclosure relates to the field of integrated circuits, and more particularly, to an operational amplifier and a sampling and amplifying circuit.
Background
An operational amplifier (OP) is a high gain amplifier that can perform precise analog voltage signal addition, subtraction, and multiplication operations through negative feedback. An analog to digital converter (ADC) is an electronic system that converts an analog signal into a digital signal, and is usually implemented by an integrated circuit (chip). The high-speed (sampling rate >100MHz) and high-precision (digit >12) analog-to-digital converter is mainly applied to scenes such as wireless communication, radar detection and the like. In order to realize high speed and high precision, the analog-to-digital converter generally adopts a pipeline structure, which needs to amplify the residual difference voltage accurately and quickly. The mainstream approach to solve this problem is to implement the adc using a switched capacitor circuit including a fully differential operational amplifier.
The traditional high-speed operational amplifier has high power consumption and is difficult to be used in low-power consumption handheld equipment; the existing ring amplifier structure is generally very sensitive to the changes of process, temperature and power supply voltage, namely the robustness is poor, and the existing ring amplifier structure cannot be directly used in integrated circuit industrial products such as an analog-digital converter and the like. Therefore, it is desirable to design a high-speed operational amplifier suitable for advanced manufacturing process, so that the operational amplifier has higher robustness to improve the application range of the operational amplifier.
Disclosure of Invention
In view of the above, the present disclosure provides an operational amplifier and a sampling and amplifying circuit, and the operational amplifier according to the present disclosure can ensure high speed and high gain, and can be manufactured by an advanced process and has high robustness, so as to improve the application range of the operational amplifier.
According to an aspect of the present disclosure, there is provided an operational amplifier including: the first-stage circuit is used for obtaining a first output signal according to a first input signal and a common-mode feedback signal, and generating a first bias signal and a second bias signal when the first output signal is output to the split capacitor; a second stage circuit for generating a third bias signal and a fourth bias signal according to the first bias signal and the second bias signal; and the third-stage circuit is used for obtaining a second output signal according to the third bias signal and the fourth bias signal, and the common-mode feedback signal is obtained according to the second output signal.
In one possible implementation manner, the first input signal, the common-mode feedback signal, and the first output signal are differential signals, the first input signal includes a positive first input signal and a negative first input signal, the common-mode feedback signal includes a positive feedback signal and a negative feedback signal, the first output signal includes a positive first output signal and a negative first output signal, the first stage circuit includes a fully-differential amplification module and a feedback module, where: the feedback module is used for receiving the positive feedback signal and the negative feedback signal, the feedback module is connected with the fully-differential amplification module through a first switch, and the first switch is switched on or off under the control of a first control signal; the fully differential amplification module is configured to receive the positive first input signal and the negative first input signal, when the first switch is turned on, the positive feedback signal and the negative feedback signal provide common mode feedback for the fully differential amplification module, and the fully differential amplification module outputs the positive first output signal and the negative first output signal.
In one possible implementation manner, the first bias signal, the second bias signal, the third bias signal, and the fourth bias signal are differential signals, the first bias signal includes a positive first bias signal and a negative first bias signal, the second bias signal includes a positive second bias signal and a negative second bias signal, the third bias signal includes a positive third bias signal and a negative third bias signal, the fourth bias signal includes a positive fourth bias signal and a negative fourth bias signal, the second stage circuit includes a positive second stage circuit and a negative second stage circuit, and the method includes, for the positive second stage circuit or the negative second stage circuit: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a second switch, and a third switch, wherein a gate of the first transistor receives the positive first bias signal or the negative first bias signal, and receives a fifth bias signal through the second switch, a second pole of the first transistor is connected to ground, and a first pole of the first transistor is connected to a second pole of the fifth transistor, and outputs the positive third bias signal or the negative third bias signal; a gate of the second transistor receives the positive second bias signal or the negative second bias signal, and receives a sixth bias signal through a third switch, a first pole of the second transistor is connected to a power supply voltage, a second pole of the second transistor is connected to a first pole of the third transistor and a first pole of a fourth transistor, and the positive fourth bias signal or the negative fourth bias signal is output; a gate of the third transistor and a gate of the fourth transistor receive a seventh bias signal and an eighth bias signal, respectively; the grid electrode of the fifth transistor receives a second control signal, the second control signal is used for controlling the connection and disconnection between the first pole and the second pole of the fifth transistor, and the first pole of the fifth transistor is connected with the second pole of the third transistor and the second pole of the fourth transistor.
In a possible implementation manner, the second switch and the third switch further receive the first control signal, and the first control signal is further used for controlling on and off of the second switch and the third switch, wherein the second control signal controls off between a first pole and a second pole of the fifth transistor, the second stage circuit and the third stage circuit do not operate when the first control signal controls on of the second switch and the third switch, the fifth bias signal and the sixth bias signal act on the first transistor and the second transistor to generate a quiescent current of the second stage circuit, and the seventh bias signal and the eighth bias signal act on the third transistor and the fourth transistor to generate a quiescent current of the third stage circuit; the second control signal controls the conduction between the first pole and the second pole of the fifth transistor, when the first control signal controls the second switch and the third switch to be switched off, the second-stage circuit and the third-stage circuit work, and the third-stage circuit outputs the second output signal.
In one possible implementation, the second output signal is a differential signal, the second output signal includes a positive second output signal and a negative second output signal, the third stage circuit includes a positive third stage circuit and a negative third stage circuit, and the method includes, for the positive third stage circuit or the negative third stage circuit: a sixth transistor and a seventh transistor, wherein a gate of the sixth transistor is connected to the first pole of the first transistor, a second pole of the sixth transistor is connected to ground, and the first pole of the sixth transistor is connected to the second pole of the seventh transistor; a gate of the seventh transistor is connected to a second pole of the second transistor, a first pole of the seventh transistor is connected to a power supply voltage, and a second pole of the seventh transistor outputs the positive second output signal or the negative second output signal.
In a possible implementation manner, the operational amplifier is further connected to a bias signal generating circuit, and the fifth bias signal, the sixth bias signal, the seventh bias signal, and the eighth bias signal are generated by the bias signal generating circuit.
According to another aspect of the present disclosure, there is provided a sampling and amplifying circuit, including the operational amplifier described above, and a sampling capacitor and a feedback capacitor, the sampling and amplifying circuit being configured to: in a first stage, the sampling capacitor samples an analog input signal; in the second stage, the sampling capacitor outputs the first input signal to a first-stage circuit of the operational amplifier, and the first-stage circuit amplifies the first input signal to obtain a first output signal which is stored on the split capacitor; in a third phase, the split capacitor outputs a first bias signal and a second bias signal to a second-stage circuit of the operational amplifier; in a fourth stage, the second stage circuit of the operational amplifier outputs the third bias signal and the fourth bias signal to the third stage circuit of the operational amplifier, the third stage circuit of the operational amplifier outputs the second output signal, and the feedback capacitor feeds the second output signal back to the first stage circuit of the operational amplifier.
In a possible implementation manner, a first end of the sampling capacitor is connected to the analog input signal through a fourth switch, and a second end of the sampling capacitor is connected to the first stage circuit of the operational amplifier and the first end of the feedback capacitor and is connected to ground through a fifth switch; the first stage circuit of the operational amplifier is connected with the first end of the split capacitor, and the second end of the split capacitor is connected with the second stage circuit of the operational amplifier and is grounded through a sixth switch; the third-stage circuit of the operational amplifier is connected with the second end of the feedback capacitor and is grounded through a seventh switch; the sampling and amplifying circuit further receives a third control signal and a fourth control signal, the third control signal controls the fifth switch to be turned on or off, and the fourth control signal controls the seventh switch to be turned on or off.
In a possible implementation manner, in a first stage, the first control signal controls the fourth switch and the sixth switch to be turned on, and the first switch, the second switch and the third switch are turned on; the second control signal controls the first pole and the second pole of the fifth transistor to be turned off, the third control signal controls the fifth switch to be turned on, and the fourth control signal controls the seventh switch to be turned on; in a second stage, the first control signal controls the fourth switch and the sixth switch to be conducted, and the first switch, the second switch and the third switch are conducted; the second control signal controls the first pole and the second pole of the fifth transistor to be turned off, the third control signal controls the fifth switch to be turned off, and the fourth control signal controls the seventh switch to be turned on; in a third phase, the first control signal controls the fourth switch and the sixth switch to be turned off, and the first switch, the second switch and the third switch are turned off; the second control signal controls the first pole and the second pole of the fifth transistor to be turned off, the third control signal controls the fifth switch to be turned off, and the fourth control signal controls the seventh switch to be turned on; in a fourth stage, the first control signal controls the fourth switch and the sixth switch to be turned off, and the first switch, the second switch and the third switch are turned off; the second control signal controls the first pole and the second pole of the fifth transistor to be connected, the third control signal controls the fifth switch to be switched off, and the fourth control signal controls the seventh switch to be switched off.
According to the operational amplifier disclosed by the embodiment of the disclosure, the first-stage circuit obtains the first output signal according to the first input signal and the common-mode feedback signal, and the first output signal generates the first bias signal and the second bias signal when being output to the split capacitor, so that the split capacitor is utilized to realize current bias, and the robustness of the operational amplifier can be improved; the operational amplifier has high gain and dynamic bandwidth effect by arranging the cascade connection mode of the first-stage circuit, the second-stage circuit and the third-stage circuit, and faster establishment speed is obtained; the third stage circuit is used as an output stage to obtain a second output signal, so that the maximum output swing is realized. The high gain, high output swing offsets the adverse effects of the intrinsic gain of the advanced process and the supply voltage droop. The second output signal is obtained by the third bias signal and the fourth bias signal, and can not be limited by the current source, so that the speed of the operational amplifier can be improved. By the mode, the operational amplifier disclosed by the invention can be manufactured by adopting an advanced process and has higher robustness while ensuring high speed and high gain, so that the application range of the operational amplifier is enlarged.
Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.
Fig. 1 shows a schematic diagram of a conventional ring amplifier.
Fig. 2 shows another structure diagram of a conventional ring amplifier.
Fig. 3 illustrates an exemplary structural schematic of an operational amplifier according to an embodiment of the present disclosure.
Fig. 4 illustrates an exemplary structural schematic diagram of the first stage circuit 110 according to an embodiment of the disclosure.
Fig. 5 illustrates an exemplary structural schematic of the second stage circuit 120 and the third stage circuit 130 according to an embodiment of the disclosure.
Fig. 6 shows a schematic diagram of an exemplary structure of a bias signal generating circuit used in an embodiment of the present disclosure.
Fig. 7 shows an exemplary structural schematic diagram of the sampling and amplifying circuit 20 of the embodiment of the present disclosure.
Fig. 8 illustrates an exemplary timing diagram of various control signals used by the sampling and amplification circuit 20 of an embodiment of the present disclosure.
Detailed Description
Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers can indicate functionally identical or similar elements. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.
The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.
Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements and circuits that are well known to those skilled in the art have not been described in detail so as not to obscure the present disclosure.
Taking an operational amplifier applied to a high-speed and high-precision analog-to-digital converter as an example, a traditional high-speed operational amplifier generally adopts a two-stage circuit structure to realize high gain, a dominant pole is generated in a first-stage circuit through Miller compensation to stabilize the operational amplifier, and the operational amplifier with the structure has high power consumption, so that the power consumption of the high-speed and high-precision analog-to-digital converter applying the operational amplifier with the structure is more than hundreds of milliwatts, and the application range of the high-speed and high-precision analog-to-digital converter is greatly limited. In addition, in some application scenarios, the adc may need to be manufactured by advanced processes (low voltage, 28nm or less line width), and due to the reduced voltage and the reduced intrinsic gain of the transistor in the advanced processes, the design difficulty of the conventional high-speed operational amplifier is increased, which may increase the hardware cost of the operational amplifier, and further increase the hardware cost of the high-speed and high-precision adc.
On the basis, the prior art proposes a ring amplifier (ring amplifier), which uses a cascade of multi-stage amplifiers based on inverters to achieve high gain, and places the dominant pole of the amplifier at the output stage to reduce power consumption, where the theoretical power consumption under the same load and bandwidth is about one tenth of that of the conventional high-speed operational amplifier. However, the structure of the existing ring amplifier is generally very sensitive to the changes of the process, the temperature and the power supply voltage, and can not be directly used in industrial products.
Fig. 1 shows a schematic diagram of a conventional ring amplifier. As shown in fig. 1, the ring amplifier is coupled to an input signal VINAmplifying to obtain an output signal VO. The second stage of the ring amplifier comprises an N-channel field effect transistor and a P-channel field effect transistor (two transistors to the left in FIG. 1) having their gates connected together so that the sum of the gate-to-source voltages of the transistors equals the supply voltage VDD. When the threshold voltage of the transistor of the ring amplifier is changed due to the power supply voltage, the process deviation or the temperature change, the current of the second stage will be changed drastically, and similarly, the current of the third stage cascaded with the second stage will also be changed drastically, which causes the unit gain bandwidth and the phase margin of the ring amplifier to be changed drastically with the power supply voltage, the process deviation or the temperature change, and thus the ring amplifier cannot be used in practical applications.
Fig. 2 shows another structure diagram of a conventional ring amplifier. As shown in FIG. 2, the first stage of the ring amplifier is the same as that of FIG. 1, and receives an input signal VINAmplifying and outputting differential signal IP2And IN2(ii) a The second stage of the ring amplifier is biased by a tail current source and receives a differential signal IP2And IN2Outputs a differential signal OP2And ON2(ii) a The third stage is biased by a capacitor and receives a differential signal OP2And ON2To obtain an output signal VO. By biasingThe robustness of the ring amplifier is improved, but the tail current source of the second stage of the ring amplifier limits the grid source voltage and the slew rate of the transistor, so that the speed of the ring amplifier is reduced.
In view of the above, the present disclosure provides an operational amplifier and a sampling and amplifying circuit, and the operational amplifier according to the present disclosure can ensure high speed and high gain, and can be manufactured by an advanced process and has high robustness, so as to improve the application range of the operational amplifier.
Fig. 3 illustrates an exemplary structural schematic of an operational amplifier according to an embodiment of the present disclosure. As shown in fig. 3, the operational amplifier 10 includes:
the first stage circuit 110 is configured to obtain a first output signal according to the first input signal and the common mode feedback signal, and generate a first bias signal and a second bias signal when the first output signal is output to the split capacitor. The first stage circuit 110 may be a current-biased fully differential amplifier circuit (or may be a fully differential amplifier circuit in other implementations, and the disclosure is not limited thereto). The first input signal can be referred to as signal V in the following and related description of fig. 4IPSum signal VIMSee signal V below and in the description relating to fig. 4 for an example of a common-mode feedback signalOPSum signal VOMSee signal V below and in the associated description of fig. 4 for the first output signalO1PSum signal VO1MSee split capacitor C, described below and in relation to fig. 5ncFor example, the first bias signal may be referred to as signal V11 in the following and related description of fig. 5, and the second bias signal may be referred to as signal V21 in the following and related description of fig. 5.
And a second stage circuit 120 for generating a third bias signal and a fourth bias signal according to the first bias signal and the second bias signal. The second stage circuit 120 may be a pseudo-differential amplifier circuit. The third bias signal may be referred to as an example of the signal V31 in the following description related to fig. 5, and the fourth bias signal may be referred to as an example of the signal V41 in the following description related to fig. 5.
And the third stage circuit 130 is configured to obtain a second output signal according to the third bias signal and the fourth bias signal, and obtain the common mode feedback signal according to the second output signal. The third stage circuit 130 may be a pseudo-differential amplifier circuit. Wherein the second output signal can be referred to as signal V in the following and the related description of fig. 4 and 5OPSum signal VOMExamples of (2). The disclosed embodiment exemplifies that the second output signal is directly used as the common mode feedback signal.
According to the operational amplifier disclosed by the embodiment of the disclosure, the first-stage circuit obtains the first output signal according to the first input signal and the common-mode feedback signal, and the first output signal generates the first bias signal and the second bias signal when being output to the split capacitor, so that the split capacitor is utilized to realize current bias, and the robustness of the operational amplifier can be improved; the operational amplifier has high gain and dynamic bandwidth effect by arranging the cascade connection mode of the first-stage circuit, the second-stage circuit and the third-stage circuit, and faster establishment speed is obtained; the second output signal is obtained by the third stage circuit as an output stage, so that the maximum output swing is obtained. The high gain, high output swing offsets the adverse effects of the intrinsic gain of the advanced process and the supply voltage droop. The second output signal is obtained by the third bias signal and the fourth bias signal, and can not be limited by the current source, so that the speed of the operational amplifier can be improved. By the mode, the operational amplifier disclosed by the invention can be manufactured by adopting an advanced process and has higher robustness while ensuring high speed and high gain, so that the application range of the operational amplifier is enlarged.
Because the dominant pole of the operational amplifier is at the second output, the internal node parasitic capacitance of the operational amplifier is very small and has no extra compensation, so the power consumption of the operational amplifier can be reduced under the same gain-bandwidth product and load capacitance.
Fig. 4-5 are combined to show exemplary structures of the first stage circuit 110, the second stage circuit 120, and the third stage circuit 130, and then the principle that the operational amplifier 10 can be manufactured by advanced process and has high robustness while ensuring high speed and high gain is described.
Fig. 4 illustrates an exemplary structural schematic diagram of the first stage circuit 110 according to an embodiment of the disclosure.
As shown in fig. 4, in one possible implementation, the first input signal, the common-mode feedback signal, and the first output signal are differential signals, and the first input signal includes a forward first input signal VIPAnd a negative first input signal VIMThe common-mode feedback signal comprises a forward feedback signal VOPAnd a negative feedback signal VOMThe first output signal comprises a forward first output signal VO1PAnd a negative first output signal VO1M，
The first stage circuit comprises a fully differential amplification module and a feedback module, wherein:
the feedback module is used for receiving a forward feedback signal VOPAnd a negative feedback signal VOMThe feedback module is connected to the fully differential amplification module through a first switch S1, the first switch S1 is controlled by a first control signal phi2Controlling to be switched on or off;
the fully differential amplification module is used for receiving a forward first input signal VIPAnd a negative first input signal VIMWhen the first switch S1 is turned on, the positive feedback signal VOPAnd a negative feedback signal VOMProviding common-mode feedback for the fully-differential amplification module, and outputting a forward first output signal V by the fully-differential amplification moduleIPAnd a negative first output signal VIM。
The fully differential amplifying module may include transistors T1-T5, transistor T7, and resistors R1 and R2, which are described below and in relation to fig. 4, and the feedback module may include transistor T6, capacitors C1 and C2, and a first switch S1, which are described below and in relation to fig. 4.
As shown in fig. 4, the first stage circuit 110 may include a transistor T1-a transistor T7, resistors R1, R2, and capacitors C1, C2, a first switch S1,
wherein the gate of the transistor T1 receives the sixth bias signal BP1A first pole T11 is connected to the power supply voltage VDD, and a second pole T12 is connected to the first pole T21 of the transistor T2 and the first pole T31 of the transistor T3, respectively;
the gate of the transistor T2 and the gate of the transistor T4 are used as the first input terminal of the first stage 110 to receive the negative first input signal VIMThe second pole T22 of the transistor T2 and the first pole T41 of the transistor T4 are connected to the first end R11 of the resistor R1; the first terminal R11 of the resistor R1 is also used as the first output terminal of the first stage 110 for outputting the negative first output signal VO1MAs one of the differential output signals of the first stage circuit 110;
the gate of the transistor T3 and the gate of the transistor T5 are used as a second input terminal of the first stage 110, receiving a positive first input signal VIPThe second pole T32 of the transistor T3 and the first pole T51 of the transistor T5 are connected to the second terminal R22 of the resistor R2; the second terminal R22 of the resistor R2 is also used as the second output terminal of the first stage 110 for outputting the forward first output signal VO1PAs the other of the differential output signals of the first stage circuit 110;
the second end R12 of the resistor R1 is connected to the first end R21 of the resistor R2, the second end R12 of the resistor R1 and the first end R21 of the resistor R2 are also connected to the gate of the transistor T7, and are connected to the gate of the transistor T6 through the first switch S1. The first switch S1 may also receive a first control signal φ2The first control signal phi2The first switch S1 may be made conductive, for example, at a high level, and the first switch S1 may be made off at a low level.
The second pole T42 of the transistor T4 is connected to the first pole T61 of the transistor T6 and the second pole T52 of the transistor T5, the second pole T52 of the transistor T5 is connected to the first pole T71 of the transistor T7, the second pole T62 of the transistor T6 and the second pole T72 of the transistor T7 are connected to ground, and the gate of the transistor T6 is further connected to one end of the capacitor C1 and one end of the capacitor C2; the other end of the capacitor C1 and the other end of the capacitor C2 respectively receive a positive feedback signal VOPAnd a negative feedback signal VOM。
In the embodiment of the present disclosure, the transistor T1, the transistor T2, and the transistor T3 are PMOS transistors that are turned on at a low level, and the transistor T4, the transistor T5, the transistor T6, and the transistor T7 are NMOS transistors that are turned on at a high level, for example, to describe the technical solution of the present disclosure. In this case, the first electrode T11 of the transistor T1 is a source, and the second electrode T12 is a drain; the first electrode T21 of the transistor T2 is a source, and the second electrode T22 is a drain; the transistor T3 has a first electrode T31 as a source and a second electrode T32 as a drain. The first electrode T41 of the transistor T4 is a drain, and the second electrode T42 is a source; the first electrode T51 of the transistor T5 is a drain, and the second electrode T52 is a source; the first electrode T61 of the transistor T6 is a drain, and the second electrode T62 is a source; the transistor T7 has a first electrode T71 as a drain and a second electrode T72 as a source. The present application does not limit the types of transistors and the specific connection modes of the transistors in the first stage circuit 110, as long as the function of the fully differential amplifier can be achieved.
Fig. 5 illustrates an exemplary structural schematic of the second stage circuit 120 and the third stage circuit 130 according to an embodiment of the disclosure. As shown in fig. 5, the second stage circuit 120 and the third stage circuit 130 of the embodiment of the disclosure are closely related in structure, and thus are shown together in fig. 5.
As shown in fig. 5, in one possible implementation, the first bias signal, the second bias signal, the third bias signal, and the fourth bias signal are differential signals, the first bias signal includes a positive first bias signal V11 and a negative first bias signal (not shown), the second bias signal includes a positive second bias signal V21 and a negative second bias signal (not shown), the third bias signal includes a positive third bias signal V31 and a negative third bias signal (not shown), the fourth bias signal includes a positive fourth bias signal V41 and a negative fourth bias signal (not shown), the second stage circuit 120 includes a positive second stage circuit 1201 and a negative second stage circuit 1202, and the method includes, for the positive second stage circuit 1201 or the negative second stage circuit 1202:
a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a second switch S2, and a third switch S3, wherein,
the gate of the first transistor M1 receives the positive first bias signal V11 or the negative first bias signal, and receives the fifth bias signal BN through the second switch S21The second pole M12 is connected to ground, the first pole 11 is connected to the second pole M52 of the fifth transistor M5, and the positive third bias signal V31 or the negative third bias signal V52 is outputThree bias signals;
the gate of the second transistor M2 receives the positive second bias signal V21 or the negative second bias signal, and receives the sixth bias signal BP through the third switch S31A first pole M21 is connected to a power supply voltage, a second pole M22 is connected to a first pole M31 of the third transistor M3 and a first pole M41 of the fourth transistor M4, and a positive fourth bias signal V41 or a negative fourth bias signal V41 is output;
the gates of the third and fourth transistors M3 and M4 receive the seventh bias signal BN, respectively2And an eighth bias signal BP2；
The gate of the fifth transistor M5 receives the second control signal phiASecond control signal phiAFor controlling the switching on and off between the first pole M51 and the second pole M52 of the fifth transistor M5, the first pole M51 of the fifth transistor M5 is connected to the second pole M32 of the third transistor M3 and the second pole M42 of the fourth transistor M4.
For example, the structures of the positive second-stage circuit 1201 and the negative second-stage circuit 1202 may be the same, and thus only an exemplary structure of the positive second-stage circuit 1201 is shown in fig. 5. The positive signal may be provided to the positive second stage 1201 and a positive signal may be output, and the negative signal may be provided to the negative second stage 1202 and a negative signal may be output.
Second control signal phiAFor example, the fifth transistor M5 may be turned on between the first pole M51 and the second pole M52 at a high level, and turned off between the first pole M51 and the second pole M52 of the fifth transistor M5 at a low level.
The first bias signal, the second bias signal, the third bias signal, and the fourth bias signal may be signals in the second stage circuit 120 and the third stage circuit 130 when the second switch S2 and the third switch S3 are turned off and the first pole M51 and the second pole M52 of the fifth transistor M5 are turned on. Wherein the forward first bias signal V11 may be generated by only the split capacitor CncThe signal provided to the gate of the first transistor M1 on the forward second stage circuit 1201, the forward second bias signal V21 may be a signal provided only by the split capacitor CncProviding positive second stage powerThe gate of the second transistor M2 on line 1201. Similarly, the negative first bias signal and the negative second bias signal may be generated by the split capacitor C alonencAnd signals supplied to the gates of the first transistor M1 and the second transistor M2 in the negative second stage circuit 1201.
In one possible implementation, as shown in fig. 5, the second output signal is a differential signal, and the second output signal includes a positive second output signal VOPAnd a negative second output signal VOMThe third stage circuit 130 includes a positive third stage circuit 1301 and a negative third stage circuit 1302, and includes, for the positive third stage circuit 1301 or the negative third stage circuit 1302:
a sixth transistor M6 and a seventh transistor M7, wherein,
the gate of the sixth transistor M6 is connected to the first pole M11 of the first transistor M1, the second pole M62 of the sixth transistor M6 is connected to ground, and the first pole M61 of the sixth transistor M6 is connected to the second pole M72 of the seventh transistor M7;
the gate of the seventh transistor M7 is connected to the second pole M22 of the second transistor M2, the first pole M71 of the seventh transistor M7 is connected to the power supply voltage, and the second pole M72 of the seventh transistor M7 outputs the forward second output signal VOPOr negative second output signal VOM。
For example, the structures of the positive tertiary circuit 1301 and the negative tertiary circuit 1302 may be the same, so only an exemplary structure of the positive tertiary circuit 1301 is shown in FIG. 5. The positive signal may be provided to the positive tertiary circuit 1301 and outputs a positive signal, and the negative signal may be provided to the negative tertiary circuit 1302 and outputs a negative signal.
In this case, the first output signal V is positiveO1PAnd a negative first output signal VO1MBy splitting the capacitance CncCoupled to the second stage circuit 120, the third stage circuit 130 is directly connected to the second stage circuit 120 to generate a positive second output signal VOPAnd a negative second output signal VOM. The gate voltage bias of the first transistor M1 and the second transistor M2 in the second stage 120 can be achieved by using a split capacitor CncBut is different. When the second switch S2 and the third switch S3 are turned on, the fifth bias signal BN is received through the second switch S2 due to the gate of the first transistor M11The gate of the second transistor M2 receives the sixth bias signal BP through the third switch S31Therefore, the gate voltage bias of the first transistor M1 and the second transistor M2 can be set to BN respectively1And BP1。
In a possible implementation, the operational amplifier 10 is further connected to a bias signal generating circuit, a fifth bias signal BN1A sixth bias signal BP1Seventh bias signal BN2The eighth bias signal BP2Generated by a bias signal generating circuit.
The bias signal generating circuit may be, for example, a current mirror circuit. Fig. 6 shows a schematic diagram of an exemplary structure of a bias signal generating circuit used in an embodiment of the present disclosure.
Fig. 6 shows only the bias signals (e.g. including the fifth bias signal BN)1A sixth bias signal BP1The seventh bias signal BN2And an eighth bias signal BP2) An example of the manner of obtaining (c). When the bias signal generating circuit is as shown in fig. 6, the fifth bias signal BN1A sixth bias signal BP1The seventh bias signal BN2And an eighth bias signal BP2Or at other locations in the circuit, as long as each bias signal can be generated by a transistor in the bias signal generating circuit based on a current reference (e.g., provided by the current source in fig. 6); the bias signal generating circuit may also be other prior art realizable circuits dedicated to generating bias signals from a current reference. The present disclosure is not limited to a specific structure of the bias signal generating circuit, a specific manner of acquiring each bias signal, a voltage value of each bias signal, and whether or not there is a certain relationship between each bias signal.
In one possible implementation, the second switch S2 and the third switch S3 also receive the first control signal phi2The first control signal phi2And also for controlling the second switch S2 and the third switch S3 to be turned on and off, wherein,
second control signal phiAThe first control signal phi controls the fifth transistor M5 to be switched off between the first pole M51 and the second pole M522When the second switch S2 and the third switch S3 are turned on, the second stage circuit 120 and the third stage circuit 130 are not operated, and the fifth bias signal BN is generated1And a sixth bias signal BP1The first transistor M1 and the second transistor M2 are applied to generate the quiescent current of the second stage circuit 120, the seventh bias signal BN2And an eighth bias signal BP2The static current of the third stage circuit 130 is generated by acting on the third transistor M3 and the fourth transistor M4;
second control signal phi2The first control signal phi controls the conduction between the first pole M51 and the second pole M52 of the fifth transistor M5AWhen the second switch S2 and the third switch S3 are controlled to be turned off, the second stage circuit 120 and the third stage circuit 130 operate, and the third stage circuit outputs a second output signal.
For example, the first control signal phi2The second switch S2 and the third switch S3 may be made conductive at a high level, and the second switch S2 and the third switch S3 may be made off at a low level, for example. The second stage 120 and the third stage 130 may be set to operate at the first control signal phi2When the second switch S2 and the third switch S3 are turned off, i.e. only the split capacitor CncWhen the provided signals are input into the gates of the first transistor M1 and the second transistor M2, the task of amplifying the signals is performed under the first control signal phi2When the second switch S2 and the third switch S3 are turned on, the second stage circuit 120 and the third stage circuit 130 do not perform the task of amplifying the signal, and static current may be generated in the second stage circuit 120 and the third stage circuit 130. The gate voltage biases of the first transistor M1 and the second transistor M2 can be stabilized at the fifth bias signal BN1And a sixth bias signal BP1And thus the quiescent current of the second stage circuit 120 is insensitive to supply voltage, temperature, and process variations. The voltages output by the third transistor M3 and the fourth transistor M4 connected in parallel in the second stage circuit 120 serve as the bias voltage of the third stage circuit 130 (class AB amplifier output stage), and the gates of the third transistor M3 and the fourth transistor M4 are electrically connectedThe voltage bias can be stabilized at the seventh bias signal BN2And an eighth bias signal BP2And thus the quiescent current of the third stage circuit 130 is also insensitive to supply voltage, temperature and process variations. The operational amplifier of the present disclosure can be manufactured using advanced processes.
The operational amplifier of the present disclosure has a more robust operating point due to the use of the split capacitor to achieve current biasing. As can be seen from fig. 5, when the operational amplifier of the present disclosure amplifies a signal, the currents of the second stage circuit 120 and the third stage circuit 130 may not be limited by the tail current source, so that the second stage circuit 120 and the third stage circuit 130 may have a slew current much higher than a quiescent current, and a load (not shown) of the operational amplifier of the present disclosure may be rapidly charged and discharged, thereby implementing a high-speed operational amplifier.
Further, the second control signal phi can be used when the signal does not need to be amplifiedAThe fifth transistor M5 of the second stage circuit 120 is controlled to be turned off, thereby cutting off the current between the second stage circuit 120 and the third stage circuit 130 to save the power consumption of the operational amplifier. The second output signal (V) output by the third stage 130 of the operational amplifierOPAnd VOM) Global common mode feedback (see dashed box in fig. 4) is achieved by tail current transistors (i.e. transistor T6 in fig. 4) coupled to the first stage circuit 110 through capacitors C1 and C2, and the second output signal may be the same as the common mode feedback signal at this time, so that the operational amplifier has a stable output common mode voltage. Alternatively, other common mode feedback means may be used, such as using an error amplifier (not shown) to detect the signal VOPSum signal VOMAnd fed back to the first stage 110, etc., where the second output signal may be different from the common mode feedback signal, and the disclosure is not limited thereto.
Fig. 5 exemplifies that the fifth transistor M5 is connected to the first transistor M1, the third transistor M3, the fourth transistor M4, and the sixth transistor M6. It will be understood by those skilled in the art that the fifth transistor M5 may also be configured to connect the second transistor M2, the third transistor M3, the fourth transistor M4 and the seventh transistor M7, as long as the second control signal phi is enabledAControl the fifthWhen the transistor M5 is conducted between the first pole M51 and the second pole M52, the second stage circuit 120 has current flowing to the third stage circuit 130, and the second control signal φAWhen the fifth transistor M5 is controlled to be turned off between the first pole M51 and the second pole M52, the current between the second stage circuit 120 and the third stage circuit 130 is cut off, and the specific arrangement position of the fifth transistor M5 in the second stage circuit 120 is not limited in the present disclosure.
In the embodiment of the present disclosure, the second transistor M2, the third transistor M3, and the seventh transistor M7 are PMOS transistors turned on at a low level, and the first transistor M1, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are NMOS transistors turned on at a high level, for example, the technical solution of the present disclosure is described. In this case, the first pole M21 of the second transistor M2 is a source, and the second pole M22 is a drain; the first pole M31 of the third transistor M3 is a source, and the second pole M32 is a drain; the first pole M71 of the seventh transistor M7 is a source, and the second pole M72 is a drain. The first pole M11 of the first transistor M1 is a drain, and the second pole M12 is a source; the first pole M41 of the fourth transistor M4 is a drain, and the second pole M42 is a source; the first pole M51 of the fifth transistor M5 is a drain, and the second pole M52 is a source; the first pole M61 of the sixth transistor M6 is a drain, and the second pole M62 is a source. The present application does not limit the types of transistors and the specific connection manner of the transistors in the second stage circuit 120 and the third stage circuit 130.
FIG. 5 shows a split capacitor CncProvided in the second stage circuit 120 as an example. Those skilled in the art will appreciate that the split capacitance CncIt can be disposed in the first stage circuit 110, or disposed at other positions than the first stage circuit 110 and the second stage circuit 120, as long as the first stage circuit 110 can be connected to the split capacitor CncSo that the first output signal V is forwardO1PAnd a negative first output signal VO1MCan be in a split capacitor CncUpper storage and split capacitance CncCapable of being connected to the gates of the first and second transistors M1 and M2 such that the gate voltages of the first and second transistors M1 and M2 may be biased by employing a split capacitor CncAnd not, the present disclosure is directed to split capacitorsCncIs not limited in the manner of arrangement of (a).
The method realizes current bias through the split capacitor, so that the operational amplifier is insensitive to the integrated circuit process, the power supply voltage and the temperature change, the robustness problem of the operational amplifier is solved, and simultaneously, compared with the prior art, the method can not reduce the speed of the amplifier, so that the operational amplifier can be used as a high-gain high-speed operational amplifier suitable for advanced process manufacturing and can be adopted by industrial integrated circuit products. The operational amplifier comprises a three-stage circuit, and the second-stage circuit and the third-stage circuit form an AB class amplifier, so that the operational amplifier has the effect of dynamic bandwidth during amplification; meanwhile, the third-stage circuit is used as the dominant pole of the output stage, so that the noise of the front stage (second-stage circuit) of the amplifier can be filtered, and the operational amplifier disclosed by the invention has low-noise performance superior to that of the traditional amplifier.
When the operational amplifier of the embodiment of the present disclosure is used for amplifying a signal, in some scenarios, the operational amplifier is further connected to a sampling capacitor, and the signal to be amplified is sampled by the sampling capacitor and then amplified by the operational amplifier. In order to further improve the precision of the amplified signal due to the sampling thermal noise of the sampling capacitor, the present disclosure provides a sampling and amplifying circuit, which sets the control signals (including the control signal phi mentioned above) used by the sampling and amplifying circuit2、φAAnd phi, described below1、φA’) To achieve sample thermal noise cancellation.
In a possible implementation, the sampling and amplifying circuit 20 comprises the operational amplifier 10 described above, and a sampling capacitor CSA feedback capacitor CFBThe sampling and amplifying circuit 20 is configured to:
in the first stage, the capacitor C is sampledSFor analog input signal VINSampling is carried out;
in the second stage, the capacitor C is sampledSOutputs a first input signal (signal V)IPSum signal VIM) To the first stage circuit 110 of the operational amplifier 10, the first stage circuit 110 couples a first input signal (signal)Number VIPSum signal VIM) Amplifying to obtain a first output signal (signal V)O1PSum signal VO1M) And stored in a split capacitor CncThe above step (1);
in the third stage, the capacitor C is splitncOutputting the first bias signal (signal V11) and the second bias signal (V21) to the second stage circuit 120 of the operational amplifier 10;
in the fourth stage, the second stage circuit 120 of the operational amplifier 10 outputs the third bias signal (V31) and the fourth bias signal (V41) to the third stage circuit 130 of the operational amplifier 10, and the third stage circuit 130 of the operational amplifier 10 outputs the second output signal (signal VOPSum signal VOM) Feedback capacitance CFBThe second output signal (signal V)OPSum signal VOM) And fed back to the first stage circuit 110 of the operational amplifier 10.
An example of the specific operation of the sampling and amplifying circuit 20 at each stage can be seen from the following description and the related description of fig. 8. An exemplary structure of the sampling and amplifying circuit 20 will be described. Fig. 7 shows an exemplary structural schematic diagram of the sampling and amplifying circuit 20 of the embodiment of the present disclosure. For clarity of description, in FIG. 7, the capacitance C is splitncThe arrangement outside the first stage circuit 110 and the second stage circuit 120 of the operational amplifier 10 is taken as an example. Wherein the second output signal (signal V)OPSum signal VOM) In FIG. 7 with signal VOUTIt is shown that the second output signal may also be directly input to the first stage circuit 110 as a common mode feedback signal (see, for example, fig. 3).
In one possible implementation, the capacitor C is sampled, as shown in fig. 7SIs connected to the analog input signal V via a fourth switch S4INSampling capacitor CSIs connected to the first stage circuit 110 (e.g., the gates of T2 and T4, the gates of T3 and T5 in fig. 4) of the operational amplifier 10 and the feedback capacitor CFBAnd is connected to ground through a fifth switch S5;
the first stage 110 of the operational amplifier 10 (e.g., r11 and r22 in FIG. 4) is connected to a split capacitor CncE.g., a1 and a2 in fig. 5, respectivelySplit capacitor CncIs connected to the second stage circuit 120 (e.g., the gates of M1, M2 in fig. 5) of the operational amplifier 10 (e.g., b1 and b2 in fig. 5) and is connected to ground through the sixth switch S6;
the third stage 130 of the operational amplifier (e.g., B1 and B2 in FIG. 5) is connected to a feedback capacitor CFBAnd to ground through a seventh switch S7;
wherein the first control signal phi2The fourth switch S4 and the sixth switch S6 are controlled to be turned on or off, and the sampling and amplifying circuit 20 also receives a third control signal phi1And a fourth control signal phiA’The third control signal phi1Controls the fifth switch S5 to be turned on or off, and a fourth control signal phiA’Controls the seventh switch S7 to be turned on or off.
For example, the input terminals (i.e., the gates of M6 and M7 in fig. 5) of the third stage 130 of the operational amplifier are connected to the output terminals (i.e., M22 and M11 in fig. 5) of the second stage 120, and when the switch S7 is turned off, the amplified signal V is outputOUT。
The sampling and amplifying circuit 20 can receive a first control signal phi2The fourth switch S4 and the sixth switch S6 can be turned on and off by the first control signal phi2Control can be effected, for example, in a first control signal phi2The fourth switch S4 and the sixth switch S6 are controlled to be turned on when the high level is high, and the first control signal phi2And when the level is low, the fourth switch S4 and the sixth switch S6 are controlled to be turned off. First control signal phi2Meanwhile, the first switch S1 in the first stage circuit 110, the second switch S2 in the second stage circuit 120, and the third switch S3 are also controlled, as described above with reference to fig. 4 and 5.
The sampling and amplification circuit 20 may also receive a third control signal phi1A second control signal phiAAnd a fourth control signal phiA’The third control signal phi1Can be used to control the fifth switch S5 to turn on or off, for example, at the third control signal phi1The fifth switch S5 is controlled to be turned on when the high level is high, and the third control signal phi1The fifth switch S5 is controlled to be turned off at a low level. The second control signalφAThe fifth transistor M5 in the second stage circuit 120 can be controlled in a manner described above in connection with fig. 5. Fourth control signal phiA’Can be used to control the seventh switch S7 to be turned on or off, for example, at the fourth control signal phiA’The seventh switch S7 is controlled to be turned on at the high level and the fourth control signal phiA’The seventh switch S7 is controlled to be turned off at a low level.
The circuit 20 can convert an analog input signal VINAmplifying CS (sampling capacitor C)SCapacitance value of) divided by CFB (feedback capacitance C)FBCapacitance value of) times, can be directly applied to a pipeline analog-to-digital converter or other discrete-time amplification circuit.
Fig. 8 illustrates an exemplary timing diagram of various control signals used by the sampling and amplification circuit 20 of an embodiment of the present disclosure. Exemplary operation of the sampling and amplification circuit 20 of the disclosed embodiment at various stages of operation is described below in conjunction with fig. 4, 5, 7, and 8.
As shown in FIG. 8, the sampling and amplification circuit 20 may be controlled by a third control signal φ1A first control signal phi2A second control signal phiAWith a fourth control signal phiA’Four control signals, wherein the second control signal phiAWith a fourth control signal phiA’May be signals in opposite phases. By setting the levels of the respective control signals of fig. 8, one duty cycle of the sampling and amplifying circuit 20 of the embodiment of the present disclosure can be divided into 4 phases.
In the first phase, the first control signal phi2Controlling the fourth switch S4 and the sixth switch S6 to be turned on, and controlling the first switch S1, the second switch S2 and the third switch S3 to be turned on; second control signal phiAControlling the fifth transistor M5 to be turned off between the first pole M51 and the second pole M52, and the third control signal phi1Controls the fifth switch S5 to be conducted, and the fourth control signal phiA’Controlling the seventh switch S7 to be turned on;
in the second phase, the first control signal phi2Controlling the fourth switch S4 and the sixth switch S6 to be turned on, and controlling the first switch S1, the second switch S2 and the third switch S3 to be turned on; second control signal phiAControl ofThe fifth transistor M5 is turned off between the first pole M51 and the second pole M52, and the third control signal phi1Controls the fifth switch S5 to be turned off, and controls the fourth control signal phiA’Controlling the seventh switch S7 to be turned on;
in a third phase, the first control signal phi2Controlling the fourth switch S4 and the sixth switch S6 to be turned off, and controlling the first switch S1, the second switch S2 and the third switch S3 to be turned off; second control signal phiAControlling the fifth transistor M5 to be turned off between the first pole M51 and the second pole M52, and the third control signal phi1Controls the fifth switch S5 to be turned off, and controls the fourth control signal phiA’Controlling the seventh switch S7 to be turned on;
in the fourth stage, the first control signal phi2Controlling the fourth switch S4 and the sixth switch S6 to be turned off, and controlling the first switch S1, the second switch S2 and the third switch S3 to be turned off; second control signal phiAControlling the conduction between the first pole M51 and the second pole M52 of the fifth transistor M5, and the third control signal phi1Controls the fifth switch S5 to be turned off, and controls the fourth control signal phiA’The seventh switch S7 is controlled to be turned off.
For example, in the first phase, the third control signal φ may be set1A first control signal phi2A fourth control signal phiA’At a high level, the second control signal phiAIs low. As can be seen from fig. 4, 5 and 7, the first switch S1-the seventh switch S7 are both turned on, and the first pole M51 and the second pole M52 of the fifth transistor M5 are turned off. Analog input signal VINCan be input to the sampling capacitor CSSampling capacitor CSFor the analog input signal VINSampling is performed.
In the second phase, the third control signal φ may be set1A second control signal phiAAt a low level, the first control signal phi2A fourth control signal phiA’Is high. As can be seen from fig. 4, 5 and 7, at this time, the first switch S1-the fourth switch S4, the sixth switch S6 and the seventh switch S7 are all turned on, the fifth switch S5 is turned off, and the gap between the first pole M51 and the second pole M52 of the fifth transistor M5 is turned off. In the third control signal phi1From the first stage highAfter the level of the fifth switch S5 is turned off by the level transition to the low level, the input terminal of the operational amplifier 10 (i.e., the input terminal of the first stage 110, the gates of the transistors T2-T5) will fix the sampled thermal noise (e.g., the sampling capacitor C) with a mean square value of about kT/CSSCS), while the fourth switch S4 is still closed, the sampling capacitor CSLeft-side still connected analog input signal VINThus sampling thermal noise and sampled capacitance CSThe AC coupled component will be amplified by the first stage 110 of the operational amplifier 10 and stored in the split capacitor CncUp (i.e., correlated double sampling is done).
In the third stage, a third control signal φ may be set1A first control signal phi2A second control signal phiAAt a low level, the fourth control signal phiA’Is high. As can be seen from fig. 4, 5 and 7, the first switch S1 to the sixth switch S6 are all turned off, the seventh switch S7 is turned on, and the gap between the first pole M51 and the second pole M52 of the fifth transistor M5 is turned off. Due to the third control signal phi1The low level causes the fifth switch S5 to remain in the off state, and thus in the first control signal phi2After the second stage of high level is converted to low level to make the first switch S1-the fourth switch S4, and the sixth switch S6 also turned off, the split capacitor C is turned offncThe above signal can be regarded as the input equivalent offset voltage of the operational amplifier 10, and can cancel the sampling thermal noise fixed at the input end of the operational amplifier 10 when the switch S5 is turned off in the second stage.
In the fourth stage, the third control signal φ may be set1A first control signal phi2A fourth control signal phiA’At a low level, the second control signal phiAIs high. As can be seen from fig. 4, 5 and 7, the first switch S1-the seventh switch S7 are all turned off, and the first pole M51 and the second pole M52 of the fifth transistor M5 are turned on. Due to the third control signal phi1The low level makes the fifth switch S5 still in the off state, the first control signal phi2The low level makes the first switch S1-the fourth switch S4, the sixth switch S6 in the off state too, so that the second control signal φABy a third stageAfter the low level of the segment is converted to the high level to make the conduction between the first pole M51 and the second pole M52 of the fifth transistor M5, the second stage circuit 120 and the third stage circuit 130 of the operational amplifier 10 start to amplify the signals, and output the amplified signal V at the output terminal of the third stage circuit 130OUTThe amplified signal VOUTEliminating the sampling capacitor CSSo that the sampling and amplification circuit 20 of the present disclosure uses the sampling capacitor C under the same signal-to-noise ratio requirementSThe sampling capacitance can be much smaller than that of the traditional switched capacitor circuit, so that the load capacitance input by the sampling and amplifying circuit 20 is reduced, the power consumption of the circuit is reduced, and the circuit area is greatly reduced. Under the same circuit area, the sampling and amplifying circuit of the embodiment of the disclosure can improve the signal-to-noise ratio.
It will be understood by those skilled in the art that when the transistors in the operational amplifier 10 are of other types than those illustrated in fig. 4 and 5, the levels of the control signals may be adjusted accordingly, so as to achieve the effect of controlling the sampling and amplifying circuit 20 to operate in the sequence from the first stage to the fourth stage through the levels of the control signals. The present disclosure is not limited to a specific form of the level of each control signal.
The operational amplifier can be arranged in the sampling and amplifying circuit, the sampling and amplifying circuit can perform related double sampling on noise brought by the sampling capacitor by using the split capacitor through adjusting the on and off states of a switch in the circuit, so that the elimination of sampling thermal noise is realized, and the signal-to-noise ratio can be improved. Based on this, the operational amplifier and the sampling and amplifying circuit of the present disclosure can be used for a pipeline analog-to-digital converter with high speed, high precision and low power consumption, or used for all other applications requiring an integrated operational amplifier, such as a discrete time analog filter in a Sigma-Delta type analog-to-digital converter. Since the operational amplifier is a key module of these products, the operational amplifier of the present disclosure will make these products easy to implement in advanced low voltage processes and meet the index requirements of low power consumption.
Having described embodiments of the present disclosure, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen in order to best explain the principles of the embodiments, the practical application, or improvements made to the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims (9)

1. An operational amplifier, comprising:
the first-stage circuit is used for obtaining a first output signal according to a first input signal and a common-mode feedback signal, and generating a first bias signal and a second bias signal when the first output signal is output to the split capacitor;
a second stage circuit for generating a third bias signal and a fourth bias signal according to the first bias signal and the second bias signal;
and the third-stage circuit is used for obtaining a second output signal according to the third bias signal and the fourth bias signal, and the common-mode feedback signal is obtained according to the second output signal.
2. The operational amplifier of claim 1, wherein the first input signal, the common-mode feedback signal, and the first output signal are differential signals, wherein the first input signal comprises a positive-going first input signal and a negative-going first input signal, wherein the common-mode feedback signal comprises a positive-going feedback signal and a negative-going feedback signal, wherein the first output signal comprises a positive-going first output signal and a negative-going first output signal,
the first stage circuit comprises a fully differential amplification module and a feedback module, wherein:
the feedback module is used for receiving the positive feedback signal and the negative feedback signal, the feedback module is connected with the fully-differential amplification module through a first switch, and the first switch is switched on or off under the control of a first control signal;
the fully differential amplification module is configured to receive the positive first input signal and the negative first input signal, when the first switch is turned on, the positive feedback signal and the negative feedback signal provide common mode feedback for the fully differential amplification module, and the fully differential amplification module outputs the positive first output signal and the negative first output signal.
3. The operational amplifier of claim 2, wherein the first bias signal, the second bias signal, the third bias signal, and the fourth bias signal are differential signals, wherein the first bias signal comprises a positive-going first bias signal and a negative-going first bias signal, wherein the second bias signal comprises a positive-going second bias signal and a negative-going second bias signal, wherein the third bias signal comprises a positive-going third bias signal and a negative-going third bias signal, wherein the fourth bias signal comprises a positive-going fourth bias signal and a negative-going fourth bias signal,
the second level circuit includes positive second level circuit and negative direction second level circuit, to positive second level circuit or negative direction second level circuit, includes:
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a second switch, and a third switch, wherein,
a gate of the first transistor receives the positive first bias signal or the negative first bias signal, and receives a fifth bias signal through a second switch, a second pole of the first transistor is connected to ground, a first pole of the first transistor is connected to a second pole of the fifth transistor, and the first transistor outputs the positive third bias signal or the negative third bias signal;
a gate of the second transistor receives the positive second bias signal or the negative second bias signal, and receives a sixth bias signal through a third switch, a first pole of the second transistor is connected to a power supply voltage, a second pole of the second transistor is connected to a first pole of the third transistor and a first pole of a fourth transistor, and the positive fourth bias signal or the negative fourth bias signal is output;
a gate of the third transistor and a gate of the fourth transistor receive a seventh bias signal and an eighth bias signal, respectively;
the grid electrode of the fifth transistor receives a second control signal, the second control signal is used for controlling the connection and disconnection between the first pole and the second pole of the fifth transistor, and the first pole of the fifth transistor is connected with the second pole of the third transistor and the second pole of the fourth transistor.
4. The operational amplifier of claim 3, wherein the second switch and the third switch further receive the first control signal, the first control signal further being used to control the second switch and the third switch to turn on and off,
the second control signal controls the first pole and the second pole of the fifth transistor to be turned off, when the first control signal controls the second switch and the third switch to be turned on, the second stage circuit and the third stage circuit do not work, the fifth bias signal and the sixth bias signal are applied to the first transistor and the second transistor to generate the quiescent current of the second stage circuit, and the seventh bias signal and the eighth bias signal are applied to the third transistor and the fourth transistor to generate the quiescent current of the third stage circuit;
the second control signal controls the conduction between the first pole and the second pole of the fifth transistor, when the first control signal controls the second switch and the third switch to be switched off, the second-stage circuit and the third-stage circuit work, and the third-stage circuit outputs the second output signal.
5. The operational amplifier of any of claims 1-4, wherein the second output signal is a differential signal, the second output signal comprising a positive-going second output signal and a negative-going second output signal,
the third stage circuit includes positive third stage circuit and negative third stage circuit, to positive third stage circuit or negative third stage circuit, includes:
a sixth transistor and a seventh transistor, wherein,
a gate of the sixth transistor is connected to the first pole of the first transistor, a second pole of the sixth transistor is connected to ground, and the first pole of the sixth transistor is connected to the second pole of the seventh transistor;
a gate of the seventh transistor is connected to a second pole of the second transistor, a first pole of the seventh transistor is connected to a power supply voltage, and a second pole of the seventh transistor outputs the positive second output signal or the negative second output signal.
6. The operational amplifier of claim 4 or 5, further connected to a bias signal generating circuit, wherein the fifth bias signal, the sixth bias signal, the seventh bias signal, and the eighth bias signal are generated by the bias signal generating circuit.
7. A sampling and amplifying circuit comprising the operational amplifier of claims 1-6, and a sampling capacitor, a feedback capacitor,
the sampling and amplification circuit is configured to:
in a first stage, the sampling capacitor samples an analog input signal;
in the second stage, the sampling capacitor outputs the first input signal to a first-stage circuit of the operational amplifier, and the first-stage circuit amplifies the first input signal to obtain a first output signal which is stored on the split capacitor;
in a third phase, the split capacitor outputs a first bias signal and a second bias signal to a second-stage circuit of the operational amplifier;
in a fourth stage, the second stage circuit of the operational amplifier outputs the third bias signal and the fourth bias signal to the third stage circuit of the operational amplifier, the third stage circuit of the operational amplifier outputs the second output signal, and the feedback capacitor feeds the second output signal back to the first stage circuit of the operational amplifier.
8. The sampling and amplification circuit of claim 7,
the first end of the sampling capacitor is connected with the analog input signal through a fourth switch, and the second end of the sampling capacitor is connected with the first-stage circuit of the operational amplifier and the first end of the feedback capacitor and is connected with the ground through a fifth switch;
the first stage circuit of the operational amplifier is connected with the first end of the split capacitor, and the second end of the split capacitor is connected with the second stage circuit of the operational amplifier and is grounded through a sixth switch;
the third-stage circuit of the operational amplifier is connected with the second end of the feedback capacitor and is grounded through a seventh switch;
the sampling and amplifying circuit further receives a third control signal and a fourth control signal, the third control signal controls the fifth switch to be turned on or off, and the fourth control signal controls the seventh switch to be turned on or off.
9. The sampling and amplification circuit of claim 8,
in a first stage, the first control signal controls the fourth switch and the sixth switch to be turned on, and the first switch, the second switch and the third switch are turned on; the second control signal controls the first pole and the second pole of the fifth transistor to be turned off, the third control signal controls the fifth switch to be turned on, and the fourth control signal controls the seventh switch to be turned on;
in a second stage, the first control signal controls the fourth switch and the sixth switch to be conducted, and the first switch, the second switch and the third switch are conducted; the second control signal controls the first pole and the second pole of the fifth transistor to be turned off, the third control signal controls the fifth switch to be turned off, and the fourth control signal controls the seventh switch to be turned on;
in a third phase, the first control signal controls the fourth switch and the sixth switch to be turned off, and the first switch, the second switch and the third switch are turned off; the second control signal controls the first pole and the second pole of the fifth transistor to be turned off, the third control signal controls the fifth switch to be turned off, and the fourth control signal controls the seventh switch to be turned on;
in a fourth stage, the first control signal controls the fourth switch and the sixth switch to be turned off, and the first switch, the second switch and the third switch are turned off; the second control signal controls the first pole and the second pole of the fifth transistor to be connected, the third control signal controls the fifth switch to be switched off, and the fourth control signal controls the seventh switch to be switched off.
CN202210137368.7A 2022-02-15 2022-02-15 Operational amplifier and sampling and amplifying circuit Pending CN114553159A (en)

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