CN114551254A - Silicon-based fan-out type wafer level packaging method and packaging structure - Google Patents
Silicon-based fan-out type wafer level packaging method and packaging structure Download PDFInfo
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 92
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 92
- 239000010703 silicon Substances 0.000 title claims abstract description 92
- 238000000034 method Methods 0.000 title claims abstract description 50
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 50
- 239000000758 substrate Substances 0.000 claims abstract description 42
- 239000004033 plastic Substances 0.000 claims abstract description 34
- 239000003292 glue Substances 0.000 claims abstract description 19
- 238000000227 grinding Methods 0.000 claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 claims abstract description 13
- 238000011049 filling Methods 0.000 claims abstract description 9
- 238000002161 passivation Methods 0.000 claims abstract description 7
- 229910000679 solder Inorganic materials 0.000 claims abstract description 7
- 238000004140 cleaning Methods 0.000 claims abstract description 6
- 238000010330 laser marking Methods 0.000 claims abstract description 5
- 238000005520 cutting process Methods 0.000 claims abstract description 4
- 239000000463 material Substances 0.000 claims abstract description 4
- 239000003822 epoxy resin Substances 0.000 claims description 7
- 229920000647 polyepoxide Polymers 0.000 claims description 7
- 150000001875 compounds Chemical class 0.000 claims description 3
- 238000002347 injection Methods 0.000 claims description 3
- 239000007924 injection Substances 0.000 claims description 3
- 238000000465 moulding Methods 0.000 claims description 3
- 239000002861 polymer material Substances 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 239000004642 Polyimide Substances 0.000 claims description 2
- 229920001721 polyimide Polymers 0.000 claims description 2
- 239000002952 polymeric resin Substances 0.000 claims 1
- 229920003002 synthetic resin Polymers 0.000 claims 1
- 239000012634 fragment Substances 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 7
- 238000005530 etching Methods 0.000 description 7
- 229920005989 resin Polymers 0.000 description 6
- 239000011347 resin Substances 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 5
- 230000010354 integration Effects 0.000 description 5
- 238000012858 packaging process Methods 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 206010063385 Intellectualisation Diseases 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/293—Organic, e.g. plastic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3738—Semiconductor materials
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Abstract
The invention discloses a silicon-based fan-out wafer level packaging method and a silicon-based fan-out wafer level packaging structure, and belongs to the field of integrated circuit packaging. Providing a silicon substrate, and sequentially forming a trench groove and a large cavity on the front surface of the silicon substrate; grinding the back surface of the silicon substrate to enable the large cavity to form a through groove; fixing the silicon substrate and the embedded chip on the plastic package carrier plate by adopting a facedown process through temporary bonding glue in sequence; filling a plastic package material into the embedded chip, the silicon-based gap and the trench groove by adopting a plastic package process; removing the plastic package carrier plate and cleaning the temporary bonding glue to form a reconstituted wafer; sequentially manufacturing a passivation layer, a multilayer wiring and a solder mask on the front surface of the wafer; grinding, thinning and laser marking are carried out on the back of the wafer; and manufacturing the micro-convex points on the front surface of the wafer, and cutting the wafer into single packaged chips to finish packaging. The through groove is used for solving the problem of chip crack or silicon-based fragment caused by silicon bulge at the bottom of the groove in the existing chip mounting process; the wafer takes silicon as a substrate, so that the problems of warping and deviation in the tape-out process can be solved, and the wiring density can be improved.
Description
Technical Field
The invention relates to the technical field of integrated circuit packaging, in particular to a silicon-based fan-out type wafer level packaging method and a silicon-based fan-out type wafer level packaging structure.
Background
As chip process nodes continue to decrease, moore's law approaches its limits, and microsystems technologies based on high-performance wafer-level packaging are the inevitable choice in the post-moore era (moremore). The packaging is more and more important for improving the overall performance of the chip, and is also an important component for promoting the development of miniaturization, intellectualization, multifunctionalization and low power consumption of electronic devices. In the post-molar era, the prospect of advanced packaging is to realize heterogeneous chip integration, but there is a long way to achieve this goal.
The fan-out wafer level packaging can realize heterogeneous/heterogeneous chip integration, reduces the packaging size and improves the performance of the micro-system component at the same time of high integration. The mainstream fan-out package mainly comprises a resin fan-out package and a silicon-based fan-out package; resin fan-out packaging using Epoxy Mold Compound (EMC) to reconfigure the wafer is currently the most adopted fan-out scheme; compared with the resin fan-out type package, the silicon-based fan-out type package has the advantages of low cost, small warpage, high wiring density, good heat dissipation and simple manufacturing process, and is easier to realize the system integration of a large chip; however, from the viewpoint of dry etching, the silicon bulge at the bottom of the groove of the conventional silicon-based fan-out type packaging groove brings crack or silicon-based fragment abnormity when a Die Attach process is embedded into a chip; meanwhile, the etching morphology, the etching depth uniformity and the footing influence the dry film filling quality, and the problem of bubbles brings about layering abnormity; the shape is etched by a dry method, particularly, the process window of an etching angle is extremely small, the debugging is difficult to realize and the period is long; the existing silicon-based fan-out type packaging has insufficient integration capability on chips with different depths, although dry etching for multiple times can solve the problem, the packaging process, delivery time and cost are increased, and the dry film filling quality problem is also enlarged due to different depths.
Disclosure of Invention
The invention aims to provide a silicon-based fan-out wafer level packaging method and a packaging structure, which are used for solving the problems that the conventional resin fan-out packaging is warped and offset, high-density wiring cannot be carried out, and a chip crack or silicon-based fragment is caused by silicon protrusion at the bottom of a groove in the chip mounting process.
In order to solve the above technical problem, the present invention provides a silicon-based fan-out wafer level packaging method, comprising:
providing a silicon substrate, and sequentially forming a trench groove and a large cavity on the front surface of the silicon substrate;
grinding the back surface of the silicon substrate to enable the large cavity to form a through groove;
fixing the silicon-based embedded chip on the plastic package carrier plate by a face down process through temporary bonding glue in sequence;
filling a plastic package material into the embedded chip, the silicon-based gap and the trench groove by adopting a plastic package process;
removing the plastic package carrier plate and cleaning the temporary bonding glue to form a reconstituted wafer;
sequentially manufacturing a passivation layer, a multilayer wiring and a solder mask on the front surface of the wafer;
grinding, thinning and laser marking are carried out on the back of the wafer;
and manufacturing the micro-convex points on the front surface of the wafer, and cutting the wafer into single packaged chips to finish packaging.
Optionally, performing dry etching twice on the front surface of the silicon substrate to sequentially form a trench groove and a large cavity; wherein the content of the first and second substances,
the trench is etched in a segmented mode, and the width, the length and the depth of the trench body are not less than 10 micrometers; the upper opening of the trench is chamfered at an angle of 45-60 degrees, and the chamfer angle is not less than 3 mu m; the trench slots are interconnected, and the number of the interconnection channels between the adjacent trench slots is not less than 1.
Optionally, the large cavity is formed at the bottom of the trench, and is etched in segments, wherein the depth of the large cavity is not less than 50 μm, and the number of the large cavities is 1 or more; the side wall profile of the large cavity is linear and forms an angle of 87 +/-3 degrees with the horizontal plane; the upper opening of the large cavity is chamfered at an angle of 45-60 degrees, and the height of the chamfer is not less than 3 mu m.
Optionally, fixing the silicon-based embedded chip on the plastic package carrier plate by a face down process sequentially through the temporary bonding glue comprises:
the Trench grooves form bridges between the silicon substrate and the temporary bonding glue and serve as interconnection channels for subsequent plastic packaging glue injection and gas exhaust;
the embedded chip is positioned in the through groove of the silicon substrate and is fixed on the plastic package carrier plate through temporary bonding glue.
Optionally, the temporary bonding glue is a polymer material, and the thickness is not less than 1 μm.
Optionally, the molding compound is epoxy resin, or other resin or polyimide polymer materials.
The invention also provides a silicon-based fan-out type wafer-level packaging structure which is manufactured by the silicon-based fan-out type wafer-level packaging method.
The silicon-based fan-out wafer level packaging method and the packaging structure provided by the invention have the following beneficial effects:
(1) the through groove is used for solving the problem of chip crack or silicon substrate fragment caused by silicon bulge at the bottom of the groove in the existing silicon substrate fan-out type packaging and mounting process; the Trench groove bridging structure enables the plastic packaging process to be feasible; the Trench groove bridge structure is used as an interconnection channel to realize plastic package glue injection and exhaust functions, so that the generation of cavities and bubbles is effectively reduced and even avoided, and the risk of delamination and cracking of a package body is reduced;
(2) the embedded chip and the silicon substrate are fixed on the same horizontal plane through a temporary bonding film by adopting a Face down process, so that the problem of planarization caused by groove silicon protrusion, groove depth uniformity, etching morphology and footing in the conventional silicon substrate fan-out type packaging is solved; from the aspect of a dry etching process, the embedded chip and the silicon substrate are fixed on the plastic package carrier plate through the temporary bonding film by adopting a Face down process and are subjected to plastic package, the process window of the silicon substrate penetrating through the side wall angle of the groove is obviously enlarged, the debugging period and the debugging cost are reduced, and the process stability is further improved;
(3) filling epoxy resin into the embedded chip, the silicon-based gap and the trench groove by adopting a plastic packaging process, and reconstructing the wafer; the wafer takes silicon as a substrate, so that the problems of warping and deviation in the tape-out process can be solved, and the wiring density is improved;
(4) the chamfer angle is formed by segmented etching, so that the cracking risk caused by stress concentration at the position of a sharp corner is effectively reduced; epoxy resin is filled in place of a normally-used ground dry film in the conventional silicon-based fan-out type packaging by adopting a plastic packaging process, so that the packaging cost is greatly reduced;
(5) the invention provides a ground silicon fan-out type wafer level packaging method which is simple in process, low in cost and suitable for large-scale mass production, and the packaging body takes silicon as a base body, so that the heat dissipation capability is obviously enhanced.
Drawings
FIG. 1 is a schematic flow chart of a silicon-based fan-out wafer level packaging method according to the present invention;
FIG. 2 is a schematic diagram of a trench etched in a front side of a silicon substrate;
FIG. 3 is a schematic diagram of a large cavity formed in a trench using a step etch;
FIG. 4 is a schematic view of a trench groove and a large cavity chamfer;
FIG. 5 is a schematic view of a silicon-based backside ground down to a large cavity forming a through trench;
fig. 6 is a schematic diagram of a silicon substrate with its front surface bonded to a plastic package carrier and embedded in a chip;
FIG. 7 is a schematic diagram of epoxy filling the gap and the trench between the embedded chip and the silicon substrate;
fig. 8 is a schematic diagram of releasing the plastic package carrier and cleaning the residual temporary bonding film;
FIG. 9 is a schematic illustration of the fabrication of passivation layers, multilayer wiring and solder mask layers on the front side of a reconstituted wafer;
FIG. 10 is a schematic view of the back side of the reconstituted wafer being polished to thin without exposing the silicon substrate;
FIG. 11 is a schematic view of the backside of the reconstituted wafer being ground to thin and expose the silicon substrate but not the chips;
FIG. 12 is a schematic diagram illustrating grinding and thinning of the backside of the reconstituted wafer to the chip sacrificial layer;
FIG. 13 is a schematic view of a front surface with micro bumps fabricated by ball-planting or printing;
fig. 14 is a schematic diagram of a single-package chip package structure.
Detailed Description
The silicon-based fan-out wafer level packaging method and the packaging structure according to the present invention will be described in detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Example one
The invention provides a silicon-based fan-out wafer level packaging method, the flow of which is shown in figure 1, and the method comprises the following steps:
step S01, providing a silicon substrate, and performing dry etching twice on the front surface of the silicon substrate to sequentially form a trench groove and a large cavity;
step S02, grinding and thinning the back of the silicon substrate to form a through groove in the large cavity;
s03, fixing the silicon-based embedded chip on the plastic package carrier plate through temporary bonding glue by adopting a face down process in sequence;
step S04, filling epoxy resin into the embedded chip, the silicon-based gap and the trench by adopting a plastic package process, and enabling the epoxy resin to exceed the plastic package carrier plate to form a reconstituted wafer;
step S05, sequentially manufacturing a passivation layer, a multilayer wiring layer and a solder mask layer on the front side of the reconstructed wafer;
step S06, grinding, thinning and laser marking are sequentially completed on the back of the reconstructed wafer;
and step S07, manufacturing the micro bumps on the front surface of the reconstituted wafer, and cutting the wafer into single packaged chips.
Providing a silicon substrate 101, and etching a trench 102 on the front surface of the silicon substrate 101 in a segmented manner, as shown in fig. 2, wherein the length, the width and the depth of the trench 102 are not less than 10 μm, the opening of the trench 102 is chamfered at 45-60 degrees, and the height of the chamfer is not less than 3 μm, as shown in fig. 4.
Then, a large cavity 201 shown in fig. 3 is formed in the trench 102 by using a step etching method, wherein the depth of the large cavity 201 is not less than 50 μm, and the number of the large cavities is 1 or more; the side wall profile of the large cavity 201 is linear, the angle between the side wall profile and the horizontal plane is 87 +/-3 degrees, the upper opening of the large cavity 201 is chamfered at an angle of 45-60 degrees, and the height of the chamfer is not less than 3 mu m, as shown in figure 4. Finally, grinding and thinning the back surface of the silicon substrate 101 to a target thickness to form a through groove 103 in the large cavity 201, and cleaning the through groove, as shown in fig. 5;
then, the front side of the thinned silicon substrate 101 is bonded on a plastic package carrier 203 through a temporary bonding film 202, as shown in fig. 6;
then, the embedded chips 301 and 302 are loaded into the through groove 103, and the embedded chips 301 and 302 are fixed on the plastic package carrier plate 203 in the through groove 103 through the temporary bonding glue 202, as shown in fig. 6; the embedded chips can be heterogeneous or heterogeneous chips such as an FPGA, a DSP, a GPU, a CPU, a bridge chip and the like, the number of the embedded chips in the through groove 103 is 1 or more, the embedded chips with the same thickness or different thicknesses can be loaded, and the thickness of the embedded chips is required to be less than that of the reconstructed wafer; the embedded chip can be preset with a sacrificial layer according to the requirement of the packaging size.
Filling the gaps between the embedded chips 301 and 302 and the silicon substrate 101 and the trench groove 102 with epoxy resin 104 by using a resin-based plastic package process, as shown in fig. 7; and then, removing the bonded plastic package carrier plate 203 by adopting a pyrolytic bonding mode, cleaning the residual temporary bonding film 202, and reconstructing the wafer for molding, as shown in fig. 8.
As shown in fig. 9, a passivation layer 105 is formed on the front surface of the reconstituted wafer by spin coating, and a hole is formed at the position of the chip pad 303 by photolithography; and then, the manufacturing of the multilayer wiring 106 and the solder mask layer 107 is completed by sequentially adopting the methods of photoetching, physical vapor deposition, electroplating and chemical plating.
And then, grinding and thinning the back of the reconstructed wafer, and then sequentially finishing the laser marking. After grinding and thinning, the silicon substrate can not be exposed on the back of the wafer, as shown in fig. 10; after grinding and thinning, the silicon substrate can be exposed on the back surface of the wafer but the chip is not exposed, as shown in fig. 11; after the grinding and thinning, the back surface of the wafer can also be ground to a chip sacrificial layer (i.e. a non-functional area), as shown in fig. 12; the specific method can be selected according to the silicon-based thickness, the size of the embedded chip and the requirement of the customer packaging size.
Then, manufacturing the micro bumps 108 on the front surface by adopting a ball-planting or printing mode, as shown in fig. 13; a single package chip package structure, as shown in fig. 14.
Example two
A second embodiment provides a silicon-based fan-out wafer level package structure fabricated by the method of the first embodiment, and the structure is shown in fig. 14. The silicon-based fan-out type wafer level packaging structure comprises a silicon substrate 101, wherein a through groove is formed in the silicon substrate 101 and used for embedding chips (a chip 301 and a chip 302), and a plastic package material 104 is filled in a gap between the chip and the silicon substrate 101; a passivation layer 105, a multilayer wiring 106, a solder resist layer 107, and a micro bump 108 are sequentially formed on the front surface.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (7)
1. A silicon-based fan-out wafer level packaging method is characterized by comprising the following steps:
providing a silicon substrate, and sequentially forming a trench groove and a large cavity on the front surface of the silicon substrate;
grinding the back surface of the silicon substrate to enable the large cavity to form a through groove;
fixing the silicon-based embedded chip on the plastic package carrier plate by a face down process through temporary bonding glue in sequence;
filling a plastic package material into the embedded chip, the silicon-based gap and the trench groove by adopting a plastic package process;
removing the plastic package carrier plate and cleaning the temporary bonding glue to form a reconstituted wafer;
sequentially manufacturing a passivation layer, a multilayer wiring and a solder mask on the front surface of the wafer;
grinding, thinning and laser marking are carried out on the back of the wafer;
and manufacturing the micro-convex points on the front surface of the wafer, and cutting the wafer into single packaged chips to finish packaging.
2. The silicon-based fan-out wafer level packaging method of claim 1, wherein the trench and the large cavity are sequentially formed by performing two dry etches on the front surface of the silicon substrate; wherein the content of the first and second substances,
the trench is etched in a segmented mode, and the width, the length and the depth of the trench body are not less than 10 micrometers; the upper opening of the trench is chamfered at an angle of 45-60 degrees, and the chamfer angle is not less than 3 mu m; the trench slots are interconnected, and the number of the interconnection channels between the adjacent trench slots is not less than 1.
3. The silicon-based fan-out wafer level packaging method of claim 2, wherein the large cavity is formed at the bottom of the trench, and is etched in segments, the depth of the large cavity is not less than 50 μm, and the number of the large cavities is 1 or more; the side wall profile of the large cavity is linear and forms an angle of 87 +/-3 degrees with the horizontal plane; the upper opening of the large cavity is chamfered at an angle of 45-60 degrees, and the height of the chamfer is not less than 3 mu m.
4. The silicon-based fan-out wafer level packaging method of claim 1, wherein fixing the silicon-based embedded chip on the plastic package carrier plate sequentially through temporary bonding glue by a face down process comprises:
the Trench grooves form bridges between the silicon substrate and the temporary bonding glue, and serve as interconnection channels for subsequent plastic packaging glue injection and air exhaust;
the embedded chip is positioned in the through groove of the silicon substrate and is fixed on the plastic package carrier plate through temporary bonding glue.
5. The silicon-based fan-out wafer level packaging method of claim 4, wherein the temporary bonding glue is a polymer material with a thickness not less than 1 μm.
6. The method of claim 1, wherein the molding compound is an epoxy resin or other polymeric resin or polyimide.
7. A silicon-based fan-out wafer level package structure, manufactured by the silicon-based fan-out wafer level packaging method of any one of claims 1-6.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117059583A (en) * | 2023-10-12 | 2023-11-14 | 江苏芯德半导体科技有限公司 | Wafer-level fan-out type packaging structure with heterogeneous glue material and packaging method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117059583A (en) * | 2023-10-12 | 2023-11-14 | 江苏芯德半导体科技有限公司 | Wafer-level fan-out type packaging structure with heterogeneous glue material and packaging method thereof |
| CN117059583B (en) * | 2023-10-12 | 2024-01-09 | 江苏芯德半导体科技有限公司 | Wafer-level fan-out type packaging structure with heterogeneous glue material and packaging method thereof |
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