CN114550633B - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
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- CN114550633B CN114550633B CN202210187695.3A CN202210187695A CN114550633B CN 114550633 B CN114550633 B CN 114550633B CN 202210187695 A CN202210187695 A CN 202210187695A CN 114550633 B CN114550633 B CN 114550633B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
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Abstract
The embodiment of the invention discloses a display panel and display equipment, wherein a non-display area of the display panel comprises Q first grid driving circuits, driving chips and first decoding circuits; the driving chip comprises M first signal output ends and M second signal output ends; the first decoding circuit comprises M first signal input ends, a second signal input end and N third signal output ends; the first signal output end is electrically connected with the first signal input end in a one-to-one correspondence manner, and the second signal output end is electrically connected with the second signal input end; each first grid driving circuit is correspondingly connected to a third signal output end of the first decoding circuit; in the non-selection stage, the first decoding circuit is used for resetting each first gate driving circuit according to the reset control signal provided by the second signal output end. In the embodiment of the invention, the narrow frame is facilitated, and each first grid driving circuit is reset in the non-area selection stage, so that the correct area selection in the area selection stage is ensured, and the area selection accuracy is improved.
Description
Technical Field
The embodiment of the invention relates to the technical field of display panels, in particular to a display panel and display equipment.
Background
With the progress and development of technology, the use of display panels has been advanced into various electronic products due to the improvement of living standard. Display panels are manufactured in large quantities and display requirements for the display panels are increasing.
Fingerprints are natural to everyone, and with the development of technology, various display devices with fingerprint identification functions are appeared on the market.
However, the screen occupation of the existing display device with the fingerprint identification function is relatively low, and the requirement of a user on a narrow frame with a high screen occupation ratio cannot be met.
Disclosure of Invention
The embodiment of the invention provides a display panel and display equipment, which are used for realizing a narrow frame.
An embodiment of the present invention provides a display panel including: a display region and a non-display region surrounding the display region;
The display area comprises a plurality of fingerprint identification units which are arranged in an array along a first direction and a second direction, wherein the first direction and the second direction are intersected;
The non-display area comprises Q first grid driving circuits and driving chips;
The first grid driving circuit is electrically connected with at least two rows of fingerprint identification units extending along the first direction;
the driving chip comprises M first signal output ends and M second signal output ends;
The non-display area further comprises a first decoding circuit, wherein the first decoding circuit comprises M first signal input ends, second signal input ends and N third signal output ends, M is more than or equal to 1 and less than or equal to Q and less than or equal to N, and M, Q and N are both positive integers;
the first signal output ends are electrically connected with the first signal input ends in a one-to-one correspondence manner, and the second signal output ends are electrically connected with the second signal input ends;
each first gate driving circuit is correspondingly connected to one third signal output end of the first decoding circuit;
the display panel comprises a non-selection stage;
In the non-selection stage, the first decoding circuit is configured to reset each of the first gate driving circuits according to a reset control signal provided by the second signal output terminal.
The embodiment of the invention also provides display equipment, which comprises the display panel;
the display panel includes a fingerprint identification stage including a non-selection stage.
According to the display panel provided by the embodiment of the invention, the first decoding circuit arranged between the driving chip and the first grid driving circuit is arranged in the non-display area, so that the driving chip can provide signals for the first decoding circuit through a small number of signal output ends, the first decoding circuit can provide signals for a large number of first grid driving circuits after decoding, the wiring quantity of the non-display area is effectively reduced, and the narrow frame of the display panel is facilitated. In addition, each first gate driving circuit is reset in the non-area selection stage, so that each first gate driving circuit is in the same reset state before area selection, and then the area can be correctly selected in the area selection stage, the error triggering of the unselected first gate driving circuits is avoided, and the area selection accuracy is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, a brief description will be given below of the drawings required for the embodiments or the description of the prior art, and it is obvious that although the drawings in the following description are specific embodiments of the present invention, it is obvious to those skilled in the art that the basic concepts of the device structure, the driving method and the manufacturing method, which are disclosed and suggested according to the various embodiments of the present invention, are extended and extended to other structures and drawings, and it is needless to say that these should be within the scope of the claims of the present invention.
Fig. 1 is a schematic diagram of a display panel according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of another display panel according to an embodiment of the present invention;
FIG. 3 is a schematic view of another display panel according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a decoding module in a first decoding circuit;
FIG. 5 is a circuit schematic of a selected decoding module;
FIG. 6 is a schematic circuit diagram of an unselected decoding module;
FIG. 7 is a schematic view of a display panel according to another embodiment of the present invention;
Fig. 8 is a timing diagram of the display panel shown in fig. 7.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described by means of implementation examples with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments obtained by those skilled in the art based on the basic concepts disclosed and suggested by the embodiments of the present invention are within the scope of the present invention.
Referring to fig. 1, a schematic diagram of a display panel according to an embodiment of the invention is shown. The display panel provided in this embodiment includes: a display area 10 and a non-display area 20 surrounding the display area 10; the display area 10 comprises a plurality of fingerprint identification units 11 arranged in an array along a first direction X and a second direction Y, wherein the first direction X and the second direction Y intersect; the non-display area 20 includes Q first gate driving circuits 30 and driving chips 40; the first gate driving circuit 30 is electrically connected to at least two rows of fingerprint recognition units 11 extending in the first direction X; the driving chip 40 includes M first signal output terminals STV and second signal output terminals IC-VG; the non-display area 20 further includes a first decoding circuit 50, where the first decoding circuit 50 includes M first signal input terminals S, a second signal input terminal VG, and N third signal output terminals OUT, where M < Q < N > 1, and M, Q and N are positive integers; the first signal output ends STV are electrically connected with the first signal input ends S in a one-to-one correspondence manner, and the second signal output ends IC-VG are electrically connected with the second signal input ends VG; each first gate driving circuit 30 is correspondingly connected to a third signal output terminal OUT of the first decoding circuit 50; the display panel comprises a non-selection stage; in the non-selection stage, the first decoding circuit 50 is configured to reset each of the first gate driving circuits 30 according to the reset control signal provided from the second signal output terminal IC-VG.
In this embodiment, the display panel is a display panel with a fingerprint recognition function. Optionally, the display panel is a full-screen fingerprint identification display panel, the fingerprint identification area coincides with the display area 10, and the fingerprint identification units 11 are distributed in the whole display area 10; specifically, the display area 10 includes a plurality of fingerprint recognition units 11 arranged in an array along a first direction X and a second direction Y, where the first direction X and the second direction Y intersect. In other embodiments, the display panel may be a partial fingerprint identification display panel, where the fingerprint identification area coincides with a partial area of the display area, and the fingerprint identification units are distributed in the fingerprint identification area; specifically, the fingerprint identification area of the display area comprises a plurality of fingerprint identification units which are arranged in an array along a first direction and a second direction, wherein the first direction and the second direction are intersected. The display panel with the fingerprint recognition function provided by the embodiment of the invention is any display panel with the fingerprint recognition function, and the structure of the display panel, the structure of the fingerprint recognition unit in the display panel and the like are not specifically described herein.
The periphery of the display area 10 is a non-display area 20, and the non-display area 20 is provided with a peripheral circuit for driving the display area 10 to perform operations such as display, touch control, fingerprint identification and the like. In this embodiment, only the peripheral circuits in the non-display area 20 for driving the display area 10 to perform fingerprint identification operation are described in detail, and the other functional peripheral circuits in the non-display area will not be described in detail.
The non-display area 20 includes Q first gate driving circuits 30 and a driving chip 40, and the first gate driving circuits 30 are electrically connected to at least two rows of fingerprint recognition units 11 extending along the first direction X. The selectable display area 10 includes Q fingerprint identification sections 12 sequentially arranged along the Y direction, each fingerprint identification section 12 includes at least two rows of fingerprint identification units 11 extending along the X direction, and a first gate driving circuit 30 correspondingly drives each fingerprint identification unit 11 in one fingerprint identification section 12. The Q first gate driving circuits 30 may be sequentially arranged along the Y direction and may be sequentially labeled as G (1) -G (Q), and then the Q first gate driving circuits G (1) -G (Q) may respectively and correspondingly drive the Q fingerprint identification partitions 12 sequentially arranged along the Y direction. For example, Q is equal to 32, the display area 10 includes 32 fingerprint recognition partitions 12 sequentially arranged along the Y direction, and the corresponding non-display area 20 includes 32 first gate driving circuits 30, and one first gate driving circuit 30 correspondingly drives one fingerprint recognition partition 12.
The driving chip 40 includes M first signal output terminals STV and one second signal output terminal IC-VG. The non-display area 20 further includes a first decoding circuit 50, where the first decoding circuit 50 includes M first signal input terminals S, one second signal input terminal VG, and N third signal output terminals OUT, where 1.ltoreq.m < q.ltoreq.n, and M, Q and N are positive integers. Taking m=5 as an example, the 5 first signal output terminals STV of the driving chip 40 may be sequentially labeled as STV0, STV1, STV2, STV3, and STV4, and the 5 first signal input terminals S of the first decoding circuit 50 may be sequentially labeled as S0, S1, S2, S3, and S4; the first signal output terminals STV of the driving chip 40 are electrically connected to the first signal input terminals S of the first decoding circuit 50 in one-to-one correspondence, and then STV0 is electrically connected to S0, STV1 is electrically connected to S1, STV2 is electrically connected to S2, STV3 is electrically connected to S3, and STV4 is electrically connected to S4. The second signal output terminal IC-VG of the driving chip 40 is electrically connected to the second signal input terminal VG of the first decoding circuit 50.
The first decoding circuit 50 includes N third signal output terminals OUT, each of the first gate driving circuits 30 is correspondingly connected to one of the third signal output terminals OUT of the first decoding circuit 50, the N third signal output terminals OUT are sequentially labeled as OUT1, OUT2, …, OUTN, and Q third signal output terminals OUT of the N third signal output terminals OUT are correspondingly arranged with the Q first gate driving circuits 30. It should be noted that, if the driving chip 40 includes M first signal output terminals STV, at most, it can be used to implement fingerprint identification control on 2 M fingerprint identification partitions 12, that is, Q is less than or equal to n=2 M. For example, m=5, where the fingerprint control can be implemented on the 32 fingerprint recognition partitions 12 at most, n=32 may be designed, and Q OUT in N may be selected to be electrically connected to Q first gate driving circuits 30 correspondingly, for example, q=32, or q=20, etc., which is not limited thereto. Obviously, a first decoding circuit 50 is designed, which is applicable to the display panels with various fingerprint identification partitions; taking m= 5,N =32 as an example, the present invention is applicable to a display panel having 32 fingerprint recognition partitions, a display panel having 10 fingerprint recognition partitions, and the like, and is not limited thereto.
By arranging the first decoding circuit 50 between the driving chip 40 and the first gate driving circuit 30 in the non-display area 20, the driving chip 40 provides signals to the first decoding circuit 50 through a smaller number of signal output ends, and the first decoding circuit 50 provides signals to a larger number of first gate driving circuits 30 after decoding, so that the number of wirings in the non-display area 20 is effectively reduced, and the narrow frame of the display panel is facilitated.
In this embodiment, the display panel includes a fingerprint recognition stage and a non-fingerprint recognition stage other than the fingerprint recognition stage, and the non-fingerprint recognition stage includes a non-selection stage. In the non-selection stage, the first decoding circuit 50 resets each of the first gate driving circuits 30 according to the reset control signal supplied from the second signal output terminal IC-VG of the driving chip 40. Specifically, taking the reset control signal vgl as an example, the second signal input terminal VG of the first decoding circuit 50 receives the reset control signal vgl, the first decoding circuit 50 processes vgl to make the N third signal output terminals OUT of the first decoding circuit 50 output the reset signal, and then the first gate driving circuit 30 receives the reset signal and resets, at this time, all Q first gate driving circuits 30 are in the reset state.
The first gate driving circuit 30 being in the reset state means that the first gate driving circuit 30 is not operated, and then the fingerprint recognition unit 11 of the display area 10 is not operated, and the display panel does not perform the fingerprint recognition function. The related practitioner can reasonably design a reset control signal and a reset signal according to the requirements of products; for example, the reset control signal may be high, and the reset control signal may be low in other display panels; and, the reset signal may be high level, and the reset signal may be designed to be low level in other display panels. There is no particular limitation.
In this embodiment, taking the reset control signal vgl and the reset signal vgh as an example, the second signal output terminal IC-VG of the driving chip 40 provides the low level signal to the second signal input terminal VG of the first decoding circuit 50, and the first decoding circuit 50 controls the N third signal output terminals OUT to output the reset signal vgh according to the reset control signal vgl, so that all the first gate driving circuits 30 are in the reset state.
The optional display panel further comprises a selection stage; in the region selection stage, the first decoding circuit 50 is configured to control the selected third signal output terminal OUT to output a first enable signal according to the region selection signal provided by the first signal output terminal STV, so that the corresponding first gate driving circuit 30 is activated, and control the unselected third signal output terminal OUT to output a second enable signal, so that the corresponding first gate driving circuit 50 is turned off, and the region selection signal includes a first level signal and a second level signal lower than the first level signal.
The display panel further comprises a fingerprint identification stage, wherein the fingerprint identification stage comprises a region selection stage. In the region selection stage, the M first signal output terminals STV0-STV4 of the driving chip 40 provide region selection signals, the first decoding circuit 50 decodes the region selection signals received by the first signal input terminals S0-S4 to determine the first gate driving circuit 30 corresponding to the selected fingerprint identification region 12, and then the first decoding circuit 50 controls the selected third signal output terminals OUT to output the same first enable signals and controls the unselected third signal output terminals OUT to output the same second enable signals. The first gate driving circuit 30 switches from the reset state to the start state according to the first enable signal, causing the corresponding fingerprint recognition unit 11 to perform the fingerprint recognition operation; the first gate driving circuit 30 switches from the reset state to the off state according to the second enable signal, and deactivates the corresponding fingerprint recognition unit 11. Thereby enabling selection of the identification partition of the pointer in the display area. The first enable signal may be selected to be high and the second enable signal low.
It should be noted that the display panel includes a fingerprint recognition stage. In the fingerprint identification stage, one fingerprint identification partition 12 can be selected for fingerprint identification operation, and then the driving chip 40 outputs a corresponding area selection signal, the first decoding circuit 50 decodes and controls the selected third signal output terminal OUT to output a first enabling signal, and triggers the corresponding first gate driving circuit 30 to start working, so that the corresponding fingerprint identification partition 12 is selected to execute the fingerprint identification function.
In the fingerprint identification stage, a plurality of continuous fingerprint identification partitions 12 can be selected for fingerprint identification operation, and then the driving chip 40 outputs corresponding area selection signals, and the first decoding circuit 50 decodes and controls the selected plurality of third signal output terminals OUT to output the same first enabling signals, so as to trigger the corresponding first gate driving circuits 30 to start working, and enable the corresponding fingerprint identification partitions 12 to be selected for executing the fingerprint identification function.
In the fingerprint identification stage, a plurality of fingerprint identification partitions 12 arranged at intervals can be selected to perform fingerprint identification operation, and then the driving chip 40 outputs corresponding area selection signals, the first decoding circuit 50 decodes and controls the selected plurality of third signal output terminals OUT to output the same first enabling signals, and the corresponding first gate driving circuits 30 are triggered to start to work, so that the corresponding fingerprint identification partitions 12 are selected to perform fingerprint identification functions.
In the fingerprint identification stage, after the first decoding circuit 50 decodes, the unselected third signal output terminals OUT are controlled to output the same second enable signal, so that the corresponding first gate driving circuits 30 are turned off, and the corresponding fingerprint identification partitions 12 are unselected.
Optionally, the first enable signal is vgh and the second enable signal is vgl. The selectable region signal includes a first level signal and a second level signal lower than the first level signal, the selectable first level signal being vgh and the second level signal being vgl. The optional reset control signal is less than or equal to the second level signal.
According to the display panel provided by the embodiment of the invention, the first decoding circuit arranged between the driving chip and the first grid driving circuit is arranged in the non-display area, so that the driving chip can provide signals for the first decoding circuit through a small number of signal output ends, the first decoding circuit can provide signals for a large number of first grid driving circuits after decoding, the wiring quantity of the non-display area is effectively reduced, and the narrow frame of the display panel is facilitated. In addition, each first gate driving circuit is reset in the non-area selection stage, so that each first gate driving circuit is in the same reset state before area selection, and then the area can be correctly selected in the area selection stage, the error triggering of the unselected first gate driving circuits is avoided, and the area selection accuracy is improved.
Referring to fig. 2, a schematic diagram of another display panel according to an embodiment of the invention is shown. In this embodiment, the optional first decoding circuit 50 includes a non-selection block 51, a selection block 52, N decoding blocks 53, and 2M gate signal lines 54; the decoding module 53 includes M decoding inputs and a third signal output OUT; the non-selective area module 51 comprises an input end VG and 2M output ends, and the input end VG of the non-selective area module 51 is electrically connected with the second signal output end IC-VG; the area selection module 52 comprises M input ends S and 2M output ends, and the M input ends S of the area selection module 52 are electrically connected with the M first signal output ends STV in a one-to-one correspondence manner; the 2M output ends of the non-selective area module 51 are in one-to-one correspondence with the 2M output ends of the selective area module 52, and one output end of the non-selective area module 51 is electrically connected with one output end of the corresponding selective area module 52 through a gating signal line 54; the M decoding input ends of the decoding module 53 are electrically connected with M gate signal lines 54 in the 2M gate signal lines 54 in one-to-one correspondence; for any two decoding modules 53, there are differences between the M gate signal lines 54 electrically connected to one decoding module 53 and the M gate signal lines 54 electrically connected to the other decoding module 53.
The optional display panel further comprises a selection stage; in the non-selective stage, the non-selective module 51 is turned on, the selective module 52 is turned off, and the reset control signal provided by the second signal output end IC-VG is transmitted to the 2M gate signal lines 54; in the area selecting stage, the non-area selecting module 51 is turned off and the area selecting module 52 is turned on, and the driving chip 40 provides the area selecting signals to the 2M gate signal lines 54 through the M first signal output terminals STV.
In this embodiment, the first decoding circuit 50 includes a non-selection area module 51. The non-selection area module 51 includes an input terminal VG electrically connected to the second signal output terminal IC-VG of the driving chip 40. The non-selective area module 51 further includes 2M output terminals, each of which is electrically connected to a corresponding one of the gate signal lines 54. Then in the non-selection stage, the non-selection module 51 is turned on, the selection module 52 is turned off, and the non-selection module 51 transmits the reset control signal output from the second signal output terminal IC-VG of the driving chip 40 to the 2M gate signal lines 54.
The first decoding circuit 50 further comprises a selection module 52. The selection module 52 includes M input terminals S, taking m=5 as an example, and the M input terminals S are optionally labeled as S0-S4 in turn, where the M input terminals S of the selection module 52 are electrically connected to the M first signal output terminals STV in a one-to-one correspondence manner, and then the optional S0 corresponds to the electrical connection STV0, the S1 corresponds to the electrical connection STV1, the S2 corresponds to the electrical connection STV2, the S3 corresponds to the electrical connection STV3, and the S4 corresponds to the electrical connection STV4. The select block 52 further includes 2M outputs, each of which is electrically connected to a corresponding one of the strobe signal lines 54. Then, in the area selecting stage, the non-area selecting module 51 is turned off, the area selecting module 52 is turned on, and the area selecting module 52 generates an area selecting command according to the area selecting signal output by the first signal output end STV of the driving chip 40 and transmits the area selecting command to the 2M gate signal lines 54.
The first decoding circuit 50 further includes N decoding modules 53, where the decoding modules 53 include M decoding input terminals and a third signal output terminal OUT, and the M decoding input terminals of the decoding modules 53 are electrically connected to M gate signal lines 54 among the 2M gate signal lines 54 in a one-to-one correspondence. The N decoding modules 53 and the third signal output terminal OUT thereof are labeled as decoding module 1/OUT1, decoding modules 2/OUT2, …, and decoding module N/OUTN in order.
For any two decoding modules 53, there are differences between the M gate signal lines 54 electrically connected to one decoding module 53 and the M gate signal lines 54 electrically connected to the other decoding module 53. For the decoding module 53 and the M gate signal lines 54 electrically connected thereto, the driving chip 40 may trigger the corresponding decoding module 53 to decode the first enable signal or the second enable signal by providing different signals to the M gate signal lines 54, if the signals provided by the M gate signal lines 54 trigger the decoding module 53 to decode the first enable signal, the signal is defined as an effective area selection instruction, and if the signals provided by the M gate signal lines 54 trigger the decoding module 53 to decode the second enable signal, the signal is defined as an ineffective area selection instruction. Obviously, when the first gate driving circuit 30 corresponding to the decoding module 53 is selected, the driving chip 40 provides an effective area selecting instruction to the decoding module 53 through the M gate signal lines 54, so as to trigger the decoding module 53 to decode the first enabling signal. The M gate signal lines 54 electrically connected to any two decoding modules 53 are different, so that the valid selection instruction of each decoding module 53 can be unique.
In the non-selection period, the M decoding inputs of the decoding module 53 receive the reset control signal supplied from the gate signal line 54, generate a reset signal according to the reset control signal, and transmit the reset signal to the first gate driving circuit 30.
In the region selection stage, the M decoding input ends of the decoding module 53 receive the region selection instructions provided by the M gate signal lines 54, and if the region selection instructions are effective region selection instructions, the decoding module 53 generates a first enabling signal according to the effective region selection instructions, and transmits the first enabling signal to the first gate driving circuit 30; if the selection command is an invalid selection command, the decoding module 53 generates a second enable signal according to the invalid selection command, and transmits the second enable signal to the first gate driving circuit 30.
Referring to fig. 3, a schematic diagram of another display panel according to an embodiment of the invention is shown. In this embodiment, the display panel further includes a region selection stage; the selection module 52 includes M switch units 52a and a first control line CL1, where the switch units 52a include one input terminal and 2 output terminals; the input end of the switch unit 52a is correspondingly and electrically connected to the first signal output end STV, the control end of the switch unit 52a is electrically connected to the first control line CL1, and the 2 output ends of the switch unit 52a are correspondingly and electrically connected to the two gate signal lines 54; the first control line CL1 is used for controlling the M switch units 52a to be turned off simultaneously in the non-selection stage, and controlling the M switch units 52a to be turned on simultaneously in the selection stage.
In this embodiment, one input end of the switch unit 52a is correspondingly and electrically connected to one first signal output end STV, and then the input ends of the M switch units 52a are correspondingly and electrically connected to the M first signal output ends STV, respectively. The 2 output terminals of the switching units 52a are electrically connected to the two gate signal lines 54, respectively, and the output terminals of the M switching units 52a are electrically connected to the 2M gate signal lines 54, respectively. The control terminal of each of the switching units 52a is commonly electrically connected to the first control line CL1.
In the non-selection stage, the selection module 52 is turned off, and the first control line CL1 controls the M switching units 52a to be turned off simultaneously. In the area selecting stage, when the area selecting module 52 is turned on, the first control line CL1 controls the M switch units 52a to be turned on simultaneously, and the area selecting signals provided by the M first signal output ends of the driving chip 40 generate the area selecting instructions for the N decoding modules 53 through the M switch units 52 a.
The optional switching unit 52a includes a first switching device k11, a second switching device k12, and an inverter k13; the input end of the first switching device k11 is electrically connected with the first signal output end STV, and the input end of the second switching device k12 is electrically connected with the same first signal output end STV through an inverter k13; the output terminal of the first switching device k11 is electrically connected to the gate signal line 54, and the output terminal of the second switching device k12 is electrically connected to the other gate signal line 54.
As described above, one switching unit 52a corresponds to one first signal output terminal STV and two gate signal lines 54. For the switching unit 52a, the control terminal of the first switching device k11 and the control terminal of the second switching device k12 are both electrically connected to the first control line CL1.
In the non-selection phase, the selection module 52 is turned off, and the first control line CL1 controls the first switching device k11 and the second switching device k12 to be turned off at the same time. In the region selecting stage, when the region selecting module 52 is turned on, the first control line CL1 controls the first switching device k11 and the second switching device k12 to be turned on simultaneously, and the signal output by the first switching device k11 is equal to the signal of the first signal output terminal STV, and the signal output by the second switching device k12 is opposite to the signal of the first signal output terminal STV.
The first switching device k11 and the second switching device k12 are selected to be P-type transistors; or the first switching device k11 and the second switching device k12 are both N-type transistors. As shown in fig. 3, the first switching device k11 and the second switching device k12 are both N-type transistors, and the first control line CL1 outputs a high-level signal to turn on the first switching device k11 and the second switching device k12, and the first control line CL1 outputs a low-level signal to turn off the first switching device k11 and the second switching device k 12.
As shown in fig. 3, the optional display panel further includes a field selection stage; the non-selective area module 51 comprises 2M third switching devices k2 and a second control line CL2, wherein the input end of each third switching device k2 is electrically connected with the second signal output end IC-VG, the output end of each third switching device k2 is correspondingly electrically connected with the corresponding gating signal line 54, and the control end of each third switching device k2 is electrically connected with the second control line CL2; the second control line CL2 is used for controlling the 2M third switching devices k2 to be turned on simultaneously in the non-selection stage, and controlling the 2M third switching devices k2 to be turned off simultaneously in the selection stage.
In this embodiment, the control ends of the 2M third switching devices k2 are simultaneously connected to the second control line CL2, the input ends of the 2M third switching devices k2 are all electrically connected to the second signal output end IC-VG, and the output ends of the 2M third switching devices k2 are respectively and correspondingly electrically connected to the 2M gate signal lines 54.
In the non-selection phase, the non-selection module 51 is turned on, and then the second control line CL2 controls the 2M third switching devices k2 to be turned on simultaneously, and the signal output by the third switching device k2 is equal to the reset control signal provided by the second signal output terminal IC-VG of the driving chip 40. In the region selection phase, the non-region selection module 51 is turned off, and the second control line CL2 controls the 2M third switching devices k2 to be turned off at the same time.
As described above, the third switching device k2 is disposed in the non-area selection module 51, and the first switching device k11 and the second switching device k12 are disposed in the area selection module 52, so that the first switching device k11, the second switching device k12 and the third switching device k2 are additionally disposed between the first signal input terminal S and the second signal input terminal VG in the first decoding circuit 50, which can prevent the area selection signal of the first signal input terminal S from being transmitted to the second signal input terminal VG or the reset control signal of the second signal input terminal VG from being transmitted to the first signal input terminal S, so as to avoid crosstalk between the two signals.
The optional third switching devices k2 are P-type transistors or N-type transistors. As shown in fig. 3, the optional third switching devices k2 are all N-type transistors, and the second control line CL2 outputs a high-level signal to turn on the third switching devices k2, and the second control line CL2 outputs a low-level signal to turn off the third switching devices k 2.
Referring to fig. 4, a schematic diagram of a decoding module in the first decoding circuit is shown. In this embodiment, the optional decoding module 53 includes M first decoding units 53a, one second decoding unit 53b, and one reset unit 53c; the control end of the first decoding unit 53a is electrically connected to the gate signal line, the input end of the first decoding unit 53a is electrically connected to the first voltage signal line VGL, and the output end of the first decoding unit 53a is electrically connected to the third signal output end OUT; the control end and the output end of the second decoding unit 53b are electrically connected with the third signal output end OUT, and the input end of the second decoding unit 53b is electrically connected with the second voltage signal line VGH; the control terminal of the RESET unit 53c is electrically connected to the RESET control line RESET, the input terminal of the RESET unit 53c is electrically connected to the second voltage signal line VGH, and the output terminal of the RESET unit 53c is electrically connected to the third signal output terminal OUT.
Referring to fig. 5, a circuit diagram of a selected decoding module is shown, and referring to fig. 6, a circuit diagram of an unselected decoding module is shown. The optional display panel further comprises a selection stage; in the selecting stage, as shown in fig. 5, for the selected decoding module 53, the first decoding unit 53a is turned off, and the second decoding unit 53b is turned on, so that the voltage signal of the second voltage signal line VGH is transmitted to the third signal output terminal OUT; as shown in fig. 6, for the unselected decoding module 53, at least one first decoding unit 53a is turned on, and the second decoding unit 53b and the reset unit 53c are turned off, so that the voltage signal of the first voltage signal line VGL is transmitted to the third signal output terminal OUT.
In this embodiment, the control ends of the M first decoding units 53a in the decoding module 53 are electrically connected to M different gate signal lines, and the M gate signal lines electrically connected to the different decoding modules 53 are different. Taking m=5 as an example, the first decoding circuit 50 includes 10 gate signal lines, and 5 gate signal lines are selected to drive one decoding module 53, and then 10 gate signal lines can be used to drive 32 decoding modules 53. If at least one first decoding unit 53a among the M first decoding units 53a is turned on, the voltage signal provided by the first voltage signal line VGL is transmitted to the third signal output terminal OUT through the turned-on first decoding unit 53 a. If all of the M first decoding units 53a are turned off, the third signal output terminal OUT is determined by the second decoding unit 53b and the reset unit 53 c.
The voltage signal supplied from the first voltage signal line VGL and the voltage signal supplied from the second voltage signal line VGH may be selected as signals having different levels. For example, as shown in fig. 4, the voltage signal provided by the first voltage signal line VGL is a low level signal VGL, and the voltage signal provided by the second voltage signal line VGH is a high level signal VGH; in other embodiments, the voltage signal provided by the first voltage signal line may be a high level signal, and the voltage signal provided by the second voltage signal line may be a low level signal.
As shown in fig. 5, if the decoding module 53 is selected, all of the M first decoding units 53a are turned off, and the second decoding units 53b are turned on, and then the voltage signal provided by the second voltage signal line VGH is transmitted as a first enabling signal to the third signal output terminal OUT, so that the corresponding first gate driving circuit is started to drive the fingerprint identification partition to perform the fingerprint identification operation.
As shown in fig. 6, if the decoding module 53 is not selected, at least one first decoding unit 53a is turned on, and the second decoding unit 53b and the reset unit 53c are turned off, the voltage signal provided by the first voltage signal line VGL is transmitted as a second enable signal to the third signal output terminal OUT, so that the corresponding first gate driving circuit is turned off.
As described above, the voltage signal supplied from the first voltage signal line VGL is controlled to be transmitted by the first decoding unit 53a, the voltage signal supplied from the second voltage signal line VGH is controlled to be transmitted by the second decoding unit 53b, and the first decoding unit 53a and the second decoding unit 53b are turned on in a time-sharing manner. The voltage signal provided by the first voltage signal line VGL and the voltage signal provided by the second voltage signal line VGH do not directly pass through, so that signals with different heights are output in a time-sharing manner by OUT. The inter-signal crosstalk is reduced, the problem of large current output caused by the penetration of the first voltage signal line VGL and the second voltage signal line VGH is avoided, and the power consumption is reduced.
Optionally, in the non-selection stage, for each decoding module 53, the first decoding unit 53a is turned off and the reset unit 53c is turned on, so that the voltage signal of the second voltage signal line VGH is transmitted to the third signal output terminal OUT. In the non-selection stage, the voltage signal of the second voltage signal line VGH is transmitted to the third signal output terminal OUT, and all the first gate driving circuits maintain the high level signal in the reset state.
As shown in fig. 4, the optional first decoding unit 53a includes a switching device, the second decoding unit 53b includes a switching device, and the reset unit 53c includes a switching device. The switching devices in the optional first decoding unit 53a, second decoding unit 53b, and reset unit 53c are P-type transistors or N-type transistors. The types of the switching devices in the first decoding circuit 50 are the same, so that the manufacturing difficulty of the process can be reduced.
In order to more clearly describe the working principle of the display panel provided by the embodiment of the invention. A specific example is provided below for illustration. Fig. 7 is a schematic diagram of another display panel according to an embodiment of the invention.
As shown in fig. 7, the signal provided by the first signal output terminal IC-VGL is a low level signal VGL, each switching device in the first decoding circuit 50 is an N-type transistor, the voltage signal provided by the first voltage signal line VGL is a low level signal, and the voltage signal provided by the second voltage signal line VGH is a high level signal.
If the high level signal output by the STV corresponds to the number 1, the low level signal output by the STV corresponds to the number 0, then the 5 first signal output terminals STV0-STV4 of the driving chip 40 can generate 32 kinds of selection signals, wherein each selection signal can be used as an effective selection signal of a fingerprint identification partition and stored in the driving chip 40. Wherein the 5-bit select signal is composed of STV4, STV3, STV2, STV1 and STV0 in this order.
For example, if the selected area signal corresponding to the selected fingerprint identification area is 00001, the driving chip 40 simultaneously provides the low level signal for the STV4, the low level signal for the STV3, the low level signal for the STV2, the low level signal for the STV1, the high level signal for the STV0, and after decoding by the first decoding circuit 50, the first enable signal is provided for the selected first gate driving circuit to be started, and the second enable signal is provided for the unselected first gate driving circuit to be closed.
If the sections selection stage determines that the plurality of fingerprint identification sections perform the fingerprint identification operation at the same time, the driving chip 40 sequentially outputs a plurality of section selection signals so that the plurality of fingerprint identification sections are sequentially selected to perform the fingerprint identification operation.
Taking m=5 and q=32 as an example, the selection signals corresponding to the 32 different fingerprint identification partitions are stored in the driving chip 40, and are defined as follows:
the selection signal of the partition 01 is 00001, the selection signal of the partition 17 is 10001,
The selection signal of partition 02 is 00010, the selection signal of partition 18 is 10010,
The selection signal of the partition 03 is 00011, the selection signal of the partition 19 is 10011,
The select signal for partition 04 is 00100, the select signal for partition 20 is 10100,
The selection signal of the partition 05 is 00101, the selection signal of the partition 21 is 10101,
The selection signal of the partition 06 is 00110, the selection signal of the partition 22 is 10110,
The selection signal of partition 07 is 00111, the selection signal of partition 23 is 10111,
The select signal for partition 08 is 01000, the select signal for partition 24 is 11000,
The selection signal for partition 09 is 01001, the selection signal for partition 25 is 11001,
The selection signal of the partition 10 is 01010, the selection signal of the partition 26 is 11010,
The selection signal of partition 11 is 01011, the selection signal of partition 27 is 11011,
The select signal for partition 12 is 01100, the select signal for partition 28 is 11100,
The select signal for partition 13 is 01101, the select signal for partition 29 is 11101,
The select signal for partition 14 is 01110, the select signal for partition 30 is 11110,
The select signal for partition 15 is 01111, the select signal for partition 31 is 11111,
The select signal of partition 16 is 10000 and the select signal of partition 32 is 00000.
Fig. 8 is a timing chart of the display panel shown in fig. 7. In the selection stage T2, the partition 1 is selected to perform a fingerprint identification operation.
In the non-selection phase T1, the non-selection module 51 is on and the selection module 52 is off. Specifically, the driving chip 40 supplies the low level signal (L) to the first control line CL1 and supplies the high level signal (H) to the second control line CL2, and all the first switching devices k11 and the second switching devices k12 are turned off and all the third switching devices k2 are turned on. The second signal output terminal IC-VG of the driving chip 40 outputs a low level signal, which is transmitted to each of the gate signal lines 54 through each of the third switching devices k 2. The control terminal of the first decoding unit 53a of each decoding module 53 is electrically connected to one gate signal line 54, and the first decoding units 53a of the respective decoding modules 53 are all turned off. The driving chip 40 supplies the RESET control line RESET and the second voltage signal line VGH with high level signals, and the second decoding unit 53b and the RESET unit 53c are turned on, and the third signal output terminal OUT of each decoding module 53 outputs the same high level signals, so that the Q first gate driving circuits are all in a RESET state.
In the selection phase T2, the non-selection module 51 is turned off and the selection module 52 is turned on. Specifically, the driving chip 40 supplies a high level signal to the first control line CL1 and supplies a low level signal to the second control line CL2, and all the first switching devices k11 and the second switching devices k12 are turned on and all the third switching devices k2 are turned off. Taking the stage t21 selected by the partition 1 as an example, the 5 first signal output ends STV4-STV0 of the driving chip 40 output 5-bit area selection signals 00001, and the area selection signals are processed by the area selection module 52 to generate 10-bit area selection instructions and respectively transmitted to the 10 gate signal lines 54. The 10 strobe signal lines 54 provide 10-bit select instructions. The signals received by the control ends of the 5 first decoding units 53a of the decoding module 53 corresponding to the partition 1 are 00000, and all the 5 first decoding units 53a are turned off; the driving chip 40 supplies a low level signal to the RESET control line RESET, and the RESET unit 53c is turned off, and the output terminal of the second decoding unit 53b is in a floating VGH state, and OUT1 keeps outputting a high level signal. The first gate driving circuit corresponding to the electrical connection of the OUT1 is activated, and then the fingerprint identification partition 1 corresponding to the electrical connection of the first gate driving circuit performs the fingerprint identification operation.
In the region selection stage T2, when the 5 first signal output terminals STV4-STV0 of the driving chip 40 output the region selection signal 00001, the signal received by the control end of at least one first decoding unit 53a of the decoding modules 53,5 corresponding to the other non-selected regions is a high level signal, and the signal is kept at the high level OUT in the non-region selection stage, the turned-on first decoding unit 53a is pulled down to the voltage signal VGL provided by the first voltage signal line VGL, so as to cause the second decoding unit 53b to be turned off.
In this way, in the selecting stage, the output terminal of the decoding module 53 corresponding to the selected partition 1 is clamped at a high potential; while the outputs of the decoding modules 53 corresponding to the other partitions not selected are pulled down to a low level.
In this embodiment, in the non-selection stage, the first decoding unit of the decoding module is turned off, and the output terminal OUT is at a high level.
In the region selection stage, the first decoding unit of the selected decoding module is kept off, the output end of the decoding module is in a floating VGH state, and OUT is output to be high level. At least one first decoding unit of the decoding module which is not selected is switched to be in a conducting state, the output end of the decoding module is pulled down to VGL, the second decoding unit is driven to be turned off, and OUT is output to be in a low level. Therefore, the first decoding unit connected with the VGL in the decoding module is conducted to enable the second decoding unit connected with the VGH to be automatically closed, the problem of penetration between the VGH and the VGL in the decoding module is avoided, the problem of high current caused by penetration of the VGH and the VGL is solved, and power consumption is reduced.
Based on the same inventive concept, an embodiment of the present invention further provides a display device including the display panel according to any of the above embodiments; the display panel includes a fingerprint recognition stage including a non-selection stage. In this embodiment, a non-selection stage is set before a selection stage, and each first gate driving circuit is in a reset state during the non-selection stage. And the subsequent correct area selection is facilitated.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, and that various obvious changes, rearrangements, combinations, and substitutions can be made by those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.
Claims (16)
1. A display panel, comprising: a display region and a non-display region surrounding the display region;
The display area comprises a plurality of fingerprint identification units which are arranged in an array along a first direction and a second direction, wherein the first direction and the second direction are intersected;
The non-display area comprises Q first grid driving circuits and driving chips;
The first grid driving circuit is electrically connected with at least two rows of fingerprint identification units extending along the first direction;
the driving chip comprises M first signal output ends and M second signal output ends;
The non-display area further comprises a first decoding circuit, wherein the first decoding circuit comprises M first signal input ends, second signal input ends and N third signal output ends, M is more than or equal to 1 and less than or equal to Q and less than or equal to N, and M, Q and N are both positive integers;
the first signal output ends are electrically connected with the first signal input ends in a one-to-one correspondence manner, and the second signal output ends are electrically connected with the second signal input ends;
each first gate driving circuit is correspondingly connected to one third signal output end of the first decoding circuit;
The display panel comprises a fingerprint identification stage and a non-fingerprint identification stage outside the fingerprint identification stage, wherein the non-fingerprint identification stage comprises a non-area selection stage;
In the non-selection stage, the first decoding circuit is configured to reset each of the first gate driving circuits according to a reset control signal provided by the second signal output end, so that the fingerprint identification unit of the display area does not work, and the display panel does not perform fingerprint identification.
2. The display panel of claim 1, further comprising a selection stage;
In the region selection stage, the first decoding circuit is configured to control the selected third signal output terminal to output a first enable signal according to a region selection signal provided by the first signal output terminal, so that the corresponding first gate driving circuit is started, and control the unselected third signal output terminal to output a second enable signal, so that the corresponding first gate driving circuit is turned off, where the region selection signal includes a first level signal and a second level signal lower than the first level signal.
3. The display panel according to claim 2, wherein the reset control signal is less than or equal to the second level signal.
4. The display panel of claim 1, wherein the first decoding circuit comprises a non-selection block, a selection block, N decoding blocks, and 2M gate signal lines;
The decoding module comprises M decoding input ends and one third signal output end;
the non-selective area module comprises an input end and 2M output ends, and the input end of the non-selective area module is electrically connected with the second signal output end;
The area selection module comprises M input ends and 2M output ends, and the M input ends of the area selection module are electrically connected with the M first signal output ends in a one-to-one correspondence manner;
The 2M output ends of the non-selective area module are in one-to-one correspondence with the 2M output ends of the selective area module, and one output end of the non-selective area module is electrically connected with one output end of the corresponding selective area module through one gating signal line;
The M decoding input ends of the decoding module are electrically connected with M gating signal lines in the 2M gating signal lines in a one-to-one correspondence manner;
For any two decoding modules, the M gating signal lines corresponding to one decoding module are electrically connected and the M gating signal lines corresponding to the other decoding module are different.
5. The display panel of claim 4, further comprising a selection stage;
In the non-area selecting stage, the non-area selecting module is turned on, the area selecting module is turned off, and a reset control signal provided by the second signal output end is transmitted to the 2M gating signal lines;
In the region selecting stage, the non-region selecting module is turned off, the region selecting module is turned on, and the driving chip provides region selecting signals to the 2M gating signal lines through the M first signal output ends.
6. The display panel of claim 4, further comprising a selection stage;
the area selection module comprises M switch units and a first control line, wherein each switch unit comprises an input end and 2 output ends;
The input end of the switch unit is correspondingly and electrically connected with the first signal output end, the control end of the switch unit is electrically connected with the first control line, and the 2 output ends of the switch unit are correspondingly and electrically connected with the two gating signal lines;
the first control line is used for controlling the M switch units to be turned off simultaneously in the non-selective area stage, and controlling the M switch units to be turned on simultaneously in the selective area stage.
7. The display panel of claim 6, wherein the switching unit includes a first switching device, a second switching device, and an inverter;
the input end of the first switching device is electrically connected with the first signal output end, and the input end of the second switching device is electrically connected with the same first signal output end through the inverter;
The output end of the first switching device is electrically connected with the gating signal line, and the output end of the second switching device is electrically connected with the other gating signal line.
8. The display panel of claim 7, wherein the first switching device and the second switching device are each P-type transistors; or alternatively
The first switching device and the second switching device are both N-type transistors.
9. The display panel of claim 4, further comprising a selection stage;
The non-selective area module comprises 2M third switching devices and second control lines, wherein the input ends of the third switching devices are electrically connected with the second signal output ends, the output ends of the third switching devices are correspondingly and electrically connected with the gating signal lines, and the control ends of the third switching devices are electrically connected with the second control lines;
the second control line is used for controlling the 2M third switching devices to be simultaneously turned on in the non-area selection stage, and controlling the 2M third switching devices to be simultaneously turned off in the area selection stage.
10. The display panel of claim 9, wherein the third switching devices are P-type transistors or N-type transistors.
11. The display panel of claim 4, wherein the decoding module comprises M first decoding units, one second decoding unit, and one reset unit;
The control end of the first decoding unit is electrically connected with the gating signal line, the input end of the first decoding unit is electrically connected with a first voltage signal line, and the output end of the first decoding unit is electrically connected with the third signal output end;
The control end and the output end of the second decoding unit are electrically connected with the third signal output end, and the input end of the second decoding unit is electrically connected with a second voltage signal line;
The control end of the reset unit is electrically connected with a reset control line, the input end of the reset unit is electrically connected with the second voltage signal line, and the output end of the reset unit is electrically connected with the third signal output end.
12. The display panel of claim 11, further comprising a selection stage; in the stage of the selection of the area,
For the selected decoding module, the first decoding unit is turned off, and the second decoding unit is turned on, so that the voltage signal of the second voltage signal line is transmitted to the third signal output end;
for the decoding modules which are not selected, at least one first decoding unit is turned on, and the second decoding unit and the reset unit are turned off, so that the voltage signal of the first voltage signal line is transmitted to the third signal output end.
13. The display panel of claim 11, wherein, during the non-selection phase,
For each decoding module, the first decoding unit is turned off, and the reset unit is turned on, so that the voltage signal of the second voltage signal line is transmitted to the third signal output terminal.
14. The display panel of claim 11, wherein the first decoding unit includes a switching device, the second decoding unit includes a switching device, and the reset unit includes a switching device.
15. The display panel of claim 14, wherein the switching devices in the first decoding unit, the second decoding unit, and the reset unit are P-type transistors or N-type transistors.
16. A display device comprising the display panel of any one of claims 1-15;
the display panel includes a non-fingerprint identification stage including a non-selection stage.
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