CN114548006A

CN114548006A - Verification method and device for integrated circuit, electronic equipment and storage medium

Info

Publication number: CN114548006A
Application number: CN202210171611.7A
Authority: CN
Inventors: 魏洁; 刘勋
Original assignee: Haiguang Information Technology Co Ltd
Current assignee: Haiguang Information Technology Co Ltd
Priority date: 2022-02-24
Filing date: 2022-02-24
Publication date: 2022-05-27

Abstract

An integrated circuit verification method, an integrated circuit verification device, electronic equipment and a storage medium. The verification method of the integrated circuit comprises the following steps: acquiring a plurality of asynchronous sequential device pairs; according to the asynchronous sequential device pairs, performing model construction processing on the integrated circuit to obtain a circuit to be simulated; performing front-end simulation verification on a circuit to be simulated; wherein the model construction process comprises: for each asynchronous sequential device pair: determining a response time based on a circuit characteristic between the first timing device and the second timing device; constructing a response model according to the response time; the response model is added to a data link in the integrated circuit that is determined based on the first timing device and the second timing device. The method can accurately inject metastable state signals into each asynchronous sequential device pair in the asynchronous interface, realize accurate and quick logic simulation with small change, advance the verification of the asynchronous interface to the front-end simulation stage for execution, greatly reduce the difficulty of positioning potential problems and shorten the verification time.

Description

Verification method and device for integrated circuit, electronic equipment and storage medium

Technical Field

Embodiments of the present disclosure relate to a verification method of an integrated circuit, a verification apparatus of an integrated circuit, an electronic device, and a non-transitory computer-readable storage medium.

Background

For integrated circuits, especially large scale integrated circuits, verification of their function is required after the design is completed. Due to system limitations of large scale integrated circuits, it is often necessary to exchange data between multiple different Clock frequency systems, receive and transmit data or process asynchronous signals between different Clock frequency systems through input and output interfaces, etc., i.e., there may be multiple Clock domains (Clock domains) in an integrated circuit, each Clock Domain being a region of the integrated circuit controlled by the same Clock signal.

The clock signals corresponding to different clock domains are called asynchronous clocks. For two modules connected in an integrated circuit, for example, each module may be composed of some circuit logic that performs a specific function, and if the two modules are driven by different clocks (i.e., Asynchronous clocks), respectively, the clock signals of the two modules are called Asynchronous clock signals (Asynchronous interfaces); if two modules are driven by the same clock, the clock signals of the two modules are referred to as Synchronous clock signals (Synchronous interfaces).

Disclosure of Invention

At least one embodiment of the present disclosure provides a verification method for an integrated circuit, wherein the integrated circuit includes a plurality of asynchronous clock domains, the verification method comprising: acquiring a plurality of asynchronous sequential device pairs, wherein each asynchronous sequential device pair comprises a first sequential device and a second sequential device, the first sequential device and the second sequential device are positioned in two different clock domains of the plurality of clock domains, and an electrical signal transmission relationship exists between a data output end of the first sequential device and a data input end of the second sequential device; according to the asynchronous sequential device pairs, performing model construction processing on the integrated circuit to obtain a circuit to be simulated; performing front-end simulation verification on the circuit to be simulated; wherein the model building process comprises: for each asynchronous sequential device pair: determining a response time based on a circuit characteristic between the first timing device and the second timing device; constructing a response model according to the response time, wherein the response model comprises an input end and an output end, the response model is configured to output a metastable state signal in the response time from a first time, and output a steady state response signal after the response time from the first time, and the first time is the time when the input signal received by the input end jumps; adding the response model to a data link in the integrated circuit determined based on the first timing device and the second timing device.

For example, in at least one embodiment of the present disclosure, a method for verifying an integrated circuit, wherein determining a response time according to a circuit characteristic between the first time-series device and the second time-series device includes: determining a delay time according to the circuit characteristics; and determining the response time according to the delay time.

For example, in at least one embodiment of the present disclosure, a method for verifying an integrated circuit, determining a delay time according to a characteristic of the integrated circuit, includes: determining a constraint time according to the circuit characteristic, wherein the constraint time represents that the second sequential device acquires a steady-state response signal at a second moment at least after the first moment, and the first moment and the second moment are different by the constraint time; and determining the delay time according to the constraint time.

For example, in at least one embodiment of the present disclosure, a verification method for an integrated circuit is provided, where a clock domain in which the second sequential device is located is determined based on a target clock signal, and a constraint time is determined according to a characteristic of the circuit, including: and determining the constraint time to be x clock cycles according to the circuit characteristics, wherein the clock cycles are clock cycles of the target clock signal, and x is a positive integer.

For example, in at least one embodiment of the present disclosure, a method for verifying an integrated circuit, wherein determining the delay time according to the constraint time includes: determining a decision edge, wherein the decision edge is a first transition edge in the target clock signal that occurs after the first time; counting y judgment edges by taking the judgment edges as first judgment edges, wherein y is a positive number and is less than or equal to x; and taking the time length between the first moment and the y-th judgment edge as the delay time.

For example, in at least one embodiment of the present disclosure, a verification method for an integrated circuit is provided, where y is a random value between 0 and x.

For example, in at least one embodiment of the present disclosure, a method for verifying an integrated circuit is provided, in which determining a constraint time according to a characteristic of the circuit includes: and determining the maximum time delay between the first time sequence device and the second time sequence device according to the circuit characteristics, and taking the maximum time delay as the constraint time.

For example, in at least one embodiment of the present disclosure, a method for verifying an integrated circuit, wherein determining the delay time according to the constraint time includes: determining that the delay time is equal to the constraint time.

For example, in at least one embodiment of the present disclosure, a verification method for an integrated circuit is provided, where determining the response time according to the delay time includes: determining that the response time is less than or equal to the delay time.

For example, in at least one embodiment of the present disclosure, a verification method for an integrated circuit is provided, where the second time-series device performs synchronization processing on a signal sent by the first time-series device, the response model further includes a synchronization processing module, the synchronization processing module includes a plurality of time-series devices, the synchronization processing module is configured to perform synchronization processing on a signal sent by the first time-series device, and determining a delay time according to the circuit characteristic includes: determining constraint time according to the circuit characteristics, wherein the constraint time represents that a third sequential device acquires a steady-state response signal at a second moment at least after the first moment, the first moment and the second moment are different by the constraint time, and the third sequential device represents a sequential device which is directly connected with a data signal input end of the synchronous processing module in the plurality of sequential devices; and determining the delay time according to the constraint time.

For example, in at least one embodiment of the present disclosure, a verification method for an integrated circuit is provided, where determining the response time according to the delay time includes: determining the processing delay corresponding to the synchronous processing module; and determining the response time according to the processing delay and the delay time.

For example, in at least one embodiment of the present disclosure, a method for verifying an integrated circuit, wherein determining the response time according to the processing delay and the delay time includes: determining that the response time is less than or equal to the sum of the processing delay and the delay time.

For example, in at least one embodiment of the present disclosure, a verification method for an integrated circuit is provided, where in response to a signal received by the third sequential device being a metastable signal, determining the response time according to the processing delay and the delay time includes: determining that the response time is less than or equal to a sum of the processing delay, the metastable delay, and the delay time.

For example, in at least one embodiment of the present disclosure, a verification method of an integrated circuit is provided, in which the model building process further includes: naming the simulation model according to the constraint time so that the naming of the simulation model corresponds to the constraint time.

For example, in at least one embodiment of the present disclosure, a method for verifying an integrated circuit is provided, in which adding the response model to a data link determined based on the first timing device and the second timing device in the integrated circuit includes: and inserting the response model between the second sequential device and a device directly connected with the second sequential device, wherein the output end of the response model is directly connected with the data input end of the second sequential device.

For example, at least one embodiment of the present disclosure provides a verification method of an integrated circuit, further including: obtaining a circuit to be planned which passes the simulation verification, wherein the circuit to be planned comprises the plurality of asynchronous sequential device pairs; executing planning processing on the circuit to be planned; wherein the planning process comprises: replacing at least one response model respectively corresponding to at least one asynchronous sequential device pair in the plurality of asynchronous sequential device pairs with a corresponding physical device, wherein the name of the physical device is the same as the name of the corresponding response model; and acquiring a plurality of constraint times according to the naming of the physical device.

For example, in at least one embodiment of the present disclosure, a verification method for an integrated circuit is provided, where the planning process further includes: and performing layout and wiring optimization on the circuit to be planned according to the plurality of constraint times.

For example, in at least one embodiment of the present disclosure, a verification method for an integrated circuit is provided, where the planning process further includes: setting a virtual clock domain; and setting timing constraints for a plurality of asynchronous sequential device pairs in the circuit to be planned according to the plurality of constraint times.

For example, in at least one embodiment of the present disclosure, a verification method for an integrated circuit is provided, where the planning process further includes: setting a virtual clock domain, comprising: determining at least one virtual clock from the plurality of asynchronous sequential device pairs and the plurality of clock domains; and aiming at each virtual clock, setting at least one timing path determined based on the plurality of asynchronous timing device pairs to belong to the same virtual clock domain, wherein the same virtual clock domain is determined based on each virtual clock.

For example, in at least one embodiment of the present disclosure, a verification method for an integrated circuit is provided, where the planning process further includes: and performing timing check on the plurality of asynchronous sequential device pairs according to the timing constraints set by the plurality of asynchronous sequential device pairs.

For example, in at least one embodiment of the present disclosure, a verification method for an integrated circuit is provided, where the metastable signal includes a random signal and an indeterminate signal, and the response model performs the following operations when outputting the metastable signal within the response time from a first time: acquiring a signal configuration parameter; outputting one of the random signal or the indeterminate state signal within a response time from the first time in accordance with the signal configuration parameter.

At least one embodiment of the present disclosure provides an apparatus for verifying an integrated circuit, wherein the integrated circuit includes a plurality of asynchronous clock domains, the apparatus comprising: the device comprises an acquisition unit, a first clock domain and a second clock domain, wherein the acquisition unit is configured to acquire a plurality of asynchronous sequential device pairs, each asynchronous sequential device pair comprises a first sequential device and a second sequential device, the first sequential device and the second sequential device are positioned in two different clock domains of the plurality of clock domains, and an electric signal transmission relationship exists between a data output end of the first sequential device and a data input end of the second sequential device; the processing unit is configured to execute model construction processing on the integrated circuit according to the plurality of asynchronous sequential device pairs so as to obtain a circuit to be simulated; the simulation verification unit is configured to perform front-end simulation verification on the circuit to be simulated; wherein the model building process comprises: for each asynchronous sequential device pair: determining a response time based on a circuit characteristic between the first timing device and the second timing device; constructing a response model according to the response time, wherein the response model comprises an input end and an output end, the response model is configured to output a metastable state signal in the response time from a first time, and output a steady state response signal after the response time from the first time, and the first time is the time when the input signal received by the input end jumps; adding the response model to a data link in the integrated circuit determined based on the first timing device and the second timing device.

At least one embodiment of the present disclosure provides an electronic device, including: a memory non-transiently storing computer executable instructions; a processor configured to execute the computer-executable instructions, wherein the computer-executable instructions, when executed by the processor, implement a method of verifying an integrated circuit according to any of the embodiments of the present disclosure.

At least one embodiment of the present disclosure provides a non-transitory computer-readable storage medium having stored thereon computer-executable instructions that, when executed by a processor, implement a method of integrated circuit verification according to any one of the embodiments of the present disclosure.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure and are not limiting to the present disclosure.

FIG. 1 is a schematic diagram of an asynchronous interface;

fig. 2 is a schematic flow chart of a verification method for an integrated circuit according to at least one embodiment of the disclosure;

FIG. 3 is a schematic flow chart diagram of a model building process provided by at least one embodiment of the present disclosure;

fig. 4 is a schematic diagram of a delay time according to at least one embodiment of the present disclosure;

FIG. 5A is a schematic diagram of a response model provided by an embodiment of the present disclosure;

FIG. 5B is a schematic diagram of an output signal of a response model according to an embodiment of the disclosure;

FIG. 5C is a schematic diagram of an output signal of a response model provided by another embodiment of the present disclosure;

FIG. 6A is a schematic diagram of a response model provided by another embodiment of the present disclosure;

FIG. 6B is a schematic diagram of an output signal of a response model provided by another embodiment of the present disclosure;

fig. 7A is a schematic block diagram of an apparatus for verifying an integrated circuit according to at least one embodiment of the disclosure;

fig. 7B is a schematic block diagram of a processing unit provided in at least one embodiment of the present disclosure;

fig. 7C is a schematic block diagram of a planning processing unit according to at least one embodiment of the disclosure;

fig. 8 is a schematic block diagram of an electronic device provided in at least one embodiment of the present disclosure;

fig. 9 is a schematic diagram of a non-transitory computer-readable storage medium according to at least one embodiment of the disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be described below clearly and completely with reference to the accompanying drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

To maintain the following description of the embodiments of the present disclosure clear and concise, a detailed description of some known functions and components have been omitted from the present disclosure.

With the development of semiconductor technology, the process of integrated circuits is more advanced, the scale is larger, the verification period is longer, and the verification difficulty is higher. Verification is becoming an increasingly important consideration for project progress for LSI projects and products that employ advanced processes.

In large scale integrated circuits there are often multiple clock domains. The signals of different clock domains are correlated to form a large number of data links crossing the clock domains. These data links are called asynchronous interfaces because the sender and receiver belong to different clock domains, respectively.

FIG. 1 is a schematic diagram of an asynchronous interface. As shown in fig. 1, timing devices a1 through An are timing devices driven by a first clock signal Clk _1, where point p1 is the clock input of timing device a1 and point p2 is the data output of timing device a 1; the timing devices B1 through Bn are timing devices driven by the second clock signal Clk _2, where point p3 is the data input of timing device B1. There may be a plurality of combinational logic devices (combinational logic) between An asynchronous sequential device pair (any one of sequential device a1 to sequential device An and any one of sequential device B1 to sequential device Bn) to form a data link, the sender of the data link is one of sequential device a1 to sequential device An, and the receiver of the data link is one of sequential device B1 to sequential device Bn. For example, the data link may be a timing path.

For example, on an asynchronous interface, more clock domains may also be included. For example, the sender may further include a timing device driven by the third and fourth clock signals Clk _3 and Clk _ 4; the receiving side may further include a timing device driven by the fifth and sixth clock signals Clk _5 and Clk _ 6. For example, one asynchronous sequential device pair may further include one sequential device driven by the third clock signal Clk _3 and one sequential device driven by the sixth clock signal Clk _6, and the like.

Because the phase relation between data and a clock is uncertain, the establishment time or the holding time may not be satisfied, so that a receiving party may see a metastable state.

In addition, because the clock relationship between the sending party and the receiving party is uncertain, the integrated circuit cannot perform static timing analysis, so that the integrated circuit cannot perform coverage verification in the early-stage front-end simulation, and only after the back-end timing is converged, the timing information in the sdf (Standard Delay Format) file is denormalized to a back-end netlist for back-end verification (also called back-end simulation or back-end simulation). However, since the post-simulation verification environment has high difficulty in building, a large number of boundaries (horns) to be covered, long verification time and difficulty in positioning errors, the post-simulation verification environment becomes a bottleneck of verification more and more.

If the design is found to have problems in the post-simulation stage, the problems can be solved only by Engineering Change Order, and the difficulty of Engineering modification is high; moreover, if the engineering modification is executed, the wiring may need to be re-laid, which increases the number of iterations, greatly delays the project progress, and causes the project progress to be delayed.

For example, in addition to performing verification in the later simulation stage, metastable state output with a full random or fixed cycle number may be introduced in the earlier simulation stage, but this method cannot embody the specific characteristics of the asynchronous interface because the asynchronous interface has no timing constraint at all, and the length of the metastable state is completely decoupled from the actual signal delay, resulting in a verification result that is too pessimistic or too optimistic. In addition, if a metastable state is introduced into the front-end simulation, metastable state propagation is easily caused in the logic simulation before synthesis, so that a test case cannot pass, a large amount of time is wasted for positioning a source of the metastable state, and a verification result is over pessimistic.

At least one embodiment of the present disclosure provides an integrated circuit verification method, an integrated circuit verification apparatus, an electronic device, and a non-transitory computer-readable storage medium. The verification method of the integrated circuit comprises the following steps: the method comprises the steps that a plurality of asynchronous time sequence device pairs are obtained, wherein each asynchronous time sequence device pair comprises a first time sequence device and a second time sequence device, the first time sequence device and the second time sequence device are located in two different clock domains of a plurality of clock domains, and an electric signal transmission relation exists between a data output end of the first time sequence device and a data input end of the second time sequence device; according to the asynchronous sequential device pairs, performing model construction processing on the integrated circuit to obtain a circuit to be simulated; performing front-end simulation verification on a circuit to be simulated; wherein the model construction process comprises: for each asynchronous sequential device pair: determining a response time based on a circuit characteristic between the first timing device and the second timing device; constructing a response model according to the response time, wherein the response model comprises an input end and an output end, the response model is configured to output a metastable state signal within the response time from the first moment, and output a steady state response signal after the response time from the first moment, and the first moment is the moment when the input signal received by the input end jumps; the response model is added to a data link in the integrated circuit that is determined based on the first timing device and the second timing device.

The verification method of the integrated circuit provided by at least one embodiment of the present disclosure determines the response time according to the circuit characteristics between the asynchronous sequential device pairs, and this way is closer to the real situation of the circuit, and injects metastable signals into each asynchronous sequential device pair in the asynchronous interface accurately, and implements accurate and fast logic simulation with minor modification, and advances the verification of the asynchronous interface to the front-end simulation stage for execution, and the front-end simulation verification is fast, and saves the time for building the back-end simulation environment, thereby reducing the time cost required for verification; in addition, generally, the back-end simulation can be executed only after the time sequence is converged, and the verification method provided by the disclosure can be executed in the early stage of the project, so that the difficulty in positioning potential problems is greatly reduced, the modification is facilitated, the project research and development time and the later iteration times are greatly shortened, and the project research and development efficiency is improved.

Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings, but the present disclosure is not limited to these specific embodiments.

Fig. 2 is a schematic flow chart of a verification method of an integrated circuit according to at least one embodiment of the disclosure.

For example, the verification method of the integrated circuit is applied to the design of the integrated circuit. For example, after the front-end design (logic design) stage of the circuit is completed, the verification method of the integrated circuit is applied to carry out simulation verification on the asynchronous clock in the circuit design.

For example, an integrated circuit includes a plurality of asynchronous clock domains, e.g., the plurality of asynchronous clock domains includes a clock domain controlled by a plurality of asynchronous clock signals. For example, the clock signals whose two clock signals are asynchronous may be different in clock frequency, such as 100MHz for one clock signal and 120MHz for the other clock signal. For example, the clock signals in which the two clock signals are asynchronous may be the same clock frequency but have different initial phases. That is, the plurality of asynchronous clock signals in this disclosure have no definite phase relationship with each other.

For example, referring to the asynchronous interface shown in fig. 1, the number of the plurality of clock domains is specifically illustrated as 2. As shown in fig. 1, the plurality of clock domains may include a first clock domain determined based on the first clock signal Clk _1 and a second clock domain determined based on the second clock signal Clk _ 2. For example, the first clock domain is a region controlled by the first clock signal Clk _1, and the first clock domain includes a plurality of sequential devices, such as sequential device a1 through sequential device An, driven by the first clock signal Clk _ 1. The second clock domain is a region controlled by the second clock signal Clk _2, and the second clock domain includes a plurality of sequential devices, e.g., sequential device B1 through sequential device Bn, driven by the second clock signal Clk _ 2.

In the present disclosure, the devices include logic devices, which include sequential devices and combinational logic devices. The sequential device refers to a trigger, a register, a latch and other devices in digital circuit design, has storage and memory functions on input signals, and can trigger the sequential device to store the input signals and change the state of output signals when receiving effective edges or effective levels of clock signals. The combinational logic device refers to a device for realizing logic operation, such as an AND gate, an OR gate and the like in digital circuit design, the combinational logic device does not have storage and memory functions on input signals, and at any moment, the state of an output signal of the combinational logic device depends on the state of the input signal at the current moment.

For example, as shown in fig. 2, a verification method for an integrated circuit according to at least one embodiment of the present disclosure includes steps S10 to S30.

In step S10, a plurality of asynchronous sequential device pairs is obtained.

For example, each asynchronous sequential device pair comprises a first sequential device and a second sequential device, the first sequential device and the second sequential device are located in two different clock domains of the plurality of clock domains, and an electrical signal transmission relationship exists between a data output end of the first sequential device and a data input end of the second sequential device.

For example, the two different clock domains include a first clock domain and a second clock domain, the first timing device is an "end timing device" in the first clock domain, and the second timing device is a "start timing device" in the second clock domain, that is, the data output end of the first timing device and any one timing device in the second clock domain have an electrical signal transmission relationship, the electrical signal transmission relationship is realized by at least one combinational logic device, and at this time, any one timing device in the second clock domain is the second timing device.

For example, taking fig. 1 as an example, sequential device a1 and sequential device B1 have an electrical signal transmission relationship, for example, a data signal output by sequential device a1 is transmitted to sequential device B1 via combinational logic, and sequential device B1 samples the data signal according to second clock signal Clk _2, at this time, sequential device a1 and sequential device B1 form an asynchronous sequential device pair, the first sequential device is a1, and the second sequential device is B1.

For example, in some examples, the signal sent by the first timing device is a quasi-static signal, e.g., the quasi-static signal indicates that the signal can be regarded as a steady-state signal, e.g., the signal is a stable signal for a long time before sampling, the receiver does not sample the change of the signal, or the receiver does not care about the metastable state generated by the signal. For example, the quasi-static signal may be an enable signal, a reset signal at the source, or the like. At this time, the second time sequence device does not need to perform synchronous processing on the signal, so that no other time sequence device exists in the electrical signal transmission relation, and a data link formed from the first time sequence device to the second time sequence device is a time sequence path.

For example, in other examples, the signal sent by the first timing device is not a quasi-static signal, and in this case, the second timing device needs to perform synchronization processing on the signal. For example, the synchronization process may be implemented by a synchronization processing module, e.g., the synchronization processing module includes a plurality of cascaded sequential devices. Then, there are multiple sequential devices for synchronous processing in the electrical signal transmission relationship, and the data link formed from the first sequential device to the second sequential device includes multiple sequential paths, for example, the first sequential device and the first sequential device in the synchronous processing module form one sequential path, where the first sequential device is a sequential device that receives a signal sent by the first sequential device in the multiple cascaded sequential devices.

In step S20, a model building process is performed on the integrated circuit according to the plurality of asynchronous sequential device pairs to obtain a circuit to be simulated.

Fig. 3 is a schematic flow chart of a model building process provided in at least one embodiment of the present disclosure.

For example, as shown in fig. 3, the model building process provided by at least one embodiment of the present disclosure includes steps S201 to S203.

For example, steps S201-S203 are performed separately for each asynchronous sequential device pair.

In step S201, a response time is determined according to a circuit characteristic between the first sequential device and the second sequential device.

For example, the circuit characteristics between the first sequential device and the second sequential device may include the sequential logic requirements of the second sequential device. For example, the constraint value that needs to be applied to the data link from the first sequential device to the second sequential device may be determined according to the sequential logic requirements of the second sequential device, and the specific process is described later.

In step S202, a response model is constructed from the response time.

For example, the response model includes an input and an output, and is configured to output a metastable signal within a response time from a first time, and output a steady-state response signal after the response time from the first time, where the first time is a time when an input signal received at the input makes a transition.

For example, after obtaining the response model corresponding to each asynchronous sequential device pair, step S203 is performed to insert the response model into the integrated circuit.

In step S203, a response model is added to the data link in the integrated circuit determined based on the first timing device and the second timing device.

For example, step S203 may include: the response model is inserted between the second sequential device and the device directly connected to the second sequential device, and the output terminal of the response model is directly connected to the data input terminal of the second sequential device.

For example, the device in the original design of the integrated circuit that is directly connected to the second sequential device is hereinafter referred to as the source device. For example, the source device may be a combinational logic device or a first timing device.

For example, the signal output by the source device is called a source signal, and the time when the source signal makes a transition is the first time.

For example, step S201 may include: determining a delay time according to the circuit characteristics; and determining the response time according to the delay time.

For example, determining the delay time based on the circuit characteristics may include: determining a constraint time according to the circuit characteristics; and determining the delay time according to the constraint time.

For example, it may also be determined whether the second timing device needs to perform synchronization processing on the signal sent by the first timing device according to a circuit characteristic between the first timing device and the second timing device, for example, whether the signal sent by the first timing device needs to be performed synchronization processing according to whether the signal sent by the first timing device is a quasi-static signal. The processing manners of steps S201 to S203 are slightly different according to whether the second sequential device needs to perform synchronization processing on the signal sent by the first sequential device. The processing procedures of steps S201 to S203 are specifically described below for two cases, respectively.

For example, when the signal sent by the first timing device is a quasi-static signal, the second timing device does not need to perform synchronous processing on the signal. For example, the signal may be a single bit signal or a bus signal comprising multiple bits, such as an enable signal, a reset signal, an address bus signal, and the like. At this time, the constraint time indicates that the second sequential device collects the steady-state response signal at least at a second time after the first time, and the first time and the second time are different by the constraint time.

For example, constraint time refers to a constraint value that a designer wishes to impose on a data link between a first sequential device to a second sequential device. For example, when the data link is a timing path, this constraint value may be used as a timing constraint for the timing path in the back-end design process.

Because the constraint time is determined according to the circuit characteristics, the method is closer to the actual situation of the asynchronous interface, the metastable state is accurately injected into the asynchronous interface, and some unnecessary simulation scenes are reduced, so that the simulation model is helped to reduce the scenes needing simulation, the accuracy is improved, and the workload of verification is reduced.

For example, the constraint time may be set from two perspectives, a multi-cycle constraint or a maximum delay constraint.

For example, when the constraint time is embodied as a multi-cycle constraint at the back end, the constraint time indicates that the designer expects the source signal to change to respond to the output signal of the response model (i.e., the data signal received by the second sequential device), and the maximum delay between the two actions is x clock cycles of the receiving party.

For example, the clock domain in which the second sequential device is located is determined based on the target clock signal, which may be the second clock signal as described above, for example. Determining a constraint time based on the circuit characteristic may include: and determining the constraint time to be x clock cycles according to the circuit characteristics, wherein the clock cycles are the clock cycles of the target clock signal, and x is a positive integer.

For example, when the constraint time is x clock cycles, the timing constraint imposed by the back-end design process is called a multi-cycle constraint, i.e., data is allowed to stabilize after x cycles, so that routing resources are released during routing, while also reducing routing runtime. It is common for designers to consider the problem generally from the fact that the input signal needs to be used after several clock cycles, e.g., the second sequential device needs to acquire a steady-state signal after 5 clock cycles, then the constraint time may be set to 4 clock cycles to be able to acquire a steady-state signal at the 5 th clock cycle. The setting mode has strong portability, and the constraint time is independent of the process of the circuit and the frequency of the clock signal.

For example, from the constraint time, the constraint value that the design wants to impose can be determined to be x clock cycles.

For example, determining the delay time from the constraint time may include: determining a decision edge, wherein the decision edge is a first transition edge occurring after a first time in the target clock signal; counting y judgment edges by taking the judgment edges as first judgment edges, wherein y is a positive number and is less than or equal to x; and taking the time length between the first moment and the y-th decision edge as the delay time.

Fig. 4 is a schematic diagram of a delay time according to at least one embodiment of the present disclosure.

As shown in fig. 4, the first clock signal represents a clock signal for driving the first sequential device, and the second clock signal represents a clock signal for driving the second sequential device, and as can be seen from fig. 4, the two clock signals have different frequencies, that is, the two clock signals are asynchronous clock signals.

As shown in fig. 4, the source signal is a signal output by the source device, and the time when the source signal makes a transition is the first time.

For example, the constraint time is determined to be 3 clock cycles of the target clock signal (i.e., the second clock signal) according to the circuit characteristics.

As shown in fig. 4, since the first transition edge of the second clock signal occurring after the first time is a falling edge, the edge is determined to be a falling edge. The falling edge is taken as the first judgment edge, and 3 falling edges are counted, namely the falling edges marked as (i), (ii) and (iii) in fig. 4.

As shown in fig. 4, the time from the first moment to the falling edge marked by the third sign is the delay time.

For example, in the case shown in fig. 4, y ═ x ═ 3.

For example, in some embodiments, y may be less than x, e.g., y — 2, etc.

For example, in some embodiments, y may be a fixed value.

For example, in some embodiments, y may be a random value between 0 and x. At the moment, when the source signal change is detected each time, y can select different random values, so that the delay time of the random change is obtained, more simulation conditions are covered, abundant signal relations are obtained, the difference of scenes is increased, boundary conditions are easier to find, and the obtained simulation result is more accurate and reliable.

In the back end design process, the timing constraint judgment is started from the occurrence of the jump of the source signal, and x clock cycles are recorded as delay. However, in the front-end simulation process, if the trigger edge of the second clock device is taken as the start, x clock cycles are counted, taking fig. 4 as an example, if the trigger edge is a rising edge, the delay time obtained in this way is greater than the delay recorded in the back-end design process, and the constraint time used by the front-end simulation does not correspond to the timing constraint applied by the back-end, so that some simulation scenes belong to useless simulation, and some computational power and simulation resources are wasted.

For example, when the constraint time is embodied as a maximum delay constraint, the constraint time indicates that the designer expects the source signal to change to respond to the output signal of the response model (i.e., the data signal received by the second sequential device), and the maximum delay between two actions is p picoseconds.

It should be noted that the unit of the maximum delay time in the present disclosure is described by way of picoseconds, and in practice, different time units may be selected according to needs, such as nanoseconds, milliseconds, and the like, which is not limited by the present disclosure.

For example, for some circuit blocks in the circuit, the enable signal, the reset signal at the source, and other signals similar to quasi-static signals, the load of these signals is large, but the signals are completely stable when needed, and the maximum delay value can be set for these signals according to needs.

For example, determining the constraint time based on the circuit characteristic may include: and determining the maximum time delay between the first time sequence device and the second time sequence device according to the circuit characteristics, and taking the maximum time delay as the constraint time.

For example, determining the delay time from the constraint time may include: determining the delay time to be equal to the constraint time.

For example, after obtaining the delay time in two ways as described above, determining the response time according to the delay time may include: determining that the response time is less than or equal to the delay time.

For example, the constraint time specifies the worst case of the data link, i.e. the longest delay required for the input signal to stabilize, and the actual back-end physical implementation may be delayed less than the constraint time. In circuit simulation, it is usually necessary to verify whether the circuit can still work normally under the worst condition, and if the circuit can still work normally under the worst condition, it indicates that the circuit is robust enough, so the response time of the response model can be selected as the delay time.

Of course, in practice, the response time less than or equal to the delay time, or the random value between 0 and the delay time, etc. may be selected according to the needs to cover more verification scenarios, obtain rich signal relationships, and obtain more accurate and reliable simulation results with less resource consumption and computational power consumption.

For example, in some embodiments, the model building process may further include: the simulation models are named according to the constraint time, so that the naming of the simulation models corresponds to the constraint time.

For example, the response model may be made as a general module, and the constraint time desired by the designer may be obtained according to different names during the instantiation process, so that the response time is obtained with reference to the process of step S201. For example, the response time represents the time required for a signal input from an input terminal of the response model to change until an output signal of the response model responds, and the response model constructs the response model by setting the output signal to be a metastable state signal during the response time.

For example, the response model is named Cx, and the constraint time representing the expected response model is x clock cycles of the target clock signal, i.e., the designer wants to generate a timing constraint of x cycles in the back-end design process.

For example, the response model is named Dp, which means that the constraint time of the expected response model is p picoseconds, i.e. the designer wants to generate p picoseconds of timing constraint in the back-end design process.

This approach may integrate the response model into a physical device with that name during back-end design, e.g., the physical device may be a cache. The back-end design process can obtain the timing constraints desired by the front-end designer through the names of the physical devices, so as to automatically generate sdc (synchronization design constraints) files as references for wiring optimization, adding timing constraints to asynchronous interfaces and the like. Therefore, the back end automatically generates relevant constraints by acquiring the keywords of the module name without additionally providing the front end, so that the workload of the front end is reduced, the design intention is well conveyed, the understanding and the constraints of the asynchronous interface in the design process of the front end and the back end are consistent, a circuit which is more in line with the actual situation is obtained, the simulation workload is reduced, the invalid simulation is avoided, and the circuit is efficiently verified under the conditions of limited calculation power and time as far as possible.

For example, the response model outputs a metastable signal within a response time after the first time, followed by a steady-state signal that is the response of the response model to the source signal. That is, the response time indicates the time at which the response model outputs the metastable state.

When the uncertain state is in logic simulation, it is possible that many subsequent signals become uncertain states due to propagation around the simulation tool, and further the test case fails. Each stage or different levels of circuit verification may result in too many test cases or unexpected problems due to propagation of the uncertain state, thereby requiring a lot of time to locate the source of the uncertain state. In order to avoid such a too pessimistic scenario, the response model is provided with signal configuration parameters, according to which the type of metastable signal output by the response model can be freely adjusted.

For example, meta-stable signals include random signals and indeterminate state signals (also called X-state signals). When the response model executes outputting the metastable state signal in the response time from the first moment, the following operations are executed: acquiring a signal configuration parameter; outputting one of the random signal or the indeterminate state signal during a response time from the first time based on the signal configuration parameter.

Generally, the uncertain state signal corresponds to the worst case of simulation, and can be used to determine whether the circuit in the worst simulation case can work normally. The random signal comprises random 0's or 1's, i.e. the result obtained each time the same signal is sampled is not fixed. Therefore, a designer can freely select the form of the metastable state signal according to the required simulation scene and the signal configuration parameters.

Constraint time may also be recorded by a configuration file, for example, and provided to the back-end during back-end design.

For example, the response model may be implemented in a behavioral level description language, such as a hardware programming language.

Fig. 5A is a schematic diagram of a response model according to an embodiment of the disclosure.

For example, the constraint time is obtained according to the naming of the response model, and then the response time is obtained according to step S201. For example, the response model is constructed by determining the type of metastable signal output by the response model based on the signal configuration parameters of the response model.

As shown in fig. 5A, a response model constructed according to steps S201 and S202 is inserted between the source device and the second sequential device. The input end of the response model is connected with the data signal output end of the source device, and the output end of the response model is connected with the data signal input end of the second sequential device.

For example, the source device shown in FIG. 5A is a combinational logic device.

Fig. 5B is a schematic diagram of an output signal of a response model according to an embodiment of the disclosure.

For example, if the response model instantiates the name "C3", it indicates that the constraint time is 3 clock cycles of the second clock signal. At this time, the description of the first clock signal, the second clock signal and the source signal in fig. 5B may refer to the relevant contents shown in fig. 4, and will not be repeated here.

For example, as shown in FIG. 5B, the output signal represents the output signal variation of the response model, and the shaded portion in the output signal represents that the output signal is in a metastable state, such as an indeterminate state or a random signal.

For example, as shown in FIG. 5B, the response time is equal to the delay time. The output signal of the response model is in a stable low level state before the first moment, and after the source signal received by the input end of the response model jumps (namely the first moment), the output signal becomes a metastable state signal and lasts for the response time; then, the output signal generates a rising edge, namely a response corresponding to the model output source signal; and then stabilizes to a high state.

Fig. 5C is a schematic diagram of an output signal of a response model according to another embodiment of the disclosure.

For example, if the response model instantiates a name "Dp," it means that the constraint time is p picoseconds. For example, the constraint time, the delay time, and the response time are equal to each other, so that the response time is p picoseconds as shown in fig. 5C.

As shown in fig. 5C, the output signal of the response model is in a stable low state before the first time, and after the source signal received by the input terminal of the response model makes a transition (i.e., the first time), the output signal becomes a metastable state signal and lasts for the response time; then, the output signal of the response model generates a rising edge, namely the response corresponding to the output source signal of the response model; and then stabilizes to a high state.

For example, the response model provided by at least one embodiment of the present disclosure sets a more accurate response time according to the circuit actual situation, and introduces meta-stable states with different durations according to the circuit actual situation, so as to more accurately reflect the uncertainty of the asynchronous interface in the front-end logic simulation phase.

For example, when the signal sent by the first timing device is not a quasi-static signal, the second timing device needs to perform synchronization processing on the signal to ensure that the signals received by multiple receiving sides are uniform.

For example, in some embodiments, the response model further includes a synchronization processing module comprising a plurality of timing devices, the synchronization processing module configured to perform synchronization processing on signals transmitted by the first timing device. For example, the synchronization processing module may be a multi-stage cascaded flip-flop.

For example, the response model may configure whether to include a synchronization processing module according to the mode parameter, for example, when the mode parameter is a first value, the obtained response model includes the synchronization processing module, and when the mode parameter is a second value, the obtained response model does not include the synchronization processing module. Therefore, response modules with different functions can be conveniently and flexibly obtained.

For example, determining the delay time based on the circuit characteristics may include: determining constraint time according to circuit characteristics, wherein the constraint time represents that a third time sequence device acquires a steady-state response signal at least at a second moment after the first moment, the first moment and the second moment are different by the constraint time, and the third time sequence device represents a time sequence device which is directly connected with a data signal input end of a synchronous processing module in a plurality of time sequence devices; and determining the delay time according to the constraint time.

For example, the third sequential device is the "first-stage sequential device" in the synchronous processing module. This constraint value may be used as a timing constraint for a timing path formed by the first timing device and the first stage timing device in the aforementioned synchronous processing unit during back-end design.

When the second sequential device needs to perform synchronous processing on a signal sent by the first sequential device, the constraint time refers to a constraint value that a designer wishes to apply to a timing path from the first sequential device to a third sequential device. This constraint value may be used, for example, as a timing constraint for the timing path during back-end design.

For example, the constraint time may also be set from two angles, from a multi-cycle constraint or a maximum delay constraint at this time. The specific constraint time setting mode is the same as the above process when the synchronization processing is not needed, and is not described herein again.

And after the constraint time is obtained, obtaining delay time according to the constraint time. The specific process and the corresponding technical effect are the same as those of the process without the need of synchronous processing, and are not described herein again.

When the synchronization processing is required, the path delay from the source device to the second sequential device further includes a delay introduced in the synchronization processing process, for example, the introduced delay at least includes a processing delay corresponding to the synchronization processing module.

For example, determining the response time from the delay time may include: determining the processing delay corresponding to the synchronous processing module; and determining the response time according to the processing delay and the delay time.

For example, determining the response time based on the processing delay and the delay time may include: determining that the response time is less than or equal to the sum of the processing delay and the delay time.

For example, the delay specified by the constraint time or delay time is the delay of the transmission of the source signal from the output of the source device to the third sequential device.

For example, since the phase relationship between the clock signal driving the first timing device and the clock signal driving the third timing device is uncertain, the output of the first timing device may be metastable state for the third timing device, and at this time, the delay introduced by the synchronization processing process includes metastable state delay in addition to the processing delay of the synchronization processing module itself.

For example, determining the response time according to the processing delay and the delay time may include: determining that the response time is less than or equal to a sum of the processing delay, the metastable delay, and the delay time.

For example, the metastability delay is typically one clock cycle of the target clock signal.

Fig. 6A is a schematic diagram of a response model according to an embodiment of the disclosure.

For example, the constraint time is obtained according to the naming of the response model, and then the response time is obtained according to step S201. For example, the type of metastable signal output by the response model is determined according to the signal configuration parameters of the response model.

As shown in fig. 6A, when the second sequential device needs to perform synchronization processing, a response model constructed according to steps S201 and S202 is inserted between the source device and the second sequential device. The input end of the response model is connected with the data signal output end Q of the source device, and the output end of the response model is connected with the data signal input end D of the second sequential device.

For example, the response model includes a synchronization processing module that includes 3 cascaded flip-flops, the 3 cascaded flip-flops including flip-flop reg1, flip-flop reg2, and flip-flop reg3 as shown in fig. 6A. Flip-flop reg1 is a third sequential device, and data input D1 of flip-flop reg1 receives a source signal received at an input of the response model; the data output Q1 of flip-flop reg1 is directly connected to the data input D2 of flip-flop reg2, the data output Q2 of flip-flop reg2 is directly connected to the data input D3 of flip-flop reg3, and the data output Q3 of flip-flop reg3 is connected to the output of the response model.

For example, a source signal output by a source device driven by a first clock signal is received by the flip-flop reg1, and since the phase relationship between the first clock signal and a second clock signal is uncertain, the output of the flip-flop reg1 may be metastable, but the signal output by the data output terminal Q3 is stable with a high probability through the flip-flop reg2 and the flip-flop reg3 cascaded in two subsequent stages.

Since the data input of the flip-flop in the timing constraint is the end of the timing path, the delay specified by the constraint time, i.e., the delay time, represents only the delay from the output of the source device to the data input D1 of the flip-flop reg 1.

For example, the source device shown in fig. 6A is a first timing device.

From the simulation point of view, the delay of the whole response model is composed of the delay time, the delay of the synchronous processing module and the possible metastable state delay.

Fig. 6B is a schematic diagram of an output signal of a response model according to an embodiment of the disclosure. The response model is the response model in fig. 6A.

As shown in fig. 6B, for example, it is assumed that the response model instantiation is named "C3", which indicates that the constraint time is 3 clock cycles of the second clock signal, i.e., the delay of the source signal from the data output terminal of the source device to the data input terminal D1 of the flip-flop reg1 is 3 clock cycles of the second clock signal.

The processing delay generated by the synchronous processing module is 3 clock cycles of the second clock signal. If the signal output by the first timing device received by the third timing device is a metastable state signal, the metastable state delay generated is 1 clock cycle of the second clock signal.

The delay of one clock cycle of the generation of the metastable state occurs randomly in consideration of the randomness of the metastable state, and thus, the delay from the data output terminal of the source device to the data input terminal of the second sequential device is 6 (the sum of the delay time and the processing delay time) or 7 (the sum of the delay time, the processing delay time and the metastable state delay time) clock cycles of the second clock signal.

Referring to fig. 6A and 6B, a first clock signal represents a clock signal of a driving source device, a second clock signal represents a clock signal driving a second sequential device, the source signal is a signal output from the source device, and a timing at which a transition of the source signal occurs is a first timing.

For the determination of the falling edges and the delay times of the second clock signals marked by the symbols (i), (ii), and (iii), reference may be made to the relevant contents in fig. 4, which is not described herein again.

Then, since the flip-flops in the synchronous processing module are all driven by the rising edge, 3 rising edges (marked as (r), (v), and (c) in fig. 6B) are counted from the falling edge to obtain the processing delay.

If the output signal of the flip-flop reg1 is meta-stable, a meta-stable delay of one clock cycle is also required, such as the rising edge labeled as c in fig. 6B.

Thus, as shown in FIG. 6B, the response time is equal to the sum of the aforementioned latency time, processing latency, and metastability latency. It should be noted that the metastable delay should actually occur before the rising edge r, that is, if the rising edge r arrives, the signal collected by the flip-flop reg1 is metastable, which generates the metastable delay, and fig. 6B is for convenience of description and is shown after the processing delay.

For example, as shown in fig. 6B, the output signal of the response model is in a stable low state before the first time, and after a transition of the source signal received at the input terminal of the response model (i.e., the first time), the output signal of the response model becomes a metastable state signal and lasts for the response time; then, the output signal of the response model generates a rising edge, namely the response corresponding to the output source signal of the response model; and then stabilizes to a high state.

To synthesize the foregoing, for example, when building a response module, a generic module is created and a plurality of external interfaces are provided for the generic module for configuration.

For example, for the case that the synchronous processing needs to be executed, a response model containing a synchronous processing module is obtained by configuring the mode parameters; selecting a metastable state signal type of the response model through configuration signal configuration parameters; obtaining the response time of the response model by setting the name of the response model; and connecting the output end of the constructed response model with the input end of the second sequential device, and connecting the input end of the response model with the data output end of the source device to complete the processing of one data link.

For the situation that synchronous processing does not need to be executed, obtaining a response model without a synchronous processing module by configuring mode parameters; selecting a metastable state signal type of the response model through configuration signal configuration parameters; obtaining the response time of the response model by setting the name of the response model; and connecting the output end of the constructed response model with the input end of the second sequential device, and connecting the input end of the response model with the data output end of the source device to complete the processing of one data link.

Therefore, the response model can be constructed according to the actual condition of the circuit, and the obtained response model is closer to the real state of the circuit. And various external interfaces are provided for flexibly configuring the response model, so that the method is strong in transportability, more flexible in use and capable of conveniently obtaining richer simulation scenes.

In step S30, a front-end simulation verification is performed on the circuit to be simulated.

And performing logic simulation on the circuit to be simulated obtained in the step S20 to determine whether the circuit can normally operate in various simulation scenarios, and modifying and iterating an RTL file (Register Transfer Level, Register Transfer Level description file) according to the simulation result.

Therefore, the verification method of the integrated circuit provided by at least one embodiment of the present disclosure can implement front-end simulation verification of the asynchronous interface with a small change, the simulation scenario is closer to the actual situation of the circuit, the obtained simulation result is neither pessimistic nor optimistic, and the specific delay of the asynchronous interface can be accurately reflected, thereby implementing relatively accurate and rapid front-end simulation verification of the asynchronous interface, the front-end simulation stage can reflect the important features of the asynchronous interface, so that the asynchronous interface can be verified at an early stage of a project, the project development time and the iteration number are greatly shortened, and the verification difficulty is reduced.

And taking the front-end netlist obtained by the front-end simulation verification as a circuit to be planned, and continuously executing a back-end design flow.

For example, the verification method for an integrated circuit provided in at least one embodiment of the present disclosure further includes: obtaining a circuit to be planned which passes simulation verification, wherein the circuit to be planned comprises a plurality of asynchronous sequential device pairs; executing planning processing on a circuit to be planned; wherein the planning process comprises: replacing at least one response model corresponding to at least one asynchronous sequential device pair in the plurality of asynchronous sequential device pairs with corresponding physical devices, wherein the names of the physical devices are the same as the names of the corresponding response models; a plurality of constraint times are obtained according to the naming of the physical device.

For example, in some embodiments, data links between some asynchronous sequential device pairs that do not perform subsequent optimization processes for asynchronous interfaces cannot insert a physical device that responds to a model replacement.

For example, to flexibly inject metastability through a response model, the response model may be described in a behavioral level language. Since behavioral level language descriptions are non-synthesizable languages, these response models need to be replaced with synthesizable circuit descriptions in the synthesis phase.

For example, in the synthesis phase, the response model inserted on the data link formed by each asynchronous sequential device pair may be replaced with the corresponding physical device. For example, the name of the physical device is the same as the name of the response model.

For example, if the response model does not need to perform synchronization, the physical device corresponding to the response model is a buffer, and the timing constraint desired by the front-end designer is provided to the back-end designer through the naming of the buffer. For example, if the simulation model is named "Cx", it indicates that the constraint time corresponding to the asynchronous sequential device pair corresponding to the simulation model is x clock cycles of the target clock signal.

For example, if the response model needs to execute the synchronization processing, the physical device corresponding to the response model is in the form of a combination of a buffer and a synchronization processing circuit unit, and the response model after physical implementation can not only provide the timing constraint desired by the front-end designer to the rear-end designer through the naming of the buffer, but also can complete the synchronization processing function. For example, if the simulation model is named "Dy", it indicates that the constraint time corresponding to the asynchronous sequential device pair corresponding to the simulation model is y picoseconds.

Here, the constraint time is defined the same as the constraint time in the foregoing front-end simulation process, and is not described here again.

For example, after a constraint time expected by the front end is obtained, a place and route optimization, a timing constraint, a timing check, and the like may be performed according to the constraint time.

For example, based on the naming of the physical devices, a timing constraint file, i.e., a sdc file, may be generated for use as a location reference for the device layout, etc.

For example, when the constraint time is x clock cycles of the target clock signal, the timing constraint placed on asynchronous timing device pairs in the back-end design is a multi-cycle constraint. For example, a multicycle constraint may be represented by a set _ multicycle _ path command.

For example, when the constraint time is y picoseconds, the timing constraint set for the asynchronous sequential device pair in the back-end design is a maximum delay constraint, which may be represented by a set _ max _ delay command, for example.

For example, the multi-cycle constraint or the maximum delay constraint herein is for a timing path from a first timing device to a second timing device, or a timing path from a first timing device and a third timing device in a synchronous processing module.

For example, the verification method for an integrated circuit provided in at least one embodiment of the present disclosure further includes: and performing layout and wiring optimization on the circuit to be planned according to the plurality of constraint times.

For example, if the constraint time corresponding to the first sequential device and the second sequential device is short, the two sequential devices need to be placed at a short distance to satisfy the timing constraint desired by the front end. Therefore, the constraint time can be provided to the back end as a wiring delay reference, so that the understanding and constraint of the asynchronous interface in the design process of the front end and the back end are consistent, and the physical realization of the circuit meeting the design requirement of the front end is obtained.

For example, the planning process provided by at least one embodiment of the present disclosure may further include: setting a virtual clock domain; and setting timing constraints for a plurality of asynchronous sequential device pairs in the circuit to be planned according to a plurality of constraint times.

For example, setting a virtual clock domain may include: determining at least one virtual clock based on the plurality of asynchronous sequential device pairs and the plurality of clock domains; and aiming at each virtual clock, setting at least one timing path determined based on a plurality of asynchronous timing device pairs to belong to the same virtual clock domain, wherein the same virtual clock domain is determined based on each virtual clock.

For example, if the asynchronous interface of the integrated circuit includes a smaller number of clock domains, e.g., 2 clock domains, the virtual clock domain is usually the clock domain of the receiving party, e.g., the clock domain in which the second timing device is located.

For example, if an asynchronous interface of an integrated circuit includes a large number of clock domains, since the layout and routing adjustment is an overall adjustment, if routing optimization is performed every two clock domains, each optimization iteration may have a large impact on each other, the number of iterations is large, and it is difficult to find an optimal routing result.

For example, the clock signal with the highest clock frequency or the most receiver sequential devices driven on an asynchronous interface may be selected from a plurality of clock domains as the virtual clock domain.

For each virtual clock domain, assuming that the devices on the asynchronous interface all belong to the virtual clock domain, the time sequence of the asynchronous time sequence device pairs can be checked according to the time sequence constraint set by the asynchronous time sequence device pairs. Such timing check may refer to timing check of the synchronization circuit, which is not described herein.

For example, the verification method provided by at least one embodiment of the present disclosure introduces a virtual clock to implement timing constraints on an asynchronous interface, and limits the delay of an input signal to a specified range according to the constraints in a back-end design process.

For example, in a specific example, in the back-end design process, an initial layout and routing process is first performed on a circuit to be planned to obtain an initial layout planning result, and the process executes corresponding constraints according to an automatic layout and routing algorithm.

And then, carrying out time sequence check on the initial layout planning result to determine a plurality of time sequence paths which do not meet the time sequence constraint condition on the asynchronous interface.

And then, according to the specific conditions of a plurality of time sequence paths, physically realizing part or all of the response models as corresponding physical devices, and generating the sdc file according to the names of the physical devices.

And then, performing layout and wiring optimization iteration according to the sdc file, setting a virtual clock domain, adding corresponding time sequence constraints to the multiple time sequence paths needing time sequence adjustment, performing time sequence check and the like, and finally obtaining a layout planning result meeting the conditions.

According to the verification method of the integrated circuit provided by at least one embodiment of the disclosure, an asynchronous interface verification method capable of penetrating through a front-end design flow and a back-end design flow is obtained by introducing a response model, the module conveys constraint time expected by a designer through module naming, certain time sequence constraint is performed on an asynchronous interface in a back-end design process according to the constraint time required by a front end, time sequence check is executed, and layout and wiring are performed according to the constraint time, so that the obtained circuit can better embody the design intention of the front end.

Corresponding to the verification method of the integrated circuit described above, at least one embodiment of the present disclosure further provides a verification apparatus of the integrated circuit, and fig. 7A is a schematic block diagram of the verification apparatus of the integrated circuit provided in at least one embodiment of the present disclosure.

For example, as shown in fig. 7A, the verification apparatus 700 of the integrated circuit includes at least: an acquisition unit 701, a processing unit 702 and a simulation verification unit 703.

The obtaining unit 701 is configured to obtain a plurality of asynchronous sequential device pairs, where each asynchronous sequential device pair includes a first sequential device and a second sequential device, the first sequential device and the second sequential device are located in two different clock domains of the plurality of clock domains, and an electrical signal transmission relationship exists between a data output end of the first sequential device and a data input end of the second sequential device.

The processing unit 702 is configured to perform a model building process on the integrated circuit according to the plurality of asynchronous sequential device pairs to obtain a circuit to be simulated.

The simulation verification unit 703 is configured to perform front-end simulation verification on the circuit to be simulated.

Fig. 7B is a schematic block diagram of a processing unit according to at least one embodiment of the disclosure.

For example, as shown in fig. 7B, the processing unit 702 includes: determining sub-unit 7021, constructing sub-unit 7022, adding sub-unit 7023, and naming sub-unit 7024.

Determining subunit 7021 is configured to determine a response time according to a circuit characteristic between the first sequential device and the second sequential device.

And a constructing subunit 7022 configured to construct a response model according to the response time, where the response model includes an input end and an output end, and the response model is configured to output a metastable state signal within the response time from the first time and output a steady state response signal after the response time from the first time, where the first time is a time when the input signal received by the input end makes a transition.

An adding subunit 7023 configured to add the response model to a data link in the integrated circuit determined based on the first timing device and the second timing device.

For example, determining subunit 7021, when performing determining the response time according to the circuit characteristic between the first sequential device and the second sequential device, includes performing the following operations: determining a delay time according to the circuit characteristics; and determining the response time according to the delay time.

Determining subunit 7021 performs the following operations when determining the delay time according to the circuit characteristic: determining constraint time according to the circuit characteristics, wherein the constraint time represents that the second sequential device acquires a steady-state response signal at least at a second moment after the first moment, and the first moment and the second moment are different by the constraint time; and determining the delay time according to the constraint time.

For example, the clock domain in which the second sequential device is located is determined based on the target clock signal, and the determining subunit 7021 performs determining the constraint time according to the circuit characteristics, including performing the following operations: and determining the constraint time to be x clock cycles according to the circuit characteristics, wherein the clock cycles are the clock cycles of the target clock signal, and x is a positive integer.

For example, determining subunit 7021 performs determining the delay time from the constraint time, including performing the following operations: determining a decision edge, wherein the decision edge is a first transition edge occurring after a first time in the target clock signal; taking the judgment edge as a first judgment edge, and counting y judgment edges, wherein y is a positive number and is less than or equal to x; and taking the time length between the first moment and the y-th decision edge as the delay time.

For example, determining subunit 7021 performs determining the constraint time based on the circuit characteristic, including performing the following operations: and determining the maximum time delay between the first time sequence device and the second time sequence device according to the circuit characteristics, and taking the maximum time delay as the constraint time.

For example, determining subunit 7021 performs determining the delay time according to the constraint time, including performing the following operations: the delay time is determined to be equal to the constraint time.

For example, determining subunit 7021 performs determining the response time according to the delay time, including performing the following operations: determining that the response time is less than or equal to the delay time.

For example, the second time sequence device performs synchronization processing on a signal sent by the first time sequence device, the response model further includes a synchronization processing module, the synchronization processing module includes a plurality of time sequence devices, the synchronization processing module is configured to perform synchronization processing on a signal sent by the first time sequence device, and the determining subunit 7021 performs determining the delay time according to the circuit characteristic, including performing the following operations: determining constraint time according to circuit characteristics, wherein the constraint time represents that a third time sequence device acquires a steady-state response signal at least at a second moment after the first moment, the first moment and the second moment are different by the constraint time, and the third time sequence device represents a time sequence device which is directly connected with a data signal input end of a synchronous processing module in a plurality of time sequence devices; and determining the delay time according to the constraint time.

For example, determining subunit 7021 performs determining the response time according to the delay time, including performing the following operations: determining the processing delay corresponding to the synchronous processing module; and determining the response time according to the processing delay and the delay time.

For example, determining subunit 7021 performs determining the response time based on the processing delay and the delay time, including performing the following operations: determining that the response time is less than or equal to the sum of the processing delay and the delay time.

For example, in response to the signal received by the third sequential device being a metastable state signal, determining subunit 7021 performs the following operations when determining the response time according to the processing delay and the delay time: determining that the response time is less than or equal to a sum of the processing delay, the metastable delay, and the delay time.

For example, adding subunit 7023, when performing adding the response model to the data link in the integrated circuit that is determined based on the first timing device and the second timing device, includes performing the following operations: the response model is inserted between the second sequential device and the device directly connected to the second sequential device, and the output terminal of the response model is directly connected to the data input terminal of the second sequential device.

For example, processing unit 702 also includes a naming sub-unit 7024.

Naming subunit 7024 is configured to name the simulation models according to the constraint times such that the naming of the simulation models corresponds to the constraint times.

For example, the meta-stable signal includes a random signal and an indeterminate signal, and the response model when executing outputting the meta-stable signal within the response time from the first time includes: acquiring a signal configuration parameter; one of a random signal or an indeterminate state signal is output during a response time from the first time based on the signal configuration parameter.

For example, as shown in fig. 7A, the verification apparatus 700 for an integrated circuit further includes a planning processing unit 704.

The planning processing unit 704 is configured to obtain a circuit to be planned which passes simulation verification, wherein the circuit to be planned includes a plurality of asynchronous sequential device pairs; and executing planning processing on the circuit to be planned.

Fig. 7C is a schematic block diagram of a planning processing unit according to at least one embodiment of the present disclosure.

For example, as shown in fig. 7C, plan processing unit 704 includes a constraint time acquisition unit 7041, an optimization unit 7042, a timing constraint setting unit 7043, and a timing check unit 7044.

For example, the constraint time obtaining unit 7041 is configured to replace at least one response model corresponding to each of at least one asynchronous sequential device pair of the plurality of asynchronous sequential device pairs with a corresponding physical device, where the name of the physical device is the same as the name of the corresponding response model; a plurality of constraint times are obtained according to the naming of the physical device.

For example, the optimizing unit 7042 is configured to perform layout and routing optimization on the circuit to be planned according to a plurality of constraint times.

For example, the timing constraint setting unit 7043 is configured to set a virtual clock domain; and setting timing constraints for a plurality of asynchronous sequential device pairs in the circuit to be planned according to a plurality of constraint times.

For example, when the timing constraint setting unit 7043 performs setting of the virtual clock domain, the following operations are performed: determining at least one virtual clock based on the plurality of asynchronous sequential device pairs and the plurality of clock domains; and aiming at each virtual clock, setting at least one timing path determined based on a plurality of asynchronous timing device pairs to belong to the same virtual clock domain, wherein the same virtual clock domain is determined based on each virtual clock.

For example, the timing check unit 7044 is configured to perform timing check on a plurality of asynchronous sequential device pairs according to timing constraints set by the plurality of asynchronous sequential device pairs.

For example, the acquisition unit 701, the processing unit 702, and the simulation verification unit 703 include codes and programs stored in a memory; the processor may execute the code and programs to implement some or all of the functions of the acquisition unit 701, the processing unit 702, and the simulation verification unit 703 as described above. For example, the acquisition unit 701, the processing unit 702, and the simulation verification unit 703 may be dedicated hardware devices for implementing some or all of the functions of the acquisition unit 701, the processing unit 702, and the simulation verification unit 703 as described above. For example, the obtaining unit 701, the processing unit 702, and the simulation verification unit 703 may be one circuit board or a combination of multiple circuit boards for implementing the functions as described above. In the embodiment of the present application, the one or a combination of a plurality of circuit boards may include: (1) one or more processors; (2) one or more non-transitory memories connected to the processor; and (3) firmware stored in the memory executable by the processor.

It should be noted that the obtaining unit 701 is configured to implement step S10 shown in fig. 2, the processing unit 702 is configured to implement step S20 shown in fig. 2, and the simulation verification unit 703 is configured to implement step S30 shown in fig. 2. Thus, for the specific description of the obtaining unit 701, reference may be made to the description related to step S10 shown in fig. 2 in the embodiment of the verification method of the integrated circuit, for the specific description of the processing unit 702, reference may be made to the description related to step S20 shown in fig. 2 in the embodiment of the verification method of the integrated circuit, and for the specific description of the simulation verification unit 703, reference may be made to the description related to step S30 shown in fig. 2 in the embodiment of the verification method of the integrated circuit. In addition, the verification apparatus of the integrated circuit can achieve the similar technical effects as the verification method of the integrated circuit, and the details are not repeated herein.

At least one embodiment of the present disclosure further provides an electronic device, and fig. 8 is a schematic block diagram of the electronic device provided in at least one embodiment of the present disclosure.

For example, as shown in fig. 8, the electronic apparatus includes a processor 1001, a communication interface 1002, a memory 1003, and a communication bus 1004. The processor 1001, the communication interface 1002, and the memory 1003 communicate with each other via the communication bus 1004, and components such as the processor 1001, the communication interface 1002, and the memory 1003 may communicate with each other via a network connection. The present disclosure is not limited herein as to the type and function of the network.

For example, memory 1003 is used to store computer-executable instructions non-transiently. When the processor 1001 is configured to execute the computer-executable instructions, the computer-executable instructions are executed by the processor 1001 to implement the method for verifying the integrated circuit according to any of the above embodiments. For specific implementation and related explanation of each step of the verification method of the integrated circuit, reference may be made to the above-mentioned embodiment of the verification method of the integrated circuit, which is not described herein again.

For example, the implementation manner of the verification method of the integrated circuit implemented by the processor 1001 executing the program stored in the memory 1003 is the same as the implementation manner mentioned in the foregoing embodiment of the verification method of the integrated circuit, and is not described herein again.

For example, the communication bus 1004 may be a peripheral component interconnect standard (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is shown, but this does not mean that there is only one bus or one type of bus.

For example, communication interface 1002 is used to enable communication between an electronic device and other devices.

For example, the processor 1001 and the memory 1003 may be provided on a server side (or a cloud side).

For example, the processor 1001 may control other components in the electronic device to perform desired functions. The processor 1001 may be a Central Processing Unit (CPU), a Network Processor (NP), etc., and may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components. The Central Processing Unit (CPU) may be an X86 or ARM architecture, etc.

For example, memory 1003 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and/or non-volatile memory. Volatile memory can include, for example, Random Access Memory (RAM), cache memory (cache), and/or the like. The non-volatile memory may include, for example, Read Only Memory (ROM), a hard disk, an Erasable Programmable Read Only Memory (EPROM), a portable compact disc read only memory (CD-ROM), USB memory, flash memory, and the like. On which one or more computer-executable instructions may be stored and executed by the processor 1001 to implement various functions of the electronic device. Various application programs and various data and the like can also be stored in the storage medium.

For example, for the detailed description of the process of the electronic device performing the verification of the integrated circuit, reference may be made to the related description in the embodiment of the verification method of the integrated circuit, and repeated descriptions are omitted here.

Fig. 9 is a schematic diagram of a non-transitory computer-readable storage medium according to at least one embodiment of the disclosure. For example, as shown in fig. 9, one or more computer-executable instructions 1101 may be non-temporarily stored on a storage medium 1100. For example, the computer-executable instructions 1101, when executed by a processor, may perform one or more steps in a method of verification of an integrated circuit according to the above.

For example, the storage medium 1100 may be applied to the verification apparatus 1400 of the electronic device and/or the integrated circuit described above. For example, the storage medium 1100 may include the memory 1003 in the electronic device.

For example, the description of the storage medium 1100 may refer to the description of the memory in the embodiment of the electronic device, and repeated descriptions are omitted.

For the present disclosure, there are also several points to be explained:

(1) the drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to the common design.

(2) Thicknesses and dimensions of layers or structures may be exaggerated in the drawings used to describe embodiments of the present invention for clarity. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element or intervening elements may be present.

(3) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.

The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and the scope of the present disclosure should be subject to the scope of the claims.

Claims

1. A method of validating an integrated circuit, wherein the integrated circuit comprises a plurality of asynchronous clock domains,

the verification method comprises the following steps:

acquiring a plurality of asynchronous sequential device pairs, wherein each asynchronous sequential device pair comprises a first sequential device and a second sequential device, the first sequential device and the second sequential device are positioned in two different clock domains of the plurality of clock domains, and an electrical signal transmission relationship exists between a data output end of the first sequential device and a data input end of the second sequential device;

according to the asynchronous sequential device pairs, performing model construction processing on the integrated circuit to obtain a circuit to be simulated;

performing front-end simulation verification on the circuit to be simulated;

wherein the model building process comprises:

for each asynchronous sequential device pair:

determining a response time based on a circuit characteristic between the first timing device and the second timing device;

constructing a response model according to the response time, wherein the response model comprises an input end and an output end, the response model is configured to output a metastable state signal in the response time from a first time, and output a steady state response signal after the response time from the first time, and the first time is the time when the input signal received by the input end jumps;

adding the response model to a data link in the integrated circuit determined based on the first timing device and the second timing device.

2. A verification method according to claim 1, wherein determining a response time from circuit characteristics between the first and second timing devices comprises:

determining a delay time according to the circuit characteristics;

and determining the response time according to the delay time.

3. A verification method according to claim 2, wherein determining a delay time from the circuit characteristic comprises:

determining a constraint time according to the circuit characteristic, wherein the constraint time represents that the second sequential device acquires a steady-state response signal at a second moment at least after the first moment, and the first moment and the second moment are different by the constraint time;

and determining the delay time according to the constraint time.

4. A verification method according to claim 3, wherein the clock domain in which the second sequential device is located is determined based on a target clock signal,

determining a constraint time based on the circuit characteristic, comprising:

and determining the constraint time to be x clock cycles according to the circuit characteristics, wherein the clock cycles are clock cycles of the target clock signal, and x is a positive integer.

5. The authentication method of claim 4, wherein determining the delay time from the constraint time comprises:

determining a decision edge, wherein the decision edge is a first transition edge in the target clock signal that occurs after the first time;

counting y judgment edges by taking the judgment edges as first judgment edges, wherein y is a positive number and is less than or equal to x;

and taking the time length between the first moment and the y-th judgment edge as the delay time.

6. A verification method according to claim 5 wherein y is a random value between 0 and x.

7. A verification method according to claim 3, wherein determining a constraint time from the circuit characteristics comprises:

and determining the maximum time delay between the first time sequence device and the second time sequence device according to the circuit characteristics, and taking the maximum time delay as the constraint time.

8. The authentication method of claim 7, wherein determining the delay time from the constraint time comprises:

determining that the delay time is equal to the constraint time.

9. The authentication method of any one of claims 3-8, wherein determining the response time from the delay time comprises:

determining that the response time is less than or equal to the delay time.

10. A verification method according to claim 2, wherein said second sequential device performs synchronization processing on a signal transmitted by said first sequential device,

the response model further includes a synchronization processing module comprising a plurality of timing devices, the synchronization processing module configured to perform synchronization processing on signals transmitted by the first timing device,

determining a delay time based on the circuit characteristic, comprising:

determining constraint time according to the circuit characteristics, wherein the constraint time represents that a third sequential device acquires a steady-state response signal at a second moment at least after the first moment, the first moment and the second moment are different by the constraint time, and the third sequential device represents a sequential device which is directly connected with a data signal input end of the synchronous processing module in the plurality of sequential devices;

and determining the delay time according to the constraint time.

11. The authentication method of claim 10, wherein determining the response time from the delay time comprises:

determining the processing delay corresponding to the synchronous processing module;

and determining the response time according to the processing delay and the delay time.

12. A verification method according to claim 11, wherein determining the response time from the processing delay and the delay time comprises:

determining that the response time is less than or equal to the sum of the processing delay and the delay time.

13. A verification method according to claim 12 wherein in response to the signal received by the third sequential device being a metastable signal,

determining the response time according to the processing delay and the delay time, wherein the determining comprises the following steps:

determining that the response time is less than or equal to a sum of the processing delay, the metastable delay, and the delay time.

14. A validation method according to claim 3 or 10, wherein the model construction process further comprises:

naming the simulation model according to the constraint time so that the naming of the simulation model corresponds to the constraint time.

15. A verification method according to claim 1 wherein adding the response model to a data link in the integrated circuit determined based on the first and second timing devices comprises:

and inserting the response model between the second sequential device and a device directly connected with the second sequential device, wherein the output end of the response model is directly connected with the data input end of the second sequential device.

16. The authentication method of claim 1, further comprising:

obtaining a circuit to be planned which passes the simulation verification, wherein the circuit to be planned comprises the plurality of asynchronous sequential device pairs;

executing planning processing on the circuit to be planned;

wherein the planning process comprises:

replacing at least one response model respectively corresponding to at least one asynchronous sequential device pair in the plurality of asynchronous sequential device pairs with a corresponding physical device, wherein the name of the physical device is the same as the name of the corresponding response model;

and acquiring a plurality of constraint times according to the naming of the physical device.

17. A validation method according to claim 16, wherein the planning process further comprises:

and performing layout and wiring optimization on the circuit to be planned according to the plurality of constraint times.

18. A validation method according to claim 16, wherein the planning process further comprises:

setting a virtual clock domain;

and setting timing constraints for a plurality of asynchronous sequential device pairs in the circuit to be planned according to the plurality of constraint times.

19. A method of validating as defined in claim 18, wherein setting a virtual clock domain comprises:

determining at least one virtual clock from the plurality of asynchronous sequential device pairs and the plurality of clock domains;

and aiming at each virtual clock, setting at least one timing path determined based on the plurality of asynchronous timing device pairs to belong to the same virtual clock domain, wherein the same virtual clock domain is determined based on each virtual clock.

20. A validation method according to claim 18, wherein the planning process further comprises:

and carrying out time sequence check on the plurality of asynchronous sequential device pairs according to the time sequence constraint set by the plurality of asynchronous sequential device pairs.

21. A verification method according to claim 1, wherein said meta-stable signal comprises a random signal and an indeterminate signal,

when the response model executes outputting the metastable state signal in the response time from the first moment, the method comprises the following operations:

acquiring a signal configuration parameter;

outputting one of the random signal or the indeterminate state signal within a response time from the first time in accordance with the signal configuration parameter.

22. An apparatus for verification of an integrated circuit, wherein the integrated circuit comprises a plurality of asynchronous clock domains,

the authentication apparatus includes:

the device comprises an acquisition unit, a first clock domain and a second clock domain, wherein the acquisition unit is configured to acquire a plurality of asynchronous sequential device pairs, each asynchronous sequential device pair comprises a first sequential device and a second sequential device, the first sequential device and the second sequential device are positioned in two different clock domains of the plurality of clock domains, and an electric signal transmission relationship exists between a data output end of the first sequential device and a data input end of the second sequential device;

the processing unit is configured to execute model construction processing on the integrated circuit according to the plurality of asynchronous sequential device pairs so as to obtain a circuit to be simulated;

the simulation verification unit is configured to perform front-end simulation verification on the circuit to be simulated;

wherein the model building process comprises:

for each asynchronous sequential device pair:

23. An electronic device, comprising:

a memory non-transiently storing computer executable instructions;

a processor configured to execute the computer-executable instructions,

wherein the computer-executable instructions, when executed by the processor, implement a method of validating an integrated circuit as claimed in any one of claims 1 to 21.

24. A non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer-executable instructions that, when executed by a processor, implement a method of verification of an integrated circuit according to any of claims 1-21.