CN114546908A - Bus bandwidth self-adaption unit, method and chip - Google Patents
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Abstract
The embodiment of the application provides a bus bandwidth self-adaptive unit, a method and a chip, wherein the bus bandwidth self-adaptive unit comprises: the monitoring subunit is used for monitoring each bus of the system on chip to obtain bus bandwidth use parameters of a device in the system on chip on at least one dimension; the comparison subunit is used for comparing the bus bandwidth use parameters in each dimension to obtain a comparison result; and the output subunit is used for carrying out bandwidth use adjustment on the bus bandwidth for the device based on the comparison result. By the embodiment of the application, the effectiveness of bus bandwidth allocation of the system on chip and the utilization rate of the bus bandwidth can be improved, bus bandwidth resources are saved, and bus power consumption is reduced.
Description
Technical Field
The embodiment of the application relates to the technical field of computers, in particular to a bus bandwidth self-adaption unit, a method and a chip.
Background
With the development of SoC technology, devices on chip with various functions may be integrated into one chip, and the connection between these devices on chip becomes the key for constructing SoC. And the on-chip bus effectively solves the connection between devices on the SoC in a bus mode and ensures the data communication between the devices.
Taking the AMBA bus as an example, which is a multi-bus system, many different types of buses can be used in combination, including: AHB (Advanced High-performance Bus), ASB (Advanced System Bus), AXI (Advanced eXtensible Interface), and APB (Advanced Peripheral Bus). Through the buses, communication between devices on chips with different functions can be effectively realized.
Currently, the bandwidth allocated by the on-chip bus for communication among the devices is fixed. However, in practical applications, actual bandwidths of different devices used for on-chip communication vary, and the bandwidths are often not fully utilized. Therefore, if the utilization rate of the bus bandwidth is increased, the bus bandwidth resource is saved, which becomes a problem to be solved urgently.
Disclosure of Invention
In view of the above, embodiments of the present application provide a bus bandwidth adaptive scheme to at least partially solve the above problems.
According to a first aspect of embodiments of the present application, there is provided a bus bandwidth adaptive unit, including: the monitoring subunit is used for monitoring each bus of the system on chip to obtain bus bandwidth use parameters of a device in the system on chip on at least one dimension; the comparison subunit is used for comparing the bus bandwidth use parameters in each dimension to obtain a comparison result; and the output subunit is used for carrying out bandwidth use adjustment on the bus bandwidth for the device based on the comparison result.
According to a second aspect of the embodiments of the present application, there is provided a bus bandwidth adaptive method, including: monitoring each bus of a system on chip to obtain bus bandwidth use parameters of a device in the system on chip on at least one dimension; for each dimension, comparing the bus bandwidth use parameters under the dimension to obtain a comparison result; based on the comparison, a bandwidth usage adjustment of the bus bandwidth is made for the device.
According to a third aspect of embodiments of the present application, there is provided a chip, at least comprising: a processor, a bus, a device on chip, and a bus bandwidth adaptation unit as described in the first aspect; wherein: the processor and the on-chip device are connected through the bus; the bus bandwidth adaptation unit is tightly coupled in the bus.
According to the bus bandwidth self-adaptive scheme provided by the embodiment of the application, the specific situations of devices in the system on chip when the bus is used are different, so that the devices can be monitored in real time to obtain bus bandwidth use parameters in one or more dimensions; further, under each dimensionality, comparing the bus bandwidth use parameters to obtain a comparison result; according to the comparison result, the specific situation of the current bus bandwidth used by the device can be determined, and whether and how to adjust the device accordingly can be further determined. The busy degree of the corresponding device for accessing the on-chip memory can be obtained through the bus bandwidth use parameter and the comparison result obtained based on the bus bandwidth use parameter; and the bandwidth use of the device is adjusted according to the comparison result, so that the self-adaptive adjustment and allocation of the bus bandwidth can be realized, the bus bandwidth can be effectively and fully utilized, the effectiveness of bus bandwidth allocation of the system on chip and the utilization rate of the bus bandwidth are improved, the bus bandwidth resource is saved, and the bus power consumption is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the embodiments of the present application, and other drawings can be obtained by those skilled in the art according to the drawings.
FIG. 1 is a schematic diagram of an AMBA bus system suitable for use with embodiments of the present application;
fig. 2A is a block diagram of a bus bandwidth adaptive unit according to a first embodiment of the present application;
FIG. 2B is a diagram illustrating an exemplary structure of a bus bandwidth adaptive unit in the embodiment shown in FIG. 2A;
FIG. 2C is a schematic diagram of a configuration of a bus bandwidth adaptive unit in the embodiment shown in FIG. 2A;
FIG. 3A is a flowchart illustrating steps of a bus bandwidth adaptation method according to a second embodiment of the present application;
FIG. 3B is a flowchart illustrating a specific example of bus bandwidth adaptation in the embodiment shown in FIG. 3A;
fig. 4 is a schematic structural diagram of a chip according to a third embodiment of the present application.
Detailed Description
In order to make those skilled in the art better understand the technical solutions in the embodiments of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, but not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application shall fall within the scope of the protection of the embodiments in the present application.
The following further describes specific implementations of embodiments of the present application with reference to the drawings of the embodiments of the present application.
Fig. 1 shows a schematic diagram of an AMBA bus system to which embodiments of the present application are applicable.
The AMBA (Advanced Microcontroller Bus Architecture) defines a communication standard of a high-performance embedded Microcontroller, which can integrate a RISC processor into other IP cores and peripherals, is a "digital glue" for effectively connecting the IP cores, is also an important component of an ARM multiplexing policy, and is an interface for communicating the ARM core with other elements on the chip.
An exemplary AMBA bus system is shown in fig. 1, which is comprised of a high performance backbone bus (AMBA AHB or AMBA ASB or AMBA AXI) capable of supporting external memory bandwidth, including processors, on-chip memory and other direct data access (DMA) devices, etc., shown as: a high performance ARM processor, a high performance AI accelerator, a DMA bus host, etc., and shows a high bandwidth external memory interface that supports on-chip memory. This bus provides a high bandwidth interface for data transfer between the devices. In addition, the bus is also provided with a bridge for connecting an APB with low bandwidth, and the APB is connected with most system peripherals, which are schematically shown as follows: UART, Keypad, Timer, and PIO.
Example one
Based on the bus system, a first embodiment of the present application provides a bus bandwidth adaptive unit, which is described below with reference to fig. 2A to 2C.
Fig. 2A shows a block diagram of a bus bandwidth adaptation unit according to a first embodiment of the present application, where the bus bandwidth adaptation unit includes: a monitoring subunit 102, a comparison subunit 104, and an output subunit 106.
Wherein:
the monitoring subunit 102 is configured to monitor each bus of the system on chip, and obtain a bus bandwidth usage parameter of a device in the system on chip in at least one dimension. In the embodiment of the present application, the bus mainly refers to a high bandwidth bus, such as AMBA AHB, AMBA ASB, or AMBA AXI; the devices primarily include devices with bus bandwidth usage gaps including, but not limited to, video codecs, GPUs, AI accelerators, DSPs, and the like. Bus bandwidth usage for different devices may be obtained from different dimensions, e.g. for video codecs it may be mainly from the frame dimension considerations, while for other devices or bandwidth occupation of multiple devices including video codecs it may also be obtained from dimensions such as QoS (Quality of Service), backpressure conditions for bus entries, etc.
In the embodiments of the present application, the numbers "plural" and "plural" relating to "plural" mean two or more unless otherwise specified.
In one possible approach, the at least one dimension includes: part or all of the bus entrance backpressure dimension, the frame storage dimension and the QoS analysis dimension; correspondingly, the bus bandwidth usage parameters include part or all of the bus entrance backpressure proportion, the frame margin, and the QoS resolution request quantity. Through the dimensions and the parameters, the use condition of the bus bandwidth can be effectively evaluated.
Generally, the higher the bus entrance backpressure ratio, the higher the data transmission requirement of the corresponding device, and the current bandwidth allocation may not meet the requirement; the frame margin can reflect whether the bandwidth of the corresponding device has redundancy, and the larger the frame margin is, the more the redundancy is likely to exist, or the more the redundancy is likely to exist; the QoS resolution request also occupies a bandwidth, and when the number of the QoS resolution request increases, the QoS resolution request may occupy resources excessively and needs to be distinguished and processed based on the urgency degree of the QoS resolution request.
And a comparing subunit 104, configured to, for each dimension, compare the bus bandwidth usage parameters in the dimension to obtain a comparison result.
The dimensions are different, and the specific comparison mode may be different. For example, for the bus inlet backpressure dimension, whether the bus inlet backpressure ratio is higher than a certain high threshold (first ratio threshold) or lower than a certain low threshold (second ratio threshold) may be compared, where the high threshold or the low threshold may be flexibly set by a person skilled in the art according to actual needs, and the embodiment of the present application is not limited thereto. For example, the high threshold may be 20%, the low threshold may be 1% -0%, etc.
For another example, for the frame storage dimension, it may also be compared whether the frame storage remaining amount is lower than a certain low threshold (first remaining amount threshold) or higher than a certain high threshold (second remaining amount threshold), and similarly, the high threshold or the low threshold may be flexibly set by a person skilled in the art according to actual needs, which is not limited by the embodiment of the present application. For example, the high threshold may be 2, the low threshold may be 1, and so on.
For another example, for the QoS resolution dimension, when the number of QoS resolution requests is less than or equal to a certain number threshold, the QoS resolution dimension may be processed conventionally, and if the number of QoS resolution requests is greater than the number threshold, the QoS resolution dimension needs to be processed subsequently in the embodiment of the present application.
And the output subunit 106 is configured to perform bandwidth usage adjustment of the bus bandwidth for the device based on the comparison result.
After the comparison results of the dimensions are obtained, corresponding adjustment processing can be performed based on the comparison results. For example, if the bus entry backpressure ratio is higher than the first ratio threshold, more bandwidth resources can be allocated to the corresponding device, and conversely, if the bus entry backpressure ratio is lower than or equal to the second ratio threshold, bandwidth resource deprivation can be performed on the corresponding device. For another example, if the frame remaining amount is higher than the second remaining amount threshold, bandwidth resource deprivation may be performed on the corresponding device; if the frame remaining capacity is lower than the first remaining capacity threshold, more bandwidth resources can be allocated for the corresponding device. For another example, if the number of QoS resolution requests is less than or equal to a certain number threshold, the QoS resolution requests may be processed as usual, and if the number of QoS resolution requests is greater than the number threshold, the QoS resolution requests may be prioritized according to their urgency, and bandwidth resources may be allocated for the QoS resolution requests according to the determined priority for processing. For example, the bandwidth resource is allocated to the QoS resolution request with the highest priority for processing, or the bandwidth resource is allocated to a small number of QoS resolution requests with the priority of TOP N for processing. N is a positive integer, and the specific value of N can be set by those skilled in the art according to actual needs, and exemplarily, N can be 2 or 3.
In one possible approach, the output subunit 106 may be configured to perform at least one of the following bandwidth usage adjustments of the bus bandwidth for the device based on the comparison: adjustment of device clock frequency, gear adjustment of advance transmission (outranging transmission of AXI bus). The bus bandwidth represents the total amount of data that can be transmitted by the bus in a unit time and can be determined by the product of the bit width of the bus and the working frequency. Based on this, the bandwidth of the device can be effectively used and adjusted by adjusting the clock frequency and/or the outrating gear of the device.
Based on the bus bandwidth self-adapting unit, the specific situations of devices in the system on chip when using the bus are different, so that the devices can be monitored in real time to obtain bus bandwidth use parameters in one or more dimensions; further, under each dimensionality, comparing the bus bandwidth use parameters to obtain a comparison result; according to the comparison result, the specific situation of the current bus bandwidth used by the device can be determined, and whether and how to adjust the device accordingly can be further determined. The busy degree of the corresponding device for accessing the on-chip memory can be obtained through the bus bandwidth use parameter and the comparison result obtained based on the bus bandwidth use parameter; and the bandwidth use of the device is adjusted according to the comparison result, so that the self-adaptive adjustment and allocation of the bus bandwidth can be realized, the bus bandwidth can be effectively and fully utilized, the effectiveness of bus bandwidth allocation of the system on chip and the utilization rate of the bus bandwidth are improved, the bus bandwidth resource is saved, and the bus power consumption is reduced.
However, in order to make the adjustment more accurate, in a feasible manner, a policy configuration interface may also be provided. That is, the bus bandwidth adaptation unit may further include: a policy configuration interface 108, configured to obtain a bus bandwidth usage parameter of the monitoring subunit 102 and/or a comparison result of the comparing subunit 104; and determining a bandwidth use adjustment strategy of the bus bandwidth according to the bus bandwidth use parameter and/or the comparison result. Based on this, the output subunit 106 may be configured to perform bandwidth usage adjustment of the bus bandwidth for the device according to the bandwidth usage adjustment policy. In this way, the policy configuration interface 108 may preset a corresponding adjustment policy, and after obtaining the bus bandwidth usage parameter and/or the comparison result, match the bus bandwidth usage parameter with the preset adjustment policy, and determine a matching adjustment policy. The preset adjustment policy may include, but is not limited to, the adjustment manner for adjusting the bus bandwidth based on the comparison result by the output subunit 106. Therefore, on one hand, the policy configuration interface 108 performs policy matching, which reduces the processing burden of the output subunit 106 and simplifies the specific technical implementation; on the other hand, more needed adjustment strategies can be preset in the strategy configuration interface 108 according to needs, and the set adjustment strategies can be updated more conveniently, so that the bus bandwidth adaptive unit has more flexibility, and the bandwidth adjustment efficiency is also improved.
Optionally, the policy configuration interface 108 may determine the bandwidth usage adjustment policy of the bus bandwidth through a preset reinforcement learning machine model according to the bus bandwidth usage parameter and/or the comparison result. The reinforcement machine learning model may be any machine learning model that takes bus bandwidth usage parameters and/or comparison results as inputs and takes an adjustment policy as an output. Illustratively, the reinforcement machine learning model may be a policy evaluation model. Further optionally, the policy evaluation model may be a KB-Tree based policy evaluation model to achieve more precise policy selection.
An exemplary bus bandwidth adaptation unit as described above is shown in fig. 2B, where it can be seen that the monitor subunit 102 monitors a plurality of buses, each having at least one on-chip device. The comparison subunit 104 performs comparison and generates a comparison result based on the product line bandwidth usage parameters of the on-chip devices in each dimension monitored by the monitoring subunit 102. In fig. 2B, the monitoring result of the monitoring subunit 102 and the comparison result of the comparing subunit 104 are both transmitted to the policy configuration interface 108, the policy configuration interface 108 determines the adaptive bandwidth usage adjustment policy, and then issues the bandwidth usage adjustment policy to the output subunit 106, and the output subunit 106 adjusts the bandwidth usage of each device. This adjustment is illustrated in fig. 2B as an adjustment of the clock frequency of each device and an adjustment of the outgoing gear based on the AXI bus.
In the specific adjustment, an adjustment step length may be set, and the specific step length setting may be flexibly set by a person skilled in the art according to actual needs, which is not limited in the embodiment of the present application. For example, the adjustment step of the clock frequency may be 1-10MHz, and the adjustment step of outranging may be one step at a time (the outranging capability N is adjusted up one step or down one step, i.e., N +1 or N-1). Of course, the above is merely exemplary, and other step size values may be set in specific uses.
When the setting of the bus bandwidth adaptive unit is specifically performed, as shown in fig. 2C, the setting may be coupled with a bus of the system on chip. In FIG. 2C, the bus is connected to on-chip devices, including but not limited to: memory controller, CPU, GPU, VDEC (video decoder), Disp (display unit). In this example, the bus monitors the data transmission of each device on the bus by the bus bandwidth adaptive unit coupled thereto, and performs the processing and adjustment as described above based on the monitoring result. In a preferred embodiment, the bus bandwidth adaptation unit may be tightly coupled to the bus of the system on chip to better serve the bus.
Hereinafter, the bandwidth usage adjustment procedure of the bus bandwidth adaptation unit will be described by taking an on-chip device as an example of a multimedia processing device (such as a video decoder).
When the on-chip device is a multimedia processing device, the bus bandwidth usage parameter at least includes a frame margin, and in this way, the frame margin means that the video decoder completes a difference between the frame margin (the number of video frames in the memory) and the frame margin of the display unit.
Based on this, the monitoring subunit 102 monitors the bus bandwidth usage parameter of the multimedia processing device when using the bus to perform video frame processing, including the video decoder completing frame storage and display unit frame storage, and obtains the frame storage amount of the multimedia processing device based on this; the comparing subunit 104 compares the frame remaining amount with a preset threshold (e.g. the aforementioned first remaining amount threshold and the second remaining amount threshold) to obtain a comparison result; the output sub-unit 106 adjusts the bandwidth usage of the bus bandwidth for the multimedia processing device according to the comparison result. For example, if the comparison result indicates that the frame storage margin is less than the first margin threshold, the data transmission capability of the multimedia processing device is increased, such as increasing the clock frequency of the multimedia processing device, and/or, in the case of using the AXI bus, the transmission gear of outranging is increased. And if the comparison result indicates that the frame storage margin is greater than the second margin threshold, reducing the data transmission capability of the multimedia processing device, and/or reducing the transmission gear of the outranging under the condition of using the AXI bus.
Because the multimedia processing device, such as a video decoder, has a corresponding data transmission gap, the bandwidth utilization of the multimedia processing device is adjusted based on the bandwidth utilization, and the idle bus resource of the multimedia processing device can be adjusted to be used by other on-chip devices, so that the bus resource of the system on chip is fully utilized, and the overall data transmission and processing efficiency of the system on chip is improved.
Example two
Referring to fig. 3A, a flowchart illustrating steps of a bus bandwidth adaptation method according to a second embodiment of the present application is shown.
The bus bandwidth adaptive method of this embodiment can be implemented by the foregoing bus bandwidth adaptive unit, and the method includes the following steps:
step S202: and monitoring each bus of the system on chip to obtain the bus bandwidth use parameters of the device in the system on chip in at least one dimension.
In one possible approach, the at least one dimension includes: some or all of the bus entry backpressure dimension, the frame storage dimension, the QoS resolution dimension. Correspondingly, the bus bandwidth usage parameters include part or all of the bus entrance backpressure proportion, the frame margin, and the QoS resolution request quantity.
And when the device is a multimedia processing device, the frame storage allowance is the difference value between the frame storage finished by the video decoder and the frame storage of the display unit.
Step S204: and aiming at each dimension, comparing the bus bandwidth use parameters under the dimension to obtain a comparison result.
For example, for the bus inlet backpressure dimension, whether the bus inlet backpressure ratio is higher than a certain high threshold (first ratio threshold) or lower than a certain low threshold (second ratio threshold) may be compared, where the high threshold or the low threshold may be flexibly set by a person skilled in the art according to actual needs, and the embodiment of the present application is not limited thereto. For example, the high threshold may be 20%, the low threshold may be 1% -0%, etc.
For another example, for the frame storage dimension, it may also be compared whether the frame storage remaining amount is higher than a certain high threshold (second remaining amount threshold) or lower than a certain low threshold (first remaining amount threshold), and similarly, the high threshold or the low threshold may be flexibly set by a person skilled in the art according to actual needs, which is not limited by the embodiment of the present application. For example, the high threshold may be 2, the low threshold may be 1, and so on.
For another example, for the QoS resolution dimension, when the number of QoS resolution requests is less than or equal to a certain number threshold, the QoS resolution dimension may be processed conventionally, and if the number of QoS resolution requests is greater than the number threshold, the QoS resolution dimension needs to be processed subsequently in the embodiment of the present application.
Step S206: based on the comparison, a bandwidth usage adjustment of the bus bandwidth is made for the device.
Wherein the bandwidth usage adjustment comprises at least one of: adjusting the clock frequency of the device, and adjusting the gear of the advance transmission.
In one possible approach, to make the adjustment more accurate, this step can be implemented as: inputting the bus bandwidth use parameters and/or the comparison result into the reinforcement learning machine model through a strategy configuration interface to obtain a bandwidth use adjustment strategy output by the reinforcement learning machine model; and according to the bandwidth use adjustment strategy, carrying out bandwidth use adjustment on the bus bandwidth for the device.
In the following, the above process is exemplified by taking the device as a multimedia processing device as an example, in this example, the multimedia processing device is specifically exemplified as a video decoder VDEC, but it should be understood by those skilled in the art that other devices such as a GPU, an AI accelerator, a DSP, etc. can be also applied to this example.
As shown in fig. 3B, the bandwidth adjustment procedure for VDEC in this example specifically includes:
process A: and monitoring the frame storage information of the VDEC to obtain the frame storage margin.
For example, the difference between the VDEC complete frame memory and the display unit frame memory, i.e., VDEC frame memory-Disp frame memory, may be obtained through monitoring by the monitoring subunit 102.
And a process B: judging whether the frame storage allowance is smaller than a first allowance threshold value or not; if yes, executing the process C; if not, then process D is performed.
In this example, the first margin threshold is set to 1, which is illustrated in the figure as determining that the VDEC frame is stored — Disp frame is stored < 1.
And a process C: the data transmission capability of the VDEC is improved. And returning to the process A.
E.g. increasing the clock frequency of the VDEC and/or increasing the gear of the outrating.
The process D is as follows: judging whether the frame storage allowance is larger than a second allowance threshold value or not; if yes, executing procedure E; if not, then process F is performed.
In this example, the second margin threshold is set to 2, which is illustrated in the figure as determining that the VDEC frame is stored — Disp frame is stored > 2. In this case, it is indicated that the video decoding frame is ahead, and the data transmission capability of the VDEC can be reduced.
The process E: the data transmission capability of the VDEC is reduced. And returning to the process A.
E.g. to reduce the clock frequency of the VDEC and/or to lower the output gear.
The process F: no adjustment is made to the data transfer capabilities of the VDEC and the process returns to procedure a.
By the embodiment, the specific situation of a device in the system on chip when the bus is used is monitored in real time, and the bus bandwidth use parameters on one or more dimensions are obtained; further, under each dimensionality, comparing the bus bandwidth use parameters to obtain a comparison result; according to the comparison result, the specific situation of the current bus bandwidth used by the device can be determined, and whether and how to adjust the device accordingly can be further determined. The busy degree of the corresponding device for accessing the on-chip memory can be obtained through the bus bandwidth use parameter and the comparison result obtained based on the bus bandwidth use parameter; and the bandwidth use of the device is adjusted according to the comparison result, so that the self-adaptive adjustment and allocation of the bus bandwidth can be realized, the bus bandwidth can be effectively and fully utilized, the effectiveness of bus bandwidth allocation of the system on chip and the utilization rate of the bus bandwidth are improved, the bus bandwidth resource is saved, and the bus power consumption is reduced.
EXAMPLE III
Referring to fig. 4, a schematic structural diagram of a chip according to a third embodiment of the present application is shown.
The chip in this embodiment includes at least: a processor, a bus, an on-chip device, and the bus bandwidth adaptive unit described in the first embodiment; wherein: the processor and the on-chip device are connected through the bus; a bus bandwidth adaptation unit is tightly coupled in the bus.
In a specific example, as shown in fig. 4, the chip is based on an AMBA bus structure, which includes the bus bandwidth adaptation unit described in the first embodiment above, in addition to the high performance hub bus, the processor, the on-chip memory interface (high bandwidth external memory interface, for accessing on-chip memory), the high performance AI accelerator, the DMA, the bridge, and the APB as shown in fig. 1.
As can be seen in the figure, the bus bandwidth adaptation unit is tightly coupled in the AMBA bus.
Therefore, in the chip of the embodiment, in the process that each on-chip device transmits data through the bus, the use condition of the bus bandwidth can be monitored in real time, and the use of the bandwidth of the device can be adjusted in time, so that the bus bandwidth can be effectively and fully utilized, the effectiveness of bus bandwidth allocation of the on-chip system and the utilization rate of the bus bandwidth are improved, the bus bandwidth resource is saved, and the bus power consumption is reduced.
It should be noted that, according to the implementation requirement, each component/step described in the embodiment of the present application may be divided into more components/steps, and two or more components/steps or partial operations of the components/steps may also be combined into a new component/step to achieve the purpose of the embodiment of the present application.
Those of ordinary skill in the art will appreciate that the various illustrative elements and method steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the embodiments of the present application.
The above embodiments are only used for illustrating the embodiments of the present application, and not for limiting the embodiments of the present application, and those skilled in the relevant art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present application, so that all equivalent technical solutions also belong to the scope of the embodiments of the present application, and the scope of patent protection of the embodiments of the present application should be defined by the claims.
Claims (14)
1. A bus bandwidth adaptation unit, comprising:
the monitoring subunit is used for monitoring each bus of the system on chip to obtain bus bandwidth use parameters of a device in the system on chip in at least one dimension;
the comparison subunit is used for comparing the bus bandwidth use parameters in each dimension to obtain a comparison result;
and the output subunit is used for carrying out bandwidth use adjustment on the bus bandwidth for the device based on the comparison result.
2. The bus bandwidth adaptation unit of claim 1,
the at least one dimension includes: part or all of the bus entrance backpressure dimension, the frame storage dimension and the QoS analysis dimension;
correspondingly, the bus bandwidth usage parameters include part or all of the bus entrance backpressure proportion, the frame margin, and the QoS resolution request quantity.
3. The bus bandwidth adaptation unit of claim 1 or 2,
the output subunit is configured to perform at least one of the following bandwidth usage adjustments of the bus bandwidth for the device based on the comparison result: adjusting the clock frequency of the device, and adjusting the gear of the advance transmission.
4. The bus bandwidth adaptation unit according to claim 1 or 2, wherein the bus bandwidth adaptation unit further comprises:
the strategy configuration interface is used for acquiring the bus bandwidth use parameters of the monitoring subunit and/or the comparison result of the comparison subunit; determining a bandwidth use adjustment strategy of the bus bandwidth according to the bus bandwidth use parameter and/or the comparison result;
and the output subunit is configured to perform bandwidth usage adjustment of the bus bandwidth for the device according to the bandwidth usage adjustment policy.
5. The bus bandwidth adaptation unit according to claim 4, wherein the policy configuration interface determines the bandwidth usage adjustment policy of the bus bandwidth through a preset reinforcement learning machine model according to the bus bandwidth usage parameter and/or the comparison result.
6. The bus bandwidth adaptation unit of claim 2, wherein the device is a multimedia processing device; and the frame storage allowance is the difference value between the frame storage finished by the video decoder and the frame storage of the display unit.
7. The bus bandwidth adaptation unit of claim 6, wherein, for the multimedia processing device:
the monitoring subunit at least obtains a frame margin of the multimedia processing device; the comparison subunit compares the frame storage allowance with a preset threshold value to obtain a comparison result; and the output subunit is used for adjusting the bandwidth use of the bus bandwidth of the multimedia processing device according to the comparison result.
8. The bus bandwidth adaptation unit of claim 1, wherein the bus bandwidth adaptation unit is tightly coupled in the bus; the bus is an AMBA bus.
9. A method of bus bandwidth adaptation, comprising:
monitoring each bus of a system on chip to obtain bus bandwidth use parameters of a device in the system on chip on at least one dimension;
for each dimension, comparing the bus bandwidth use parameters under the dimension to obtain a comparison result;
based on the comparison, a bandwidth usage adjustment of the bus bandwidth is made for the device.
10. The method of claim 9, wherein said performing a bandwidth usage adjustment of a bus bandwidth for the device based on the comparison comprises:
inputting the bus bandwidth use parameters and/or the comparison result into a reinforcement learning machine model through a strategy configuration interface to obtain a bandwidth use adjustment strategy output by the reinforcement learning machine model;
and according to the bandwidth use adjustment strategy, carrying out bandwidth use adjustment on the bus bandwidth for the device.
11. The method of claim 9 or 10,
the at least one dimension includes: part or all of the bus entrance backpressure dimension, the frame storage dimension and the QoS analysis dimension;
correspondingly, the bus bandwidth usage parameters include part or all of the bus entrance backpressure proportion, the frame margin, and the QoS resolution request quantity.
12. The method of claim 11, wherein the device is a multimedia processing device; and the frame storage allowance is the difference value between the frame storage finished by the video decoder and the frame storage of the display unit.
13. The method of claim 12, wherein for each dimension, the bus bandwidth usage parameter for the dimension is compared to obtain a comparison result; based on the comparison, performing bandwidth usage adjustment of bus bandwidth for the device, comprising:
comparing, for the multimedia processing device, the frame stock level to a first stock level threshold or a second stock level threshold, wherein the first stock level threshold is less than the second stock level threshold;
if the frame storage margin is determined to be smaller than the first margin threshold, improving the data transmission capability of the multimedia processing device;
if the frame memory margin is determined to be larger than the second margin threshold, reducing the data transmission capability of the multimedia processing device;
if the frame storage allowance is determined to be larger than or equal to the first allowance threshold and smaller than or equal to the second allowance threshold, the data transmission of the multimedia processing device is not adjusted.
14. A chip, comprising at least: a processor, a bus, a device on chip, and a bus bandwidth adaptation unit as claimed in any one of claims 1-8;
wherein:
the processor and the on-chip device are connected through the bus; the bus bandwidth adaptation unit is tightly coupled in the bus.
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