CN114546654A - Method and device for calling CPUs (central processing units) among different architectures and interconnection equipment - Google Patents
Method and device for calling CPUs (central processing units) among different architectures and interconnection equipment Download PDFInfo
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- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
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- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
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Abstract
The application discloses a method, a device, an interconnection device and a readable storage medium for CPU calling among different architectures, wherein the method comprises the following steps: receiving calling information input by a first CPU; determining a called second CPU and a corresponding calling requirement according to the calling information; transmitting the call requirement to a fixed memory corresponding to a second CPU (central processing unit) so that the fixed memory triggers inter-core interruption, and responding to the inter-core interruption by the second CPU to execute the call requirement; the method and the device realize the sharing of the CPU computing power among different architectures, further improve the resource expansion capability of the system, and greatly improve the cost performance of the server and the competitiveness of products. The application also provides a device for CPU calling among different architectures, interconnection equipment and a readable storage medium, and the beneficial effects are achieved.
Description
Technical Field
The present application relates to the field of CPU invocation, and in particular, to a method and an apparatus for CPU invocation between different architectures, an interconnection device, and a readable storage medium.
Background
In modern systems, SMP (symmetric Multi-Processing) is a computer architecture that integrates a set of processors (Multi-CPU) on a computer, and the CPUs share memory sub-devices and bus structures, and is currently the most widely used one. Symmetric multiprocessing is realized on different CPU platforms, the realization scheme of each platform is different, the unification of CPU and memory, IO (Input/Output) and interrupt resources is mainly completed, the access of the resources is mainly realized through an interconnection bus, and the scheduling among the resources is mainly realized through an interrupt mechanism. However, each platform has its own implementation protocol, and the protocols are incompatible with each other, so that CPUs of different architectures cannot be interconnected, so that the expansion and development of a multi-path device is hindered, and further research and development of multi-path systems such as large-scale machines and small-scale machines in China are seriously affected.
Therefore, how to implement interconnection between CPUs of different architectures is a technical problem that needs to be solved by those skilled in the art at present.
Disclosure of Invention
The application aims to provide a method, a device, an interconnection device and a readable storage medium for calling CPUs (central processing units) of different architectures, which are used for realizing interconnection among CPUs of different architectures.
In order to solve the above technical problem, the present application provides a method for CPU invocation between different architectures, which is applied to an interconnection device, and the method includes:
receiving calling information input by a first CPU;
determining a called second CPU and a corresponding calling requirement according to the calling information;
transmitting the calling requirement to a fixed memory corresponding to the second CPU, so that the fixed memory triggers inter-core interruption, and the second CPU responds to the inter-core interruption to execute the calling requirement;
the first CPU and the second CPU are provided with CXL interfaces, and the interconnection equipment is communicated with the first CPU and the second CPU respectively through a CXL protocol.
Optionally, the method further includes:
receiving an access request input by the first CPU, and determining an accessed third CPU according to the access request;
converting the access request into a consistent memory access request through protocol conversion, and sending the consistent memory access request to the third CPU, so that the third CPU executes the consistent memory access request and returns a corresponding consistent memory result;
sending the consistent memory result to the first CPU;
wherein the third CPU has the CXL interface, and the interconnect device communicates with the third CPU through the CXL protocol.
Optionally, determining the accessed third CPU according to the access request includes:
analyzing the access request to obtain a corresponding address resource;
and determining the third CPU corresponding to the address resource according to a preset corresponding relation table.
Optionally, before parsing the access request to obtain the corresponding address resource, the method further includes:
allocating corresponding address resources for each CPU according to the input address allocation request;
and establishing the preset corresponding relation table according to the corresponding relation between each CPU and the address resource.
The present application further provides a device for CPU invocation between different architectures, the device comprising:
the first receiving module is used for receiving calling information input by the first CPU;
the determining module is used for determining the called second CPU and the corresponding calling requirement according to the calling information;
the transmission module is used for transmitting the calling requirement to a fixed memory corresponding to the second CPU so that the fixed memory triggers inter-core interruption, and the second CPU responds to the inter-core interruption to execute the calling requirement;
the first CPU and the second CPU are provided with CXL interfaces, and the interconnection equipment is communicated with the first CPU and the second CPU respectively through a CXL protocol.
Optionally, the apparatus further comprises:
the second receiving module is used for receiving an access request input by the first CPU and determining an accessed third CPU according to the access request;
the conversion module is used for converting the access request into a consistent memory access request through protocol conversion and sending the consistent memory access request to the third CPU so that the third CPU executes the consistent memory access request and returns a corresponding consistent memory result;
a sending module, configured to send the consistent memory result to the first CPU;
wherein the third CPU has the CXL interface, and the interconnect device communicates with the third CPU through the CXL protocol.
Optionally, the second receiving module includes:
the analysis submodule is used for analyzing the access request to obtain a corresponding address resource;
and the determining submodule is used for determining the third CPU corresponding to the address resource according to a preset corresponding relation table.
Optionally, the second receiving module further includes:
the distribution submodule is used for distributing corresponding address resources for each CPU according to the input address distribution request;
and the establishing submodule is used for establishing the preset corresponding relation table according to the corresponding relation between each CPU and the address resource.
The present application further provides an interconnection device, including:
a memory for storing a computer program;
a processor for implementing the steps of the method for CPU invocation between different architectures as described in any of the above when said computer program is executed.
The present application also provides a readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the method for CPU invocation between different architectures as described in any of the above.
The method for CPU calling among different architectures, provided by the application, is applied to interconnection equipment, and comprises the following steps: receiving calling information input by a first CPU; determining a called second CPU and a corresponding calling requirement according to the calling information; transmitting the call requirement to a fixed memory corresponding to a second CPU (central processing unit) so that the fixed memory triggers inter-core interruption, and responding to the inter-core interruption by the second CPU to execute the call requirement; the first CPU and the second CPU are provided with CXL interfaces, and the interconnection equipment is communicated with the first CPU and the second CPU respectively through CXL protocols.
According to the technical scheme, the interconnection equipment is respectively communicated with the first CPU and the second CPU according to the CXL protocol, the calling requirement is transmitted to the fixed memory corresponding to the second CPU when the calling information input by the first CPU is received, so that the fixed memory triggers the inter-core interruption, the second CPU responds to the inter-core interruption to execute the calling requirement, the sharing of the CPU computing capacity among different architectures is realized, the resource expansion capacity of the system is improved, and the cost performance of the server and the competitiveness of products are greatly improved. The application also provides a device for CPU calling among different architectures, interconnection equipment and a readable storage medium, which have the beneficial effects and are not described herein again.
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In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a flowchart of a method for CPU invocation between different architectures according to an embodiment of the present application;
FIG. 2 is a block diagram of a prior art interconnection of multiple servers;
fig. 3 is a block diagram illustrating an interconnection of multiple servers according to an embodiment of the present disclosure;
FIG. 4 is a flowchart of a method for CPU invocation between different architectures provided by embodiments of the present application;
FIG. 5 is a block diagram of an apparatus for CPU invocation between different architectures according to an embodiment of the present application;
fig. 6 is a structural diagram of an interconnection device according to an embodiment of the present application.
Detailed Description
The core of the application is to provide a method, a device, an interconnection device and a readable storage medium for calling CPUs in different architectures, which are used for realizing interconnection among CPUs in different architectures.
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, fig. 1 is a flowchart of a method for CPU invocation between different architectures according to an embodiment of the present application.
The method is applied to interconnection equipment and specifically comprises the following steps:
s101: and receiving the calling information input by the first CPU.
In modern systems, symmetric multiprocessing is a computer architecture in which a set of processors (multiple CPUs) are collected on a computer, and memory sub-devices and bus structures are shared among the CPUs. Symmetric multiprocessing is realized on different CPU platforms, the realization scheme of each platform is different, the unification of CPU and memory as well as IO and interrupt resources is mainly completed, the access of the resources is mainly realized through an interconnection bus, and the scheduling among the resources is mainly realized through an interrupt mechanism. However, each platform has its own implementation protocol, and the protocols are incompatible with each other, so that CPUs of different architectures cannot be interconnected, so that the expansion and development of a multi-path device is hindered, and further research and development of multi-path systems such as large-scale machines and small-scale machines in China are seriously affected.
Taking intel (intel) multi-path interconnection system as an example for explanation, please refer to fig. 2, fig. 2 is a multi-path server interconnection block diagram in the prior art, and as shown in fig. 2, it can be seen that in the prior art, interconnection of CPUs is mainly realized through intel QPI (QuickPath Interconnect, high speed Interconnect bus), resource sharing between CPUs is mainly transmitted through QPI protocol, in the case of the prior art, at most, the method can only be extended to 8-path system, and the method cannot realize interconnection between CPUs of different architectures, so the present application provides a method for calling CPUs between different architectures, which is used for solving the above problems.
S102: and determining the called second CPU and the corresponding calling requirement according to the calling information.
The first CPU and the second CPU mentioned here have CXL (computer Express Link) interfaces, the interconnect device communicates with the first CPU and the second CPU respectively through CXL protocol, which is a new standard for open interconnect, and intensive workloads facing CPU and dedicated accelerator, which all need to realize efficient and stable memory access between the host and the device. The CXL standard eliminates some of these limitations by providing an interface that utilizes the PCIe (peripheral component interconnect express) 5.0 physical layer and electrical components, while providing an extremely low latency path for memory access and coherent caching between the host processor and devices that require shared memory resources (e.g., accelerators and memory expanders), which can greatly increase the speed of calls between CPUs.
S103: and transmitting the call requirement to a fixed memory corresponding to the second CPU so that the fixed memory triggers inter-core interrupt, and responding to the inter-core interrupt by the second CPU to execute the call requirement.
Because the CXL does not implement the data type of the IPI (Inter-Processor Interrupt), and cannot implement the CPU call requirement in the interconnected system, the call requirement is transmitted to the fixed memory corresponding to the second CPU in this step, so that the fixed memory triggers the Inter-core Interrupt, the second CPU responds to the Inter-core Interrupt to execute the call requirement, that is, the requirement transmission is performed by writing the fixed memory, the interconnected chip receives the requirement, and forwards the requirement according to the mode of transferring the memory, and the corresponding CPU receives the requirement and writes the requirement into the memory which can cause the IPI Interrupt, thereby implementing the function of the CPU call requirement.
In a specific embodiment, please refer to fig. 3, and fig. 3 is an interconnection block diagram of a multi-server provided in the embodiment of the present application, as shown in fig. 3, in the present application, an interconnection device is configured to communicate with each CPU according to a CXL protocol, and it can be seen in the diagram that resource sharing between CPUs is mainly performed by implementing transmission of the interconnection device of the CXL, so that sharing of CPU computing power between different architectures is implemented, and further resource expansion capability of a system is improved, and cost performance of a server and competitiveness of a product are greatly improved.
Based on the technical scheme, the method for calling the CPUs between the different architectures, provided by the application, is respectively communicated with the first CPU and the second CPU through the interconnection equipment according to the CXL protocol, when the calling information input by the first CPU is received, the calling requirement is transmitted to the fixed memory corresponding to the second CPU, so that the fixed memory triggers inter-core interruption, the second CPU responds to the inter-core interruption to execute the calling requirement, the sharing of the CPU computing capacity between the different architectures is realized, the resource expansion capacity of the system is further improved, and the cost performance of the server and the competitiveness of the product are greatly improved.
Based on the foregoing embodiments, in a specific embodiment, a CPI may also be implemented to access memory data of another CPU through the interconnect device, and specifically may be implemented by executing the steps shown in fig. 4, which is described below with reference to fig. 4.
Referring to fig. 4, fig. 4 is a flowchart of another method for CPU invocation between different architectures according to the present application.
The method is applied to interconnection equipment and specifically comprises the following steps:
s401: and receiving an access request input by the first CPU, and determining an accessed third CPU according to the access request.
The third CPU mentioned here has a CXL interface, and the interconnect device communicates with the third CPU through the CXL protocol;
in a specific embodiment, each CPU has an assigned address range in the interconnect device, so that memory accesses between CPUs can be accessed through the address range of each CPU, that is, the third CPU determined to be accessed according to an access request mentioned herein may specifically be:
analyzing the access request to obtain a corresponding address resource;
and determining a third CPU corresponding to the address resource according to the preset corresponding relation table.
On the basis of the foregoing embodiment, in a specific embodiment, before analyzing the access request to obtain the corresponding address resource, the following steps may be further performed to establish the preset correspondence table:
allocating corresponding address resources for each CPU according to the input address allocation request;
and establishing a preset corresponding relation table according to the corresponding relation between each CPU and the address resource.
S402: and converting the access request into a consistent memory access request through protocol conversion, and sending the consistent memory access request to the third CPU, so that the third CPU executes the consistent memory access request and returns a corresponding consistent memory result.
S403: and sending the consistent memory result to the first CPU.
Based on the technical scheme, according to another method for calling CPUs between different architectures, an access request is converted into a consistent memory access request through protocol conversion, and the consistent memory access request is sent to a third CPU, so that the third CPU executes the consistent memory access request and returns a corresponding consistent memory result, a CXL protocol is used for replacing private protocols such as QPI, memory access between different CPUs is realized through protocol conversion, memory sharing is further realized, and the resource expansion capability of a system is further improved.
Referring to fig. 5, fig. 5 is a structural diagram of a device for CPU call between different architectures according to an embodiment of the present application.
The apparatus may include:
a first receiving module 100, configured to receive call information input by a first CPU;
a determining module 200, configured to determine, according to the call information, a called second CPU and a corresponding call requirement;
the transmission module 300 is configured to transmit the call request to a fixed memory corresponding to the second CPU, so that the fixed memory triggers inter-core interrupt, and the second CPU responds to the inter-core interrupt to execute the call request;
the first CPU and the second CPU are provided with CXL interfaces, and the interconnection equipment is communicated with the first CPU and the second CPU respectively through CXL protocols.
On the basis of the above embodiment, in a specific embodiment, the apparatus may further include:
the second receiving module is used for receiving the access request input by the first CPU and determining an accessed third CPU according to the access request;
the conversion module is used for converting the access request into a consistent memory access request through protocol conversion and sending the consistent memory access request to the third CPU so that the third CPU executes the consistent memory access request and returns a corresponding consistent memory result;
the sending module is used for sending the consistent memory result to the first CPU;
wherein the third CPU has a CXL interface, and the interconnect device communicates with the third CPU via a CXL protocol.
On the basis of the foregoing embodiment, in a specific embodiment, the second receiving module may include:
the analysis submodule is used for analyzing the access request to obtain a corresponding address resource;
and the determining submodule is used for determining a third CPU corresponding to the address resource according to the preset corresponding relation table.
On the basis of the foregoing embodiment, in a specific embodiment, the second receiving module may further include:
the distribution submodule is used for distributing corresponding address resources for each CPU according to the input address distribution request;
and the establishing submodule is used for establishing a preset corresponding relation table according to the corresponding relation between each CPU and the address resource.
Since the embodiments of the apparatus portion and the method portion correspond to each other, please refer to the description of the embodiments of the method portion for the embodiments of the apparatus portion, which is not repeated here.
Referring to fig. 6, fig. 6 is a structural diagram of an interconnection apparatus according to an embodiment of the present application.
The interconnected device 600 may vary widely in configuration or performance and may include one or more processors 622 and memory 632, one or more storage media 630 (e.g., one or more mass storage devices) storing applications 642 or data 644. Memory 632 and storage medium 630 may be, among other things, transient or persistent storage. The program stored in the storage medium 630 may include one or more modules (not shown), each of which may include a sequence of instructions operating on the device. Further, the processor 622 may be configured to communicate with the storage medium 630 to execute a series of instruction operations in the storage medium 630 on the interconnected device 600.
The interconnect 600 may also include one or more power supplies 626, one or more wired or wireless network interfaces 650, one or more input-output interfaces 658, and/or one or more operating systems 641, such as Windows Server, Mac OS XTM, UnixTM, LinuxTM, FreeBSDTM, etc.
The steps in the method for CPU call between different architectures described in fig. 1 to 4 above are implemented by the interconnection device based on the structure shown in fig. 6.
It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described apparatuses, apparatuses and modules may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus, device and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, a division of modules is merely a division of logical functions, and an actual implementation may have another division, for example, a plurality of modules or components may be combined or integrated into another apparatus, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or modules, and may be in an electrical, mechanical or other form.
Modules described as separate parts may or may not be physically separate, and parts displayed as modules may or may not be physical modules, may be located in one place, or may be distributed on a plurality of network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, functional modules in the embodiments of the present application may be integrated into one processing module, or each of the modules may exist alone physically, or two or more modules are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode.
The integrated module, if implemented in the form of a software functional module and sold or used as a separate product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be substantially implemented or contributed to by the prior art, or all or part of the technical solution may be embodied in a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a function calling device, or a network device) to execute all or part of the steps of the method of the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, an optical disk, or other various media capable of storing program codes.
The method, the apparatus, the interconnection device and the readable storage medium for CPU call between different architectures provided by the present application are described in detail above. The principles and embodiments of the present application are explained herein using specific examples, which are provided only to help understand the method and the core idea of the present application. It should be noted that, for those skilled in the art, it is possible to make several improvements and modifications to the present application without departing from the principle of the present application, and such improvements and modifications also fall within the scope of the claims of the present application.
It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Claims (10)
1. A method for calling a CPU (Central processing Unit) between different architectures is applied to interconnection equipment, and comprises the following steps:
receiving calling information input by a first CPU;
determining a called second CPU and a corresponding calling requirement according to the calling information;
transmitting the calling requirement to a fixed memory corresponding to the second CPU, so that the fixed memory triggers inter-core interruption, and the second CPU responds to the inter-core interruption to execute the calling requirement;
the first CPU and the second CPU are provided with CXL interfaces, and the interconnection equipment is communicated with the first CPU and the second CPU respectively through a CXL protocol.
2. The method of claim 1, further comprising:
receiving an access request input by the first CPU, and determining an accessed third CPU according to the access request;
converting the access request into a consistent memory access request through protocol conversion, and sending the consistent memory access request to the third CPU, so that the third CPU executes the consistent memory access request and returns a corresponding consistent memory result;
sending the consistent memory result to the first CPU;
wherein the third CPU has the CXL interface, and the interconnect device communicates with the third CPU through the CXL protocol.
3. The method of claim 2, wherein determining the third CPU to be accessed based on the access request comprises:
analyzing the access request to obtain a corresponding address resource;
and determining the third CPU corresponding to the address resource according to a preset corresponding relation table.
4. The method of claim 3, further comprising, before parsing the access request to obtain the corresponding address resource:
allocating corresponding address resources for each CPU according to the input address allocation request;
and establishing the preset corresponding relation table according to the corresponding relation between each CPU and the address resource.
5. An apparatus for CPU invocation between different architectures, comprising:
the first receiving module is used for receiving calling information input by the first CPU;
the determining module is used for determining the called second CPU and the corresponding calling requirement according to the calling information;
the transmission module is used for transmitting the calling requirement to a fixed memory corresponding to the second CPU so that the fixed memory triggers inter-core interruption, and the second CPU responds to the inter-core interruption to execute the calling requirement;
the first CPU and the second CPU are provided with CXL interfaces, and the interconnection equipment is communicated with the first CPU and the second CPU respectively through a CXL protocol.
6. The apparatus of claim 5, further comprising:
the second receiving module is used for receiving an access request input by the first CPU and determining an accessed third CPU according to the access request;
the conversion module is used for converting the access request into a consistent memory access request through protocol conversion and sending the consistent memory access request to the third CPU so that the third CPU executes the consistent memory access request and returns a corresponding consistent memory result;
a sending module, configured to send the consistent memory result to the first CPU;
wherein the third CPU has the CXL interface, and the interconnect device communicates with the third CPU through the CXL protocol.
7. The apparatus of claim 6, wherein the second receiving module comprises:
the analysis submodule is used for analyzing the access request to obtain a corresponding address resource;
and the determining submodule is used for determining the third CPU corresponding to the address resource according to a preset corresponding relation table.
8. The apparatus of claim 7, wherein the second receiving module further comprises:
the distribution submodule is used for distributing corresponding address resources for each CPU according to the input address distribution request;
and the establishing submodule is used for establishing the preset corresponding relation table according to the corresponding relation between each CPU and the address resource.
9. An interconnect device, comprising:
a memory for storing a computer program;
a processor for implementing the steps of the method of CPU invocation between different architectures as claimed in any of claims 1 to 4 when said computer program is executed.
10. A readable storage medium, having stored thereon a computer program which, when executed by a processor, carries out the steps of the method of CPU invocation between different architectures as claimed in any of claims 1 to 4.
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| CN115934366A (en) * | 2023-03-15 | 2023-04-07 | 浪潮电子信息产业股份有限公司 | Server storage expansion method, device, equipment, medium and whole cabinet system |
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| CN115934366A (en) * | 2023-03-15 | 2023-04-07 | 浪潮电子信息产业股份有限公司 | Server storage expansion method, device, equipment, medium and whole cabinet system |
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