CN1145322C - Method for transmitting ATM cells over multi-master bus in ATM cell exchange - Google Patents
Method for transmitting ATM cells over multi-master bus in ATM cell exchangeInfo
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- CN1145322C CN1145322C CNB001303996A CN00130399A CN1145322C CN 1145322 C CN1145322 C CN 1145322C CN B001303996 A CNB001303996 A CN B001303996A CN 00130399 A CN00130399 A CN 00130399A CN 1145322 C CN1145322 C CN 1145322C
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- atm cell
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Abstract
The present invention relates to a method for transmitting ATM cells in the ATM cell exchange of a multi-master bus, which comprises that frames for transmitting the ATM cells are divided into initial frames and at least one data frame corresponding to the initial frames, and the bus requests of the data frame corresponding to the initial frame and the next initial frame are set in the clock cycle of the initial frame, which is exclusively used for the request; arbitration enable information is set in the initial frame to provide the enable information for the data frame corresponding to the initial frame and the next initial frame, or the arbitration enable information is set in each frame by dispersion to only provide the enable information for the next frame.
Description
The present invention relates to the ATM switching technology of the communications field, particularly relate to the ATM cell switching technology of multi-master bus mode.
ATM is the abbreviation of asynchronous transfer mode (Asynchronous Transfer Mode).Cell (Cell), or claim ATM cell, be a kind of packet of regular length.Long 53 bytes (Byte) of ATM cell, 5 bytes in front are called letter head (Header), and 48 bytes in back are called information field (InformationField).Being about other control information of the routing information of this cell and some in the letter head, then is the information that the user will transmit through telecommunications network in the information field.
The ATM exchange of multi-master bus mode belongs to a kind of of ATM switching technology, and the bus arbitration of multi-master bus mode belongs to the shared bus arbitration mechanism.Each interface module is articulated on the bus, when a module has cell to exchange, at first send the bus application by this module, whether allow to take bus by the bus arbitration mechanism decision, if allow, this module just with cell broadcast on bus, the total interface module is all checked the entrained routing iinformation of cell on the bus on the bus, find that destination address comprises that this module just copies this cell from bus, thereby finish the exchange of cell.
A kind of CellBus bus structures that proposed by transwitch company are arranged in the prior art, and it is a kind of multi-master bus ATM exchanged form.Have an equipment must dispose the bus arbitration function in the equipment on bus, miscellaneous equipment sends application to it, and moderator sends permission according to certain mechanism.Can only there be an arbitration the same time.Equipment disposition on CellBus has address field (5bits).This address is used for sending and sends application, and is used for differentiating the cell on the CellBus.CellBus can be configured to 16 users or 32 users.As shown in Figure 1, when 16 users, 16 equipment send the transmission application at first clock of every frame; As shown in Figure 2, during 32 users, per two frames of synchronizing signal just have one, and equipment 0～15 sends at even frame and sends application, and 16～31 equipment send this application at strange frame.
Fig. 1 shows the frame structure under 16 user models as the CellBus of prior art.As shown in Figure 1, the frame of CellBus has application, bus cell, allows three parts.
In the 0th clock cycle (Cycle0), CellBus equipment sends application on bus, can be referred to as to apply for word.The the 1st to the 14th clock cycle (Cycle1～14), be the cell part.At the 15th clock cycle (Cycle15), allow part to determine next frame by which equipment sending data, simultaneously, also have an odd even field that produces by transmitting apparatus.
In the application field, on corresponding 32 buses of each equipment two, wherein one as the priority setting.
In cell is overall, comprises 52 bytes of ATM cell, but the HEC field in the ATM cell has been deleted.At receiving terminal, again cell is outputed to and produce the HEC field before the UTOPIA interface and insert.
Concerning CellBus equipment, the cell of input has broadcasting, group broadcasting, single-address.Before beginning to receive cell, receiver carries out verification to the CEC-4 field of 4 bits of route head (routing header), also bit verification-8 (BIP-8) field is tested simultaneously.Problem is whichsoever arranged, and this cell is dropped.
Fig. 2 shows the frame structure under 32 user models as the CellBus of prior art.Under 32 users' situation, per two frames of synchronizing signal just have one, and equipment 0～15 sends at even frame and sends application, and 16～31 equipment send application at strange frame.
To sum up, CellBus transmission means according to prior art, each frame that transmits ATM cell all comprises an application word clock cycle, with supply equipment the bus of next frame is filed an application, and each frame also comprises one and allows the word clock cycle, and the arbitration of providing next frame to equipment for moderator allows information.Because each frame all will be taken out two clock cycle and be respectively applied for the application word and allow word, so just reduced the efficient of bus transmission ATM cell.The bit wide of bus is wide more, and the reduction of this efficient is just obvious more.Especially under the situation of higher bus bit wide, for example under the bus bit wide is 128 situation, the useful load that transmits an ATM cell only needs 4 clock cycle, at this moment, if taking out two clock cycle in each frame again is specifically designed to the application word and allows word, efficiency of transmission (being the ratio that efficient clock accounts for total clock) only is 4/6=2/3, will limit the transmission efficiency of ATM cell greatly.
The objective of the invention is to propose a kind of method that transmits ATM cell in the exchange of multi-master bus ATM cell, it can realize that in the exchange of multi-master bus ATM cell high efficiency ATM cell transmits, and can adapt to the more bus transfer of high-bit width better.
The object of the present invention is achieved like this: a kind of method that transmits ATM cell in the exchange of multi-master bus ATM cell, it is characterized in that, with the frame that transmits ATM cell be divided into initial frame and correspondingly be no less than a Frame, the bus application with corresponding Frame of this initial frame and next initial frame all was arranged in the clock cycle that of this initial frame is exclusively used in application; And will arbitrate allowing information setting in this initial frame,, perhaps will arbitrate allowing information dispersion to be arranged in each frame, only provide permission information for its next frame for providing permission information with corresponding Frame of this initial frame and next initial frame.
Allow information dispersion to be arranged in each frame will arbitrating, only for its next frame provides under the situation of permission information, described arbitration allows information setting in the optional position of a long word, and other positions of this long word are in order to padding data.
Allow information dispersion to be arranged in each frame will arbitrating, only for its next frame provides under the situation of permission information, described arbitration allows information setting in the optional position of a long word, and other positions of this long word are in order to the filling bit verification or keep need not.
The described clock cycle that is exclusively used in application is positioned at the frame head of initial frame.
Described each frame is all in order to transmit an ATM cell.
The arbitration that is arranged in the initial frame allows information, is arranged in a clock cycle after the described clock cycle that is exclusively used in application.
The arbitration that is arranged in the initial frame allows information, is arranged in last clock cycle of this initial frame.
Arbitration permission information and bit verification can merge puts into a clock cycle, also can take the different clock cycle respectively.
Described bus bit wide is that (32+8 * N), wherein N is a natural number.
Method of the present invention, the equipment that articulates on the bus is arranged in the initial frame the application of several frames (initial frame adds and is no less than a Frame) is concentrated, exempted the application word clock cycle in the Frame, thereby can high efficiency realization ATM cell transmit, and the bus bit wide is wide more, the present invention can adapt to more better, compared to its efficiency of transmission of prior art high advantage outstanding more.
For making the purpose, technical solutions and advantages of the present invention clearer, by the following examples, and in conjunction with the accompanying drawings, the present invention is described in more detail.Wherein
Fig. 1 shows the frame structure under 16 user models as the CellBus of prior art;
Fig. 2 shows the frame structure under 32 user models as the CellBus of prior art;
Fig. 3 shows " I+D " frame structure according to the present invention's first preferred embodiment;
Fig. 4 shows " I+2D " frame structure according to the present invention's first preferred embodiment;
Fig. 5 shows " I+3D " frame structure according to the present invention's first preferred embodiment;
Fig. 6 shows the bus interface schematic diagram in first preferred embodiment of the present invention;
Fig. 7 shows the bus interface signal timing diagram in first preferred embodiment of the present invention;
Fig. 8 shows the bus frame synchronizing signal position view in first preferred embodiment of the present invention;
Fig. 9 shows various frame structures and the performance thereof according to the present invention's first preferred embodiment;
Figure 10 shows " I+D " frame structure according to the present invention's second preferred embodiment;
Figure 11 shows " I+2D " frame structure according to the present invention's second preferred embodiment;
Figure 12 shows " I+3D " frame structure according to the present invention's second preferred embodiment;
Figure 13 shows the structural representation that allows word according to the dispersion arbitration of the present invention's second preferred embodiment;
Figure 14 shows various frame structures and the performance thereof according to the present invention's second preferred embodiment.
Because should what require that bandwidth is wider, efficiency of transmission is higher as the CellBus frame structure of prior art With in have defective, we have proposed the method that high efficiency of the present invention transmits ATM cell.
Consider when increasing the bus bit wide that the increase of application word word length can allow more bus request, like this Just a plurality of applications can be concentrated in the application word to improve the data bit width utilization rate. The while data bit width Increase causes arbitrating under the approaching condition of sensitivity with CellBus, allows to take place the transmission of multiframe (for carrying High-transmission efficient meter, a transmit data frames between twice application), the present invention namely designs in view of this consideration, from And effectively improved the efficiency of transmission of ATM cell.
Core concept of the present invention be with to the application concentrated setting of several frames a frame (referred to here as at the beginning of Beginning frame or I frame) in, the application word clock week in other frames (referred to here as Frame or D frame) exempted Phase, thus the high efficiency that reaches ATM cell exchanges. As for arbitration permission information, then can concentrated setting In initial frame, for providing permission information with the corresponding Frame of this initial frame and next initial frame, also can Allow information dispersion to be arranged in each frame of initial frame and Frame arbitrating, only carry for the next frame of this frame For permission information. Certainly need not more to speak more bright is should be positioned at the application word in sequential arbitration permission information Afterwards, first to file just has arbitration then.
Fig. 3 shows " I+D " frame structure according to the present invention's first preferred embodiment, and Fig. 4 shows " I+2D " frame structure according to the present invention's first preferred embodiment, and Fig. 5 shows " I+3D " frame structure according to the present invention's first preferred embodiment.As Fig. 1, Fig. 2, shown in Figure 3, apply for that wherein word is positioned at frame head, be the clock cycle that the equipment that is exclusively used in proposes the bus application, it is present in the initial frame.Allowing word is the clock cycle that is exclusively used in the issue arbitration result, it is positioned at the postamble of initial frame, in the present embodiment, a permission information that allows word to comprise several frames in the initial frame, these several frames are meant corresponding to Frame of this initial frame and next initial frame.Certainly, also can allow merging to take this postamble that is exclusively used in the permission word in the clock cycle bit verification (BIT INTERLEAVE PARITY is called for short BIP) and arbitration.BIP also can allow to take the different clock cycle with arbitration.
The bit wide of bus can be according to (32+8 * determine that N) wherein N is a natural number.According to the number of devices that the different bit wides and the needs of bus articulate, adopt the Frame of different numbers.In general, the bit wide of bus equipment wide more, that need articulate is few more, and the Frame that can adopt behind the initial frame is just many more.
Fig. 6 shows the bus interface schematic diagram in first preferred embodiment of the present invention.In the present embodiment, interface logic is used " GTL+ " standard interface.BTL (Backplane Transceiver Logic)/GTL+ (Gunning Transceiver Logic) standard, be that reflection and the noise problem that exists when overcoming the TTL/CMOS signal and transmit in High speed rear panel proposes, the maximum 5pf of BTL/GTL output capacitance, representative value 8～15pf than TTL/CMOS is little, can overcome the problem of the reflection and the signal distortion that noise is introduced of high frequency environment lower back partitioned signal, belong to low signal swing (Low-signal-swing) logic.
Method of the present invention is the same with Cell Bus, all is applicable to the multi-master bus mode, and bus arbitration belongs to the shared bus arbitration mechanism.Each interface module is articulated on the bus, when a module has cell to exchange, at first send bus request by this module, whether allow to take bus by the bus arbitration mechanism decision, if allow, this module just with cell broadcast on bus, the total interface module is all checked the entrained routing iinformation of cell on the bus on the bus, find that destination address comprises that this module just copies this cell from bus, thereby finish the exchange of cell.
With Cell Bus bus type seemingly, bus according to present embodiment design comprises: DATA signal (its load mode has adopted the present invention) includes, but is not limited to also that bus is read clock, bus is write control signals such as clock, bus frame synchronization, bus acknowledge and the congested indication of bus.Following docking port temporal constraint condition describes.
Fig. 7 shows the bus interface signal timing diagram in first preferred embodiment of the present invention.As shown in Figure 7, BRC among the figure (bus is read clock) and BWC (bus is write clock) are the interface input clock, and tSU is the preceding input data setup time in the effective hopping edge of BRC (the trailing edge sampling effectively), minimum 2.5ns; TH is the input data hold time behind the effective hopping edge of BRC (the trailing edge sampling effectively), and minimum is 2.5ns; TD is the dateout time-delay behind the effective hopping edge of BWC (the trailing edge sampling effectively), minimum 5ns.
Fig. 8 shows the bus frame synchronizing signal position view in first preferred embodiment of the present invention.As shown in Figure 8, BF (bus frame synchronization) signal only opens the life of starting at I frame (initial frame), and as special case, Cell Bus can regard as and has only the I frame, therefore has 16 users and 32 users' time sequence difference.Adapt to the inventive method and the bus of preferred configuration then can overcome this time sequence difference well.Even adopt similar 2bit to represent application, in the application word, can allow that also more user files an application, particularly reach 64 when above when data bit width, can in an application word, hold 32 above users' application, break through the restriction of former Cell Bus.
Fig. 9 shows various frame structures and the performance thereof according to the present invention's first preferred embodiment.Wherein efficiency of transmission is the ratio that efficient clock accounts for total clock; Packet transfer rate is a transmits data packets number in the unit period; Arbitration sensitivity is equivalent to bus arbitration interval timer number of cycles twice.Bus bit wide wherein is according to (32+8 * determine that N) N is a natural number.
In above-mentioned frame structure, the permission word that BIP that is provided by the source end and moderator send both can merge puts into one-period, also can take the different bus cycles respectively.Add dash area among Fig. 9 and be illustrated under the identical condition of efficient, can utilize data bit width still less to realize.
As special case, CellBus can regard the situation of having only the I frame under 32 buses as, it is the situation of N=0, as shown in Figure 9, transmit a complete frame and need 16 clock cycle, wherein valid data take 14 clock cycle, and efficiency of transmission (being the ratio that efficient clock accounts for total clock) is 14/16=7/8; Packet transfer rate (being equivalent to transmits data packets number in the unit period) is 1/16; Arbitration sensitivity (being equivalent to bus arbitration interval timer number of cycles twice) is 16.Its leading indicator all is lower than the frame structure that adopts the inventive method.
Figure 10 shows " I+D " frame structure according to the present invention's second preferred embodiment, and Figure 11 shows " I+2D " frame structure according to the present invention's second preferred embodiment, and Fig. 12 shows " I+3D " frame structure according to the present invention's second preferred embodiment.Shown in Figure 10,11,12, according to second preferred embodiment of the present invention, will arbitrate allowing information dispersion to be arranged in each frame, only provide permission information for its next frame, and should arbitration allow information setting in the optional position of a long word, other positions of this long word be in order to padding data.
Since transmit the byte that comprises in the data word (useful load clock cycle) of ATM cell, often required greater than ATM cell, therefore in data word, always have some idle bytes.And only need take a byte (Byte) to an arbitration permission information of a frame, therefore just this byte can be inserted the appropriate location of payload clock cycle.Thereby further omit the clock cycle that is exclusively used in permission.This arbitration permission information can be arranged in any suitable long word of frame structure, can also can be afterbody or centre position at the head of long word both.Wherein a kind of feasible scheme is that the permission word is arranged in the long word afterbody, as shown in figure 13.Its design feature is that the arbitration of only doing next frame (no matter being I frame or D frame) allows, and places it in an optional position (all the other can put data, can keep need not, also can be BIP etc.) in the long word., with regard to the position in the entire frame, not necessarily to only need be arranged in application word back and make arbitration mechanism generation arbitration result get final product with regard to this long word at postamble.The definition (as room, GPR, GEN, GTN) of each bit can be identical to the definition that allows word with CellBus in the prior art in the permission byte among Figure 13.
In the present embodiment, the permission word that BIP that is provided by the source end and moderator send both can be put into one-period, also can take the different bus cycles respectively.
Figure 14 shows various frame structures and the performance thereof according to the present invention's second preferred embodiment.Add dash area among the figure and be illustrated under the identical condition of efficient, can utilize data bit width still less to realize.
Method of the present invention, can high efficiency realization ATM cell transmit, and the bus bit wide is wide more, the present invention can adapt to more better, compared to its efficiency of transmission of prior art high advantage outstanding more, its can be extraordinary the requirement of adaptation broadband ATM exchange, obtained the beyond thought result of those of ordinary skill in the art.
It should be noted last that, above embodiment is only unrestricted in order to explanation the present invention, although the present invention is had been described in detail with reference to preferred embodiment, those of ordinary skill in the art is to be understood that, can make amendment or be equal to replacement the present invention, and not breaking away from the spirit and scope of the present invention, it all should be encompassed in the middle of the claim scope of the present invention.
Claims (9)
1, a kind of method that in the exchange of multi-master bus ATM cell, transmits ATM cell, it is characterized in that, with the frame that transmits ATM cell be divided into initial frame and correspondingly be no less than a Frame, the bus application with corresponding Frame of this initial frame and next initial frame all was arranged in the clock cycle that of this initial frame is exclusively used in application; And will arbitrate allowing information setting in this initial frame,, perhaps will arbitrate allowing information dispersion to be arranged in each frame, only provide permission information for its next frame for providing permission information with corresponding Frame of this initial frame and next initial frame.
2, the method for transmission ATM cell as claimed in claim 1, it is characterized in that, allow information dispersion to be arranged in each frame will arbitrating, only provide under the situation of permission information for its next frame, described arbitration allows information setting in the optional position of a long word, and other positions of this long word are in order to padding data.
3, the method for transmission ATM cell as claimed in claim 1, it is characterized in that, allow information dispersion to be arranged in each frame will arbitrating, only provide under the situation of permission information for its next frame, described arbitration allows information setting in the optional position of a long word, and other positions of this long word need not in order to filling bit verification or reservation.
4, the method for transmission ATM cell as claimed in claim 1 is characterized in that, the described clock cycle that is exclusively used in application is positioned at the frame head of initial frame.
5, the method for transmission ATM cell as claimed in claim 1 is characterized in that, described each frame is all in order to transmit an ATM cell.
6, the method for transmission ATM cell as claimed in claim 1 is characterized in that, the arbitration that is arranged in the initial frame allows information, is arranged in a clock cycle after the described clock cycle that is exclusively used in application.
7, the method for transmission ATM cell as claimed in claim 1 is characterized in that, the arbitration that is arranged in the initial frame allows information, is arranged in last clock cycle of this initial frame.
8, the method for transmission ATM cell as claimed in claim 1 is characterized in that, arbitration permission information and bit verification can merge puts into a clock cycle, also can take the different clock cycle respectively.
9, the method for transmission ATM cell as claimed in claim 1 is characterized in that, described bus bit wide is that (32+8 * N), wherein N is a natural number.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB001303996A CN1145322C (en) | 2000-10-31 | 2000-10-31 | Method for transmitting ATM cells over multi-master bus in ATM cell exchange |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB001303996A CN1145322C (en) | 2000-10-31 | 2000-10-31 | Method for transmitting ATM cells over multi-master bus in ATM cell exchange |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1351437A CN1351437A (en) | 2002-05-29 |
| CN1145322C true CN1145322C (en) | 2004-04-07 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB001303996A Expired - Fee Related CN1145322C (en) | 2000-10-31 | 2000-10-31 | Method for transmitting ATM cells over multi-master bus in ATM cell exchange |
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| US10439840B1 (en) * | 2018-07-27 | 2019-10-08 | Nxp B.V. | Method and device for communicating data frames on a multi-master bus |
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