CN114530174A - Memory and memory system - Google Patents

Memory and memory system Download PDF

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Publication number
CN114530174A
CN114530174A CN202210073679.1A CN202210073679A CN114530174A CN 114530174 A CN114530174 A CN 114530174A CN 202210073679 A CN202210073679 A CN 202210073679A CN 114530174 A CN114530174 A CN 114530174A
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memory
structural layer
slave
conductive
arrays
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CN202210073679.1A
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Chinese (zh)
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刘峻
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Yangtze River Advanced Storage Industry Innovation Center Co Ltd
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Yangtze River Advanced Storage Industry Innovation Center Co Ltd
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Priority to CN202210073679.1A priority Critical patent/CN114530174A/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)

Abstract

The embodiment of the application provides a memory and a storage system, wherein the memory comprises: a peripheral circuit; a storage area located at one side of the peripheral circuit; the storage area comprises a plurality of storage arrays and a first connecting structure positioned between two adjacent storage arrays; wherein both sides of the first connection structure respectively comprise a plurality of the storage arrays; a primary conductive wire extending from the peripheral circuit to the first connection structure; two ends of the main conducting wire are respectively connected with the peripheral circuit and the first connecting structure; and the at least two slave conducting wires are respectively connected with the first connecting structures, extend in the directions deviating from each other at two sides of the first connecting structures and are connected with the corresponding plurality of storage arrays.

Description

Memory and memory system
Technical Field
The present application relates to, but not limited to, the field of semiconductor technologies, and in particular, to a memory and a memory system.
Background
A memory generally includes a memory area provided with a plurality of memory arrays and peripheral circuits. The memory array in the memory is mainly used for storing data, and the peripheral circuit is mainly used for controlling access operations of the memory array in the memory area, such as programming, reading or erasing, and providing electrical signals for the memory array in the memory area.
With the development of semiconductor technology, the demand for the capacity of the memory has also increased. When the storage capacity of the memory is increased, the number of storage arrays arranged in the storage area of the memory is correspondingly increased, so that higher requirements are put on the performance of the memory.
Disclosure of Invention
In view of the foregoing, embodiments of the present application provide a memory and a memory system.
In a first aspect, an embodiment of the present application provides a memory, including:
a peripheral circuit;
a storage area located at one side of the peripheral circuit; the storage area comprises a plurality of storage arrays and a first connecting structure positioned between two adjacent storage arrays; wherein both sides of the first connection structure respectively comprise a plurality of the storage arrays;
a primary conductive wire extending from the peripheral circuit to the first connection structure; two ends of the main conducting wire are respectively connected with the peripheral circuit and the first connecting structure;
and the at least two slave conducting wires are respectively connected with the first connecting structures, extend in the directions deviating from each other at two sides of the first connecting structures and are connected with the corresponding plurality of storage arrays.
In some embodiments, the number of the memory arrays on both sides of the first connection structure is equal.
In some embodiments, the primary conductive wire is located in a first structural layer;
the slave conductive line is located in a second structural layer different from the first structural layer;
the first connecting structure communicates the first structural layer and the second structural layer.
In some embodiments, the first connection structure is a Via (Via) connecting the first structural layer and the second structural layer.
In some embodiments, the plurality of storage arrays are located in a third structural layer, the third structural layer being different from the first structural layer and different from the second structural layer; the memory further comprises:
at least one second connecting structure communicating the third structural layer and the second structural layer; the second connection structure connects the slave conductive lines and the corresponding memory arrays.
In some embodiments, the memory array includes a plurality of row units sequentially arranged along a first direction; the plurality of storage arrays are sequentially arranged along a second direction; the first direction is perpendicular to the extending direction of the slave conductive line; the second direction is parallel to the extending direction of the slave conductive line; wherein,
two sides of the first connecting structure are respectively connected with a plurality of parallel slave conducting wires;
the plurality of slave conductive lines are sequentially arranged in the first direction and respectively connected with the plurality of row units on the same straight line in the plurality of memory arrays.
In some embodiments, the row unit includes a plurality of memory blocks sequentially arranged along the second direction, and the memory further includes:
and the first-level conductive branch lines are connected with the slave conductive lines and are respectively connected with the storage blocks.
In some embodiments, the memory further comprises:
and the plurality of second-level conductive branch lines are connected with the first-level conductive branch lines and extend to the area range of the memory block along the second direction.
In some embodiments, the memory further comprises:
the power supply connecting pad is positioned in the peripheral circuit and is used for being connected with a power supply; wherein the power supply connecting pad is connected with the main conducting wire.
In some embodiments, the width of the master conductive line is greater than the width of the slave conductive line.
In addition, an embodiment of the present application further provides a storage system, including:
the memory as described in the above embodiments;
a controller coupled with the memory for controlling the memory.
The memory provided by the embodiment of the application can transmit the received electric signals to between two adjacent memory arrays through the main conducting wire extending from the peripheral circuit to the first connecting structure, realize the distribution of the signals on the first connecting structure, and transmit the distributed electric signals to the plurality of memory arrays corresponding to two sides of the first connecting structure respectively through the auxiliary conducting wire connected with the first connecting structure. Therefore, on one hand, delay and voltage drop in the signal transmission process can be reduced, and the performance of the memory is effectively improved; on the other hand, when the storage capacity is increased, the loss between the storage arrays can be improved in a balanced manner, and the reliability of the memory can be improved.
Drawings
Fig. 1A is a first schematic plan view illustrating a phase change memory according to an embodiment of the present disclosure;
fig. 1B is a schematic plan structure diagram of a phase change memory according to an embodiment of the present application;
fig. 1C is a schematic plan view illustrating a third phase change memory according to an embodiment of the present disclosure;
FIG. 2 is a first schematic diagram of a memory according to an embodiment of the present disclosure;
fig. 3A is a second schematic diagram of a memory according to an embodiment of the present disclosure;
fig. 3B is a third schematic diagram of a memory according to an embodiment of the present application;
fig. 3C is a fourth schematic diagram of a memory according to an embodiment of the present disclosure;
FIG. 3D is a fifth schematic diagram of a memory according to an embodiment of the present disclosure;
FIG. 4A is a partial schematic view of a memory array according to an embodiment of the present disclosure;
FIG. 4B is a partial schematic diagram of a memory array according to an embodiment of the present application;
FIG. 4C is a partial schematic diagram of a memory array according to an embodiment of the present application;
FIG. 5 is a partial schematic view of a row unit according to an embodiment of the present disclosure;
FIG. 6 is a partial schematic diagram of a memory block according to an embodiment of the present application;
FIG. 7 is a fifth schematic diagram of a memory according to an embodiment of the present disclosure;
fig. 8 is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure;
fig. 9 is a schematic diagram of a storage system according to an embodiment of the present application.
Detailed Description
To facilitate an understanding of the present application, exemplary embodiments disclosed herein will be described in more detail below with reference to the associated drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present application. It will be apparent, however, to one skilled in the art, that the present application may be practiced without one or more of these specific details. In some embodiments, some technical features that are well known in the art are not described in order to avoid confusion with the present application; that is, not all features of an actual embodiment may be described herein, and well-known functions and structures may not be described in detail.
In general, terms may be understood at least in part from the context of their use. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in the singular or may be used to describe a combination of features, structures, or characteristics in the plural, depending, at least in part, on the context. Similarly, terms such as "a" or "the" may also be understood to convey a singular use or to convey a plural use, depending, at least in part, on the context. Additionally, the term "based on" may be understood as not necessarily intended to convey an exclusive set of factors, and may instead allow for the presence of additional factors that are not necessarily expressly described, again depending at least in part on the context.
Unless otherwise defined, the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In order to provide a thorough understanding of the present application, detailed procedures and detailed structures will be set forth in the following description so as to explain the technical aspects of the present application. The following detailed description of the preferred embodiments of the present application, however, will suggest that the present application may have other embodiments in addition to these detailed descriptions.
Referring to fig. 1A, a planar structure of a phase change memory is shown. Among them, a plurality of memory arrays 11 (i.e., Bank0, Bank1, Bank2 … … Bank n as shown in fig. 1A) are collectively arranged and arranged in the memory area 10 in order; the peripheral circuit 20 is disposed adjacent to the memory area 10. Note that the storage area may be divided into an upper storage area 10a and a lower storage area 10b according to storage capacity, and a corresponding storage array Control Unit (BCU) 12 may be disposed between the upper storage area 10a and the lower storage area 10 b.
Further, as shown with reference to FIG. 1B, input/output (I/O) interfaces and corresponding power devices (e.g., pads) 21, data processing block 22, voltage processing block 23, regulator 24, redundancy block 25, oscillator 26, system logic control 27, one-time programmable memory (eFuses) 28, temperature sensors 29 or other electronic components, etc. may be included in peripheral circuitry 20. The I/O interface is used for receiving a control command from an external controller and controlling the memory to transmit data; the power device is used for receiving an electrical signal provided by a power supply outside the memory and transmitting the electrical signal to a corresponding memory array inside the memory according to a control command so as to drive a corresponding memory cell to perform relevant operations (for example, programming, reading, erasing and the like).
It is understood that fig. 1B shows an alternative connection structure of the relevant circuits or electronic components in the peripheral circuit 20, and the peripheral circuit 20 may further include additional peripheral circuits not shown in fig. 1B, and the embodiments of the present application should not be limited thereto.
Referring to fig. 1C, in particular, when an external power supply applies an electrical signal to the memory, the peripheral circuit 20 may transfer the electrical signal to the memory area 10 through the plurality of wires 30. Illustratively, a plurality of conductive lines 30 extend from the peripheral circuitry 20 to each memory array 11 within the memory 10 to connect to the corresponding memory array 11. If the number of memory arrays 11 is increased, the length of the conductive line 30 is increased, and the voltage drop generated on the conductive line 30 is increased, i.e. a large power supply voltage drop (V-drop) is generated, which may result in the performance of the memory being reduced. On the other hand, during the process of transmitting the signal to the corresponding memory cell by the wire 30, a corresponding resistance-capacitance (RC) delay is generated, and as the wire 30 grows, the RC delay corresponding to the memory array 11 which is farther away from the peripheral circuit 20 is larger, which further reduces the reliability of the memory.
In view of the foregoing, embodiments of the present application provide a memory and a memory system.
As shown in fig. 2, an embodiment of the present application provides a memory 100, including:
a peripheral circuit 110;
a memory area 120 located at one side of the peripheral circuit 110; the storage area 120 includes a plurality of storage arrays 130 and a first connection structure 140 located between two adjacent storage arrays 130; wherein, two sides of the first connection structure 140 respectively include a plurality of the storage arrays 130;
a main conductive line 150 extending from the peripheral circuit 110 to the first connection structure 140; two ends of the main conductive wire 150 are respectively connected to the peripheral circuit 110 and the first connecting structure 140;
at least two slave conductive lines 160 are respectively connected to the first connection structures 140, extend in directions away from each other on both sides of the first connection structures 140, and connect the corresponding plurality of memory arrays 130.
It should be noted that fig. 2 is a schematic plan view illustrating a Memory 100, which may be a common semiconductor Memory, such as a Dynamic Random Access Memory (DRAM), a NAND Flash Memory (NAND Flash Memory), or a phase change Memory. The memory according to the embodiment of the present application may be a phase change memory or a three-dimensional (3D) phase change memory, and it is understood that the memory 100 may also be applied to other semiconductor memories, and the present application is not limited thereto.
In the embodiment of the present application, referring to fig. 2, the peripheral circuit 110 is arranged adjacent to the memory area 120 and is located in the same plane. Peripheral circuitry 110 may include any suitable analog, digital, and mixed-signal circuitry, and in particular may include various types of electronic components formed using metal-oxide-semiconductor (MOS) technology, such as registers, oscillators, voltage regulators, drivers, or voltage/current generators, among others.
In some embodiments, to increase the storage capacity of the memory, the present embodiment may involve stacking a plurality of memories 100 on top of each other to form a three-dimensional structure. Therefore, the peripheral circuit 110 and the storage area 120 which are adjacently arranged in the embodiment of the present application can facilitate wiring, and reduce the process difficulty.
It will be appreciated that the peripheral circuitry 110 shown in fig. 2 may be the peripheral circuitry 20 shown in fig. 1A-1C, i.e., may also include I/O interfaces and power devices.
Illustratively, referring to fig. 3A, the peripheral circuit 110 may be disposed to extend in the y direction and receive control commands and electrical signals from the outside, and transfer them to the plurality of memory arrays 130 in the memory area 120 through the above-mentioned I/O interface and power device. Here, a plurality of memory arrays 130 may be sequentially arranged in the x direction within the memory area 120.
Further, the first connection structure 140 is located between two adjacent memory arrays 130 and divides the memory area 120 into a first memory area 120a and a second memory area 120 b. The first storage area 120a and the second storage area 120b are respectively located at two sides of the first connection structure 140, and both may include a plurality of storage arrays 130. As shown in fig. 3A, the first storage region 120a may be located in a negative direction of the x-axis of the first connection structure 140, and the second storage region 120b may be located in a positive direction of the x-axis of the first connection structure 140. It is understood that the first storage region 120a may also be located in the positive direction of the x-axis of the first connection structure 140, and correspondingly, the second storage region 120b is located in the negative direction of the x-axis of the first connection structure 140.
It should be noted that, in practical applications, the number of the storage arrays 130 in the first storage area 120a and the second storage area 120b may be the same or different, and the application is not limited herein.
The first connecting structure 140 may be a wire having an input end and two output ends, a shunt/voltage divider circuit, or other electronic components capable of realizing electrical signal distribution; the electronic component may have a plurality of input terminals and a plurality of output terminals to distribute the electrical signals. The first connection structure 140 is used for shunting signals of one or more master conductive wires 150 and respectively providing the signals to the corresponding slave conductive wires 160 on two sides. It is understood that when the first connection structure 140 is a conductive structure, two adjacent memory arrays 130 on both sides of the first connection structure 140 are electrically isolated from the first connection structure 140.
In the embodiment of the present application, as shown in fig. 3A, the first connection structure 140 may be disposed at a corresponding position with the peripheral circuit 110, i.e., also extending in the y-axis direction, so that the first storage area 120a and the second storage area 120b may be effectively separated to reduce electrical interference between the two areas. It should be emphasized that the area occupied by the actual electronic component represented by the first connection structure 140 in the drawings corresponding to the embodiments of the present application is not the outline and shape of the first connection structure 140.
Further, the present embodiment may transmit the electrical signal received by the peripheral circuit 10 to the first connection structure 140 through the main conductive line 150. Illustratively, the main conductive wire 150 may be a conductive wire with a large width, a small resistance, and a fast transmission speed, which may effectively reduce the loss of the electrical signal during transmission. It is emphasized that in the memory of fig. 1C, the width of the plurality of conductive lines 30 cannot be too large due to limitations in the number of memory arrays and memory capacity, which would otherwise cause wiring difficulties. On the other hand, the memory array 11 (e.g., BankN in fig. 1C) that is far from the peripheral circuit 20 is also more affected by the resistance-capacitance delay and the voltage drop.
In contrast, the main conductive line 150 in the embodiment of the present application may extend directly from the peripheral circuit 110 to the first connection structure 140, which may make the width of the main conductive line 150 larger than the conductive line 30 in fig. 1C and reduce the transmission loss in the memory array 130.
Further, the conductive lines 160 extending at both sides of the first connection structure 140 may ultimately transmit the electrical signals to the respective memory arrays 130 in the memory area 120. Illustratively, referring to fig. 3A, the embodiment of the present application may have at least two slave conductive lines 160 respectively disposed in the first memory region 120a and the second memory region 120 b. Here, the conductive lines 160 extend in directions (e.g., positive x-axis direction and negative x-axis direction in fig. 3A) away from each other on both sides of the first connection structure 140, respectively, and are electrically connected to the plurality of memory arrays 130 in the memory region in which they are located.
In the embodiment of the present disclosure, the main conductive line 150 may be disposed at a different layer from the memory region 120 and the secondary conductive line 160, and may also be disposed in a blank region at the periphery of the memory array 130, so that signal transmission with low impedance may be realized in the form of a wider conductive line in a sufficient space.
In some embodiments, as illustrated with reference to FIG. 3B, a storage array control module 170 may also be included in the storage area 120. The storage array control module 170 may be the same as the storage array control unit 12 of fig. 1A to 1C. Illustratively, the memory array control module 170 is electrically connected to the peripheral circuit 110, so as to implement signal interaction, so that the peripheral circuit 110 provides control signals, such as programming or read/write signals, etc., to each memory array 130 in the memory area 120 through the memory array control module 170.
In particular, the memory array control module 170 may include drivers, decoders, sense amplifiers or other electronic components that control the memory array 130, and the like.
The memory 100 provided in the embodiment of the present application may transmit the received electrical signal between two adjacent memory arrays 130 through the main conductive line 150 extending from the peripheral circuit 110 to the first connection structure 140, and distribute the signal on the first connection structure 140, and then transmit the distributed electrical signal to the plurality of memory arrays 130 corresponding to two sides of the first connection structure 140 through the sub conductive lines 160 connected to the first connection structure 140 and extending away from each other on two sides of the first connection structure 140. Therefore, on one hand, delay and voltage drop in the signal transmission process can be reduced, and the performance of the memory is effectively improved; on the other hand, when the storage capacity is increased, the loss between the storage arrays can be improved in a balanced manner, and the reliability of the memory can be improved.
In some embodiments, referring to fig. 3C, the number of the memory arrays 130 on both sides of the first connection structure 140 is equal.
In the embodiment of the present application, the closer to the memory array 130 of the first connection structure 140, the less the loss of the received electrical signal. Correspondingly, the farther away from the memory array 130 of the first connection structure 140, the more wires or electronic components are needed to pass through the electrical signal during transmission, and the larger the rc delay and voltage drop, the greater the impact on the access operation performed on the memory array 130.
Referring to fig. 3C, the memory areas 120 at both sides of the first connection structure 140 may be divided into a first memory area 120a and a second memory area 120 b. Here, the first memory area 120a has N memory arrays 130 therein, for example, Bank0_ a, Bank N _ a in fig. 3C, and a plurality of memory arrays 130 located therebetween. Similarly, the second memory area 120b may also have N memory arrays 130 therein, such as Bank0_ b, Bank N _ b in fig. 3C, and a plurality of memory arrays 130 therebetween.
It is understood that the delays and voltage drops of the received electrical signals of the two memory arrays 130 (e.g., Bank0_ a and Bank0_ b in fig. 3C) in the first memory area 120a and the second memory area 120b, which are the same or not different from the first connecting structure 140, should be the same or not different.
Therefore, in the embodiment of the present application, the number of the plurality of memory arrays 130 on both sides of the first connection structure 140 is equal, so that on one hand, the loss of the electrical signals of the memory array 130 on the side of the first connection structure 140 away from the peripheral circuit 110 is effectively reduced, and on the other hand, the resistance-capacitance delay and the voltage drop of the electrical signals received by the two memory arrays 130 respectively located at the corresponding positions of the conductive lines are substantially consistent, which is beneficial to balance and improve the performance of the memory.
In some embodiments, FIG. 3D illustrates a schematic cross-sectional view of storage area 120 of FIG. 3A along direction aa'. Specifically, referring to fig. 3D, the primary conductive wire 150 is located in the first structural layer 210;
the slave conductive line 160 is located in a second structural layer 220 different from the first structural layer 210;
the first connecting structure 140 connects the first structural layer 210 and the second structural layer 220.
In the embodiment of the present application, the components in the memory 100 may be located on different structural layers. Illustratively, the main conductive line 150 may be located in a first structural layer, and the sub-conductive line 160 may be located in a second structural layer, where the first structural layer and the second structural layer are stacked in a direction perpendicular to the surface of the memory array to separate the main conductive line 150 and the sub-conductive line 160 from each other.
Further, a first connection structure 140 that communicates the first structural layer and the second structural layer may be provided. Here, the term "communicate" means an electrical connection. In some embodiments, if the first structural layer is in direct contact with the second structural layer, the first connection structure 140 may partially penetrate the first structural layer and the second structural layer to electrically connect the master conductive wire 150 and the slave conductive wire 160. If the first structural layer and the second structural layer are not in direct contact, the first connecting structure 140 may be disposed between the first structural layer and the second structural layer to connect the first structural layer and the second structural layer, so as to achieve the electrical connection between the master conductive wire 150 and the slave conductive wire 160.
It is emphasized that the first structural layer and the second structural layer may be solid structural layers including dielectric materials (e.g., silicon oxide or silicon nitride) and/or conductive materials (e.g., metal), or may be a spatial region representing the position relationship of each component in the memory 100.
For example, the plane corresponding to the first structural layer may be located above the plane corresponding to the second structural layer, or may be located below the plane corresponding to the second structural layer. Specifically, when the first structural layer is, for example, a top metal layer, the second structural layer may be a sub-metal layer, and the first structural layer and the second structural layer may be connected through a contact plug, a via, or other interconnect structures, so that the width of the main conductive line 500 may be increased as much as possible to reduce transmission loss of the electrical signal.
In the embodiment of the present application, the master conductive wire 150 and the slave conductive wire 160 are located on the planes corresponding to different structural layers, which can reduce the difficulty of wiring and the interference between electrical signals.
In some embodiments, the first connection structure 140 is a via connecting the first structural layer and the second structural layer.
In the embodiment of the present application, the master conductive line 150 and the slave conductive line 160 may be metal interconnection lines, and the first structural layer corresponding to the master conductive line 150 and the second structural layer corresponding to the slave conductive line 160 may be two different planes representing spatial regions.
Further, the first connection structure 140 may be a via directly connecting the main conductive line 150 and the sub conductive line 160, and indirectly communicating the first structure layer and the second structure layer, so that the influence on the electrical signal may be reduced compared to other interconnection structures, and the heat dissipation performance is also better.
Specifically, one end of the via may be connected to the master conductive line 150, and the other end may be respectively connected to the at least two slave conductive lines 160, and the electrical signal in the master conductive line 150 is distributed to the at least two slave conductive lines 160. It can be understood that if the material and the length of the slave conductive lines 160 of the connection via have the same factor that affects the strength of the electrical signal, the first connection structure 140 may uniformly distribute the electrical signal to the at least two slave conductive lines 160.
The embodiment of the application adopts the via hole as the first connecting structure 140, so that the process difficulty can be reduced, the signal loss can be reduced, and the distribution of the electric signals can be efficiently and accurately realized.
In some embodiments, referring to fig. 3D, the plurality of memory arrays 130 are located in a third structural layer 230, the third structural layer 230 being different from the first structural layer 210 and different from the second structural layer 220; the memory 100 further comprises:
at least one second connecting structure 180 connecting said third structural layer 230 and said second structural layer 220; the second connection structure 180 connects the slave conductive line 160 and the corresponding memory array 130.
For example, in the embodiment of the present application, the plurality of memory arrays 130 may be located on a different level from the main conductive line 150 and the sub conductive line 160, i.e., the third structural layer 230 is different from the first structural layer 210 and different from the second structural layer 220.
Specifically, the first structural layer 210, the second structural layer 220, and the third structural layer 230 may be sequentially stacked in a direction perpendicular to the surface of the memory array 130. Here, the first structural layer 210 may be a top metal layer and is in communication with the second structural layer 220 through the first connection structure 140, i.e., a via; the second structural layer 220 may be an intermediate metal layer and is in communication with the third structural layer 230 through the second connection structure 180 described above.
In the embodiment of the present application, the second connection structure 180 may be a contact plug or an interconnection line to connect the slave conductive line 160 located in the second structural layer 220 with the plurality of memory arrays 130. In this way, the structural layers located at different planes may enable reduced electrical signal interference between the master conductive line 150, the slave conductive line 160, and the plurality of memory arrays 130, and facilitate routing.
In some embodiments, referring to fig. 4A to 4C, the memory array 130 includes a plurality of row units 131 sequentially arranged along a first direction D1; the plurality of storage arrays 130 are sequentially arranged along a second direction D2; the first direction D1 is perpendicular to the extending direction of the slave conductive line 160; the second direction D2 is parallel to the extending direction of the slave conductive line 160; wherein,
a plurality of parallel slave conductive wires 160 are connected to both sides of the first connection structure 140;
the plurality of slave conductive lines 160 are sequentially arranged in the first direction D1, and respectively connect the plurality of row units 131 located on the same straight line in the plurality of memory arrays 130.
It should be noted that the first direction D1 in fig. 4A to 4C in the embodiment of the present application may be the y-axis direction in fig. 3A or 3B, and the second direction D2 may be the x-axis direction in fig. 3A or 3B.
Specifically, the plurality of row units 131 are sequentially arranged in the first direction D1, where two adjacent row units 131 may be spaced apart from each other to achieve electrical isolation. The plurality of memory arrays 130 are sequentially arranged in the second direction D2, and two adjacent memory arrays 130 may be spaced apart from each other to achieve electrical isolation.
In some embodiments, referring to fig. 4A, the row units 131 between adjacent memory arrays 130 may have a one-to-one correspondence, i.e., a plurality of row units 131 arranged in a predetermined order in the first direction D1 may be located on the same straight line.
In other embodiments, referring to fig. 4B, the memory array 130 may include a memory array control module 170 therebetween, such that a plurality of row units 131 are sequentially arranged on both sides of the memory array control module 170, i.e., in directions away from each other along the first direction D1. Similarly, a plurality of row units 131 arranged in a predetermined order between adjacent memory arrays 130 may be located on the same straight line.
Further, referring to fig. 4C, the plurality of conductive lines 160 are sequentially arranged along the first direction D1, and the plurality of column cells 131 on the same line are in one-to-one correspondence, i.e., the plurality of conductive lines 160 are also sequentially arranged along the first direction D1 and are respectively connected to the corresponding column cells 131 in each memory array 130. Here, the plurality of slave conductive lines 160 may be parallel to each other.
It is to be understood that fig. 4C is a partially enlarged schematic view of the memory area (i.e., the second memory area 120b) located on the side of the first connection structure 140 close to the peripheral circuit 110 in fig. 3A, where a plurality of the areas extend from the conductive line 160 in the positive direction of the second direction D2. Similarly, for the storage region (i.e., the first storage region 120a) located on the side of the first connection structure 140 away from the peripheral circuit 110 in fig. 3A, the plurality of slave conductive lines 160 in this region should extend in the negative direction of the second direction D2. A similar arrangement is also true for the structure of fig. 4B that includes the storage array control module 170, which is not intended to be limiting herein.
In some embodiments, referring to fig. 5, the row unit 131 includes a plurality of memory blocks 1310 sequentially arranged along the second direction D2, and the memory 100 further includes:
a plurality of first level conductive branches 1311 connected to the slave conductive lines 160 and respectively connected to the plurality of memory blocks 1310.
It should be noted that fig. 5 is a partially enlarged view of a row of cells 131 based on fig. 4C, and the embodiment of the present application will be explained by taking three memory blocks 1310 as an example. It is understood that the number of the memory blocks 1310 in each row unit 131 needs to be determined according to the storage capacity of the memory in actual production.
For example, a plurality of memory blocks 1310 in the same row of cells 131 may be spaced apart from each other, wherein one memory Block 1310 may be referred to as a Block, and the memory Block 1310 may include a Word Line Driver 1312(Word Line Driver), a Bit Line Driver 1313(Bit Line Driver), and other circuit structures or electronic components. In the embodiment of the present application, each memory block 1310 may have at least one first level conductive branch 1311 corresponding to the conductive line 160 and extending toward the first direction D1 for electrically connecting to the memory block 1310.
In some embodiments, referring to fig. 6, the memory 100 further comprises:
a plurality of second-level conductive branches 1314 connected to the first-level conductive branches 1311 and extending into the area of the memory block 1310 along the second direction D2.
It should be noted that fig. 6 is a partially enlarged view of a memory block 1310 based on fig. 5.
Illustratively, a three-dimensional phase change memory is taken as an example, which has a plurality of memory cells stacked up and down, a word line can be shared between two adjacent memory cells up and down, a lower memory cell is coupled to a lower bit line, and an upper memory cell is coupled to an upper bit line. In addition, the above-described bit line driver 1313 may include an upper layer bit line selector 1313a and a lower layer bit line selector 1313 b.
Specifically, the first-level conductive branch 1311 in fig. 6 connects the slave conductive line 160 and the corresponding memory block 1310, and a plurality of second-level conductive branches 1314 may be connected to the first-level conductive branch 1311. Referring to fig. 6, a second level conductive branch 1314 may be connected to the first level conductive branch 1311 and to word line drivers in the memory block 1310 and provide word line signals for the word lines. The other two second-level conductive branches 1314 may be respectively connected to the first-level conductive branch 1311 and the upper bit line selector 1313a, and the first-level conductive branch 1311 and the lower bit line selector 1313b, and may provide bit line signals for the upper bit line and the lower bit line.
In some embodiments, the memory block includes a plurality of word lines parallel to each other and sequentially spaced in the first direction, the memory further including:
and a plurality of third-level conductive branches connected to the second-level conductive branches 1314 and respectively connected to the plurality of word lines.
For example, the plurality of memory cells in the memory block 1310 according to the embodiment of the present application may be sequentially arranged in a row direction (e.g., the first direction D1) and a column direction (e.g., the second direction D2), thereby forming a memory cell array. The memory cell array, the word line driver, the bit line driver, and the circuit structure or the electronic device constitute the memory block 1310. It should be noted that, since the memory cells in the same line, i.e., the same row or the same column, are connected to the same word line, the word lines may be sequentially spaced in the first direction D1 or the second direction D2 and parallel to each other in the memory cell array.
Further, as shown in conjunction with fig. 5 and 6, based on the extension of the first level conductive leg 1311 in the first direction D1, one of the second level conductive legs 1314 connects the first level conductive leg 1311 and the word line driver 1312 in the second direction D2. Further, the word line driver 1312 is connected to a plurality of third-level conductive branches (not shown), and transfers the word line signal to a corresponding word line according to an external control signal.
It should be noted that the plurality of second-level conductive branches and the first-level conductive branches, and the plurality of third-level conductive branches and the second-level conductive branches may be connected through an interconnection line or a via. In addition, the extending direction of the plurality of third-level conductive branch lines needs to be determined according to the word line direction in the actual memory cell array.
It is understood that, in other embodiments, the bit line driver may also be connected to a plurality of fourth-level conductive branches to respectively connect to a plurality of bit lines in the memory cell array, which is not limited herein.
In the embodiment of the present application, the main conducting wire 150, the secondary conducting wires 160, the first-stage conducting branch 1311, the second-stage conducting branch 1314 and other conducting branches can distribute electrical signals efficiently and quickly, and reduce the difficulty of wiring.
In some embodiments, as shown in fig. 7, the memory 100 further comprises:
a power connection pad 111 located in the peripheral circuit 110 for connecting with a supply power; wherein the power connection pad 111 is connected to the main conductive wire 150.
The power connection pad 111 according to the embodiment of the present application may be a pad or other electronic component electrically connected to an external power supply. Illustratively, the power connection pad 111 may include an input interface for introducing an electrical signal provided by a power supply into the memory 100, and an output interface for providing an electrical signal to electronic components (e.g., an oscillator or a voltage regulator, etc.) in the peripheral circuit 110 and the main conductive line 150.
Specifically, referring to fig. 7, one end of the main conductive wire 150 is connected to the output interface of the power connection pad 111, and extends along the negative x-axis direction to connect to the first connection structure 140. It is understood that the power connection pad 111 in fig. 7 may be the same as the power device 21 in fig. 1B, and the application is not limited thereto.
In some embodiments, the width of the master conductive wire 150 is greater than the width of the slave conductive wire 160.
In the embodiment of the present application, the main conductive line 150 connecting the peripheral circuit 110 and the first connection structure 140 may be provided as a conductive line having a large width, thereby reducing resistance and transmission loss. On the other hand, the slave conductive lines 160 need to be connected to a plurality of memory arrays 130, and may have a plurality of lines, so that the width thereof may be smaller than that of the master conductive line 150, so as to reduce the electrical interference between the slave conductive lines 160 and the wiring difficulty.
Referring to fig. 8, an embodiment of the present application further provides a semiconductor structure 1000, where the semiconductor structure 1000 includes:
a substrate 1100;
the memory 100, as described in the above embodiments, is located on the substrate 1100.
In the embodiment of the present application, the substrate 1100 may include, but is not limited to, a Silicon (Si) substrate, a Germanium (Ge) substrate, a Silicon Germanium (SiGe) substrate, a Silicon On Insulator (SOI) substrate, a Germanium On Insulator (GOI) substrate, or the like, and the substrate 1100 may be P-type doped or N-type doped.
In some embodiments, there may be an isolation layer over the substrate 1100 for protecting the substrate 1100, where the isolation layer may be composed of a single film or a multi-layer film. Illustratively, the isolation layer may include a silicon oxide layer and a silicon nitride layer stacked in this order from bottom to top over the substrate 1100. In other embodiments, the number of layers and the material of the isolation layer may also be adjusted according to actual requirements, which is not limited herein.
Further, the memory 100 may be formed by Deposition on the substrate 1100, where the Deposition process may include one or more of Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), or the like.
Therefore, the semiconductor structure 1000 provided by the embodiment of the present application can reduce delay and voltage drop during signal transmission through the memory 100 on the substrate 1100, effectively improve the performance of the semiconductor structure 1000, and can balance and improve the loss between the memory arrays in the semiconductor structure 1000 when the storage capacity of the semiconductor structure 1000 is increased, thereby improving the reliability of the semiconductor structure 1000.
In addition, referring to fig. 9, an embodiment of the present application further provides a storage system 2000, where the storage system 2000 includes:
the memory 100 as described in the above embodiments;
a controller 2100 coupled to the memory 100 for controlling the memory 100.
In the embodiment of the present application, the controller 2100 may be coupled to the memory 100 through a plurality of interfaces and may control operations of reading, erasing, and programming of the memory 100.
Illustratively, the controller 2100 may be designed for operation in a low duty cycle environment, such as a Secure Digital (SD) card, Compact Flash (CF) card, Universal Serial Bus (USB) flash drive, or other medium for use in electronic devices such as personal computers, digital cameras, mobile phones, and so forth. In some embodiments, the controller 2100 may also be designed for operation in a high duty cycle environment SSD or embedded multimedia card (eMMC) that is used as a data store and enterprise storage array for mobile devices such as smart phones, tablets, laptops, and the like. Further, the controller 2100 may also be configured to manage various functions with respect to data stored or to be stored in the memory 100, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, and the like; may also be configured to handle Error Correction Codes (ECC) with respect to data read from or written to memory 100. In addition, the controller 2100 may also perform any other suitable function, such as formatting the memory 100, or communicating with an external device (e.g., a host) according to a particular communication protocol. Illustratively, the controller 2100 may communicate with the external device via at least one of various interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, and so forth.
It should be noted that the features disclosed in the several method or apparatus embodiments provided in the present application may be combined arbitrarily to obtain new method or apparatus embodiments without conflict.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (11)

1. A memory, comprising:
a peripheral circuit;
a storage area located at one side of the peripheral circuit; the storage area comprises a plurality of storage arrays and a first connecting structure positioned between two adjacent storage arrays; wherein both sides of the first connection structure respectively comprise a plurality of the storage arrays;
a primary conductive wire extending from the peripheral circuit to the first connection structure; two ends of the main conducting wire are respectively connected with the peripheral circuit and the first connecting structure;
and the at least two slave conducting wires are respectively connected with the first connecting structures, extend in the directions deviating from each other at two sides of the first connecting structures and are connected with the corresponding plurality of storage arrays.
2. The memory of claim 1, wherein the number of the storage arrays on both sides of the first connection structure is equal.
3. The memory of claim 1, wherein the master conductive line is located in a first structural layer;
the slave conductive line is located in a second structural layer different from the first structural layer;
the first connecting structure communicates the first structural layer and the second structural layer.
4. The memory of claim 3, wherein the first connection structure is a via connecting the first structural layer and the second structural layer.
5. The memory of claim 3, wherein the plurality of memory arrays are located in a third structural layer, the third structural layer being different from the first structural layer and different from the second structural layer; the memory further comprises:
at least one second connecting structure communicating the third structural layer and the second structural layer; the second connection structure connects the slave conductive lines and the corresponding memory arrays.
6. The memory of claim 1, wherein the memory array comprises a plurality of row units arranged in sequence along a first direction; the plurality of storage arrays are sequentially arranged along a second direction; the first direction is perpendicular to the extending direction of the slave conductive line; the second direction is parallel to the extending direction of the slave conductive line; wherein,
two sides of the first connecting structure are respectively connected with a plurality of parallel slave conducting wires;
the plurality of slave conductive lines are sequentially arranged in the first direction and respectively connected with the plurality of row units on the same straight line in the plurality of memory arrays.
7. The memory of claim 6, wherein the row unit comprises a plurality of memory blocks sequentially arranged along the second direction, and the memory further comprises:
and the first-level conductive branch lines are connected with the slave conductive lines and are respectively connected with the storage blocks.
8. The memory of claim 7, further comprising:
and the plurality of second-level conductive branch lines are connected with the first-level conductive branch lines and extend to the area range of the memory block along the second direction.
9. The memory of claim 1, further comprising:
the power supply connecting pad is positioned in the peripheral circuit and is used for being connected with a power supply; wherein the power supply connecting pad is connected with the main conducting wire.
10. The memory of any one of claims 1-9, wherein the width of the master conductive line is greater than the width of the slave conductive line.
11. A storage system, comprising:
the memory of any one of claims 1-10;
a controller coupled with the memory for controlling the memory.
CN202210073679.1A 2022-01-21 2022-01-21 Memory and memory system Pending CN114530174A (en)

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