CN114530075A - Music theory electronic organ for teaching - Google Patents

Abstract

The invention belongs to the technical field of electronic organs, in particular to a music theory electronic organ for teaching; the utility model provides a music theory electronic organ is used in teaching, includes the folding musical instrument body, be equipped with the five-line staff table of writing by hand on the musical instrument body, the back of five-line staff table is equipped with many metal wires that correspond the parallel with the spectral line, the internal circuit board that is equipped with of musical instrument, integrated on the circuit board have master control circuit and with clock drive circuit, scanning circuit and the scanning of master control circuit communication pick up the circuit. The invention provides a new music theory electronic organ for teaching, which is characterized in that a metal wire is embedded under a staff table, a scanning circuit is connected to a circuit for leading the metal wire into the circuit to generate a scanning pulse signal, the possibility of generating eddy current by an electromagnetic induction circuit is avoided, and the possibility of generating radiation by magnetic field leakage is also avoided.

Description

Music theory electronic organ for teaching

Technical Field

The invention belongs to the technical field of electronic organs, and particularly relates to a music theory electronic organ for teaching.

Background

Along with the improvement of living standard of people, the musical instruments, the chesses, the paintings and the calligraphy become important components for people to enjoy the temperament and the spirit in spare time. The electronic organ is a music device which is happy by people, is popular among people, has multiple timbres, good tone quality and powerful functions, is popular among people, and is one of the most popular door-entering musical instruments for students to learn music. By utilizing the special function of the music synthesis of the electronic organ, students are cultivated with comprehensive music ability to arouse the enthusiasm of the students for understanding the music from the heart.

The electronic organ is a keyboard musical instrument, in fact, it is an electronic synthesizer, it adopts large scale integrated circuit, most dispose the memory storage of sound. Most of electronic organs used in the existing music classroom adopt an electric teaching board, a magnetic induction coil at the head of a teacher's pointer is used for inducing a magnetic field generated by a conductor buried under a staff on the electric teaching board, but eddy current is easily generated by adopting electromagnetic induction, sundries possibly enter between the coils, once the eddy current is generated, the electronic organs are the same as an induction cooker, and the safety problem is very obvious; the magnetic field leakage problem may exist on the outer ring of the magnetic induction coil, and the radiation may be generated.

Disclosure of Invention

Aiming at the problems, the invention provides a novel music theory electronic organ for teaching.

The specific technical scheme of the invention is as follows:

the invention provides a music theory electronic organ for teaching, which comprises a foldable organ body, wherein a handwriting staff table is arranged on the organ body, a plurality of metal wires which are parallel to spectral lines correspondingly are arranged on the back surface of the staff table, a circuit board is arranged in the organ body, and a main control circuit, a clock driving circuit, a scanning circuit and a scanning and picking circuit which are communicated with the main control circuit are integrated on the circuit board;

the clock driving circuit is used for providing clock input signals for the scanning circuit and the scanning pick-up circuit, the scanning circuit is used for receiving signals output by the main control circuit and introducing pulse current to the metal wire embedded under the staff gauge in real time to generate corresponding scanning pulse signals, the scanning pick-up circuit is used for receiving the scanning pulse signals and sending the scanning pulse signals to the main control circuit when in work, and the main control circuit is used for processing the scanning pulse signals and outputting reading and writing signal pulses to the clock driving circuit.

The invention has the following beneficial effects:

the invention provides a new music theory electronic organ for teaching, which is characterized in that a metal wire is embedded under a staff table, a scanning circuit is connected to a circuit for leading the metal wire into the circuit to generate a scanning pulse signal, the possibility of generating eddy current by an electromagnetic induction circuit is avoided, and the possibility of generating radiation by magnetic field leakage is also avoided.

Drawings

FIG. 1 is a schematic structural diagram of a conventional staff electric teaching board;

FIG. 2 is a block diagram of a conventional staff electric teaching board;

FIG. 3 is a block diagram of the musical instrument for teaching according to the present invention;

FIG. 4 is a schematic structural view of the body of the present invention;

FIG. 5 is a schematic structural view of the pointer of the present invention;

FIG. 6 is a circuit diagram of a master control circuit, a clock driving circuit, a scanning circuit and a scanning pick-up circuit in the present invention;

FIG. 7 is a circuit diagram of a microphone circuit of the present invention;

FIG. 8 is a circuit diagram of a music synthesizing circuit, a power amplifying circuit and a power IC according to the present invention;

FIG. 9 is a circuit diagram of a power circuit of the present invention;

FIG. 10 is a circuit diagram of a first signal acquisition circuit in accordance with the present invention;

FIG. 11 is a circuit diagram of a second signal acquisition circuit in accordance with the present invention;

fig. 12 is a circuit diagram of a power conversion circuit according to the present invention.

In fig. 1, 1 is a casing, 2 is a loudspeaker, 3 is a keyboard pattern, 4 is a demonstration board, 5 is a staff, 6 is a power socket, 7 is a control board, 8 is a vibrato switch, 9 is a keyboard display lamp switch, 10 is a tone-changing switch-C, 11 is a tone-changing switch-F, 12 is a tone-changing switch-G, 13 is a volume knob, 14 is a pointer jack, 15 is a power fuse, 16 is a power switch, 17 is a pointer, and 18 is a pitch display lamp.

Detailed Description

Before describing the technical solution of the embodiment of the present application, first, a technical scenario of the embodiment of the present application is described with reference to the drawings.

Referring to fig. 1, it is a schematic structural diagram of a staff electric teaching board. The structure consists of a shell, a demonstration board and a pointer, wherein an induction coil is arranged at the top of the pointer, and one of a series of leads and conductors which are parallel to spectral lines and correspond to the spectral lines are respectively embedded below a five-line staff on the demonstration board. During demonstration, the pointer is inserted into the pointer inserting hole, a user can write notes or phrases on the spectral line of the demonstration board at will, and when the pointer is touched by the pointer, the loudspeaker can emit corresponding pitches of the positions of the touched notes on the staff

Referring to fig. 2, the electric teaching board is a circuit block diagram, which is composed of an electronic organ circuit board, a keyboard display circuit board, a time division scanning and control circuit board, a pickup circuit board and a power supply 20. The electronic organ circuit is composed of a master oscillator 21, an audio generating circuit 22, an audio gating circuit 23, a tone color filter 24, an amplifier 25 and a loudspeaker 2; the time-division scanning and control circuit consists of a clock oscillator 26, a time-division pulse distributor 27, a scanning circuit driver 28, a time-division gate 29 and a series of conductors 19 buried under the common lines of the staff.

When the five-line spectrometer works, the clock oscillator generates a series of pulses with constant frequency and inputs the pulses into the time division pulse distributor, the pulse distributor generates time division signals which are respectively transmitted into the scanning circuit driver, the scanning pulse circuit is introduced into a series of conductors M buried under corresponding spectral lines of the five-line spectrometer to generate corresponding time division scanning pulse magnetic fields, and meanwhile, the output time division signals are respectively transmitted into the time division gating gates. The pick-up circuit is composed of an induction coil 23 arranged at the front end of the pointer and a scanning magnetic field pick-up device 32, the induction coil picks up corresponding time division scanning pulse magnetic field signals, and the signals output after the amplification and shaping of the induction circuit of the induction coil are sent to the time division gate;

the pointer is inserted into the jack of the pointer when corresponding to the structure chart, when the user touches a certain note of a certain spectral line on the staff of the demonstration board with the pointer, the induction coil arranged at the front end of the pointer picks up a time division scanning pulse magnetic field signal corresponding to the spectral line, the time division gating gate is controlled by the scanning magnetic field pick-up, and when the signal is synchronous with the signal from the time division pulse distributor, the control audio frequency gating circuit of the control signal enables the electronic organ circuit to send out the corresponding pitch of the position of the touched note on the staff.

However, eddy current is easy to generate by adopting electromagnetic induction, impurities may enter between coils, once the eddy current is generated, the safety problem is very obvious like an induction cooker; the magnetic field leakage problem may exist on the outer ring of the magnetic induction coil, and the radiation may be generated.

The application provides a music theory electronic organ for teaching.

As shown in fig. 3, the foldable musical instrument comprises a foldable musical instrument body, wherein a handwriting staff table is arranged on the musical instrument body, a plurality of metal wires which are parallel to the staff table and correspond to the staff lines are arranged on the back surface of the staff table, a circuit board is arranged in the musical instrument body, and a main control circuit, a clock driving circuit, a scanning circuit and a scanning and picking circuit which are communicated with the main control circuit are integrated on the circuit board;

the clock driving circuit is used for providing clock input signals for the scanning circuit and the scanning pick-up circuit, the scanning circuit is used for receiving signals output by the main control circuit and introducing pulse current to the metal wire embedded under the staff gauge in real time to generate corresponding scanning pulse signals, the scanning pick-up circuit is used for receiving the scanning pulse signals and sending the scanning pulse signals to the main control circuit when in work, and the main control circuit is used for processing the scanning pulse signals and outputting reading and writing signal pulses to the clock driving circuit.

The invention provides a new music theory electronic organ for teaching, which is characterized in that a metal wire is embedded under a staff table, a scanning circuit is connected to a circuit for leading the metal wire into the circuit to generate a scanning pulse signal, the possibility of generating eddy current by an electromagnetic induction circuit is avoided, and the possibility of generating radiation by magnetic field leakage is also avoided; meanwhile, the main control circuit is adopted to control all the circuits, so that the signal processing speed is higher and the intelligent performance is higher.

As shown in fig. 3 and 5, the present embodiment further includes a pointer 7, and the body and the pointer are electrically connected; the head of the pointer is provided with a metal receiving head 8, an acquisition circuit is integrated in the pointer, and the acquisition circuit is used for receiving scanning pulse signals sent by the metal wires when the metal receiving head is close to or contacts the five-line staff and sending the scanning pulse signals to the scanning and picking circuit; the wire emits a 25KHf square wave signal modulated at around 100-200 Hz.

The head of teacher's pointer adopts metal receiving head to replace induction coil in this embodiment, can avoid the production of vortex.

In this embodiment, the circuit board is further integrated with a music synthesis circuit, a power amplification circuit and a power supply circuit; the master control circuit processes the scanning pulse signals and then outputs midi signals to the music synthesis circuit, the music synthesis circuit is used for synthesizing the midi signals into digital audio stream signals and converting the digital audio stream signals into analog quantity signals, the power amplification circuit is used for amplifying the analog quantity signals and then outputting the analog quantity signals to the loudspeaker for playing, and the power supply circuit is used for converting input alternating current into working voltage for supplying power.

As shown in fig. 4, the musical instrument body includes a keyboard 1 and a display panel 2, which are rotatably connected by a rotating shaft, the keyboard is provided with a musical instrument key region and a staff big staff region, the musical instrument key region is provided with keys 3, the staff big staff region is provided with a staff big staff 4 and a plurality of display lamps 5, each display lamp 5 is arranged on the staff big staff 4, the position of the display lamp on the staff big staff 4 corresponds to the musical instrument key region and the staff big staff region, the musical instrument key region is provided with the keyboard 3, the staff big staff region is provided with the staff big staff 4 and a plurality of display lamps 5, each display lamp 5 is arranged on the staff big staff 4, and the position of the display lamp on the staff big staff 4 corresponds to the tone on the corresponding 3 of the tone on the keyboard 3; a staff 6 is arranged on the display panel, and a metal wire parallel to and corresponding to the spectral line is embedded under the spectral line of the staff; still be equipped with the jack on the lateral wall of the musical instrument body, including the teacher's pointer jack, the earphone jack, power jack, the USB jack, net twine jack etc. wherein, correspond when the teacher's pointer inserts the teacher's pointer jack and scan to pick up circuit and begin work.

As shown in fig. 5, the pointer is further provided with two switches for controlling the rising and falling of the sound respectively, and the temporary rising and falling of the sound can be performed when the pointer is used for demonstrating music, so as to meet the music requirement; the tone of each tone on the staff can be optionally raised and lowered, so that the teacher's pointer can be used for performing fixed tone singing method teaching on the staff in addition to the first tone singing method teaching; wherein. When the sound-raising switch is pressed, the emitted tone can automatically raise the semitone, and when the sound-lowering switch is pressed, the emitted tone can automatically lower the semitone. When the sound rising or falling switch is pressed down, the sound rising and falling signal is sent to the scanning and picking circuit through the acquisition circuit.

The music theory electronic organ for teaching comprises a keyboard and a display board, wherein the keyboard and the display board are connected in a rotating mode through a rotating shaft, when the music theory electronic organ is not used, the display board can be buckled on the keyboard, a body of the music organ can be protected, keys and a staff broad chart are arranged on the keyboard, the positions of a plurality of display lamps on the staff broad chart correspond to tones on the keyboard, the corresponding positions of musical scales on the keyboard and the staff are searched according to the names or the numbers of the keys, the corresponding names or the numbers of the keys are searched according to the names of the keys, the arrangement sequence of first tuning names of different modes on the keys, the musical interval relation among the keys of different tones, the combination rule of chord tones and the arrangement rule on the keyboard, the virtual abstract music theory knowledge is visualized, integrated, simplified and interesting, and the teaching music theory electronic organ is beneficial to mastering of students on the music theory.

As shown IN fig. 6, the main control circuit includes a main control chip U1(87C51), a latch U2(74LS373), a memory chip U3(29) and a static memory U6(6264), pin 31 of the main control chip U1 is connected to VCC, pin 19 is connected to ground through a capacitor C1, pin 18 is connected to ground through a capacitor C2, a crystal oscillator Y1(18.432M) is connected IN parallel between pin 18 and pin 19, pin 9 is connected to the output terminal of the inverter chip U5A, the input terminal of U5A is connected to VCC through a diode D1(IN4148) and to ground through a capacitor C4(10U), two terminals of a diode D2 are connected IN parallel to a resistor R1(20K), pin 10 of U1 receives an input signal, pin 11 outputs a midi signal, pin 30 is connected to the LE pin of the latch U2, pins 32-39 correspond to address lines D7-D0 of the latch U2, and pin 21-3628 is connected to the address line A3 a pin 3-3 a of the memory chip 3872, pins 17 are connected to an OE pin of the memory chip U3, a read enable signal pin OE of the static memory U6 and a clock driving circuit, pins 16 are connected to a write enable signal pin WE of the static memory U6 and a clock driving circuit, pins 1-3 are connected to address line pins A16-A18 of the memory chip U3, pins 8 are connected to a CE pin of the memory chip U3, a chip select signal pin CS2 of the static memory U6 and a clock driving circuit, the OE pin of the latch U2 is grounded, output pins Q2-Q2 are connected to address line pins A2-A2 of the memory chip U2, address line pins A2-A2 of the static memory U2 correspond to the address line pins A2-A2 of the memory chip U2 in parallel, data line pins DQ 4-D2 of the memory chip U2 and D2-D2 of the memory chip U2 are connected in parallel to the input pins D2-D2 of the latch U2, and the WE pin of the memory chip U3 is connected to VCC.

As shown in fig. 6, the main control circuit further includes a memory chip U4, the connection modes of the memory chip U4 and the memory chip U3 are the same, and the models are 29C 040.

As shown in fig. 6, the main control chip receives a signal from the server and outputs the signal to the server, and the specific circuit thereof is as follows: a pin 10 of the main control chip U1 is connected with a pin 6 of an optical coupler U16(6N135), a pin 8 connector VDD of the optical coupler U16, the pin 6 is connected with VDD through a resistor R21(4.7K), a pin 5 is grounded, a pin 2 is connected with a pin 1 of the interface MDIN and a pin 4 of the interface MIDIIN1 through a resistor R20(220), a pin 3 is connected with a pin 5 of the interface MIDIIN and a pin 2 of the interface MDIN, and a diode D2(IN4148) is connected between the pin 2 and the pin 3 IN parallel; the 11 pin of the main control chip U1 is connected with the base of a triode Q1(8050) through a NAND gate chip U7B and a resistor R6(2K), the emitter of the triode Q1 is grounded, the collector is connected with the 2 pin of an interface MDOUT and the 5 pin of the interface MIDIOUT1 through a resistor R7(270), the 1 pin of the interface MDOUT and the 4 pin of the interface MIDIOUT1 are connected in parallel and are connected with VCC through a resistor R8(200) and grounded through a capacitor C30 (220P); the interfaces MDIN, MIDIIN1, MDOUT and MIDIOUT1 are all connected with the server side, the interfaces MDIN and MIDIIN1 are used for receiving midi signals of the server side, and the interfaces MDOUT and MIDIOUT1 send the midi signals to the server side.

As shown IN fig. 8, the music synthesizing circuit includes a music synthesizer U19(CS9236) and a digital-to-analog converter U20(CS4333), a midi signal is input to pin 20 of the music synthesizer U19, pin 24 is connected to 3V through a resistor R58(47K), pin 24 is connected to 3V through a diode D3(IN4148) and is grounded through a capacitor C35(1U), pin 23 is connected to 3V through a resistor R56(10K), pins 19, 22, 8 and 5 are grounded, pins 9 and 21 are connected to 3V, pin 6 is connected to ground through a capacitor C53(22P), pin 7 is connected to ground through a capacitor C54(10P) and is connected to pin 4 of the digital-to-analog converter U20, a crystal oscillator XTAL1(16.9344M) is connected between pin 6 and pin 7, pin 10 and pin 11 are connected to pin 3V and pin 1 of the digital-to digital converter U20, pin 2 of the digital-to ground through a resistor R57(10K), a capacitor C5(10u) and a resistor R61(15K) are connected in series to pins A3V and A5 through pins 7, a capacitor C6(10u) and a resistor R62(15K) are connected in series to pins 8, the negative pole of the resistor 61 is connected with the power amplification circuit and grounded through a capacitor C56(1000P), and the negative pole of the resistor R62 is connected with the power amplification circuit and grounded through a capacitor C57 (1000P).

As shown in fig. 7, a microphone circuit is further integrated on the circuit board, the microphone circuit includes operational amplifiers U21C and U21B, a 10 pin of the operational amplifier U21C is connected to 2.5V through a resistor R71(20K), a resistor R70(20K) and a capacitor C60(0.1U) are connected in series to a 9 pin, a positive electrode of the capacitor C60 is connected to 5V through a resistor R75(10K) and to an interface MIC, the interface MIC is externally connected to the microphone, the 9 pin and the 8 pin of the U21C are connected in parallel through a resistor R69(27K), and are connected to a 6 pin of the operational amplifier U21B through a capacitor C29(0.1U) and a resistor R72(47K), a 5 pin of the U21B is connected to 2.5V through a resistor R74(20K), a7 pin is connected to output MICOUT to the power amplification circuit through a capacitor C28(0.1U), and a resistor R73(100K) is connected between the 6 pin and the 7 pin.

As shown in fig. 8, the power amplifying circuit includes operational amplifiers U21A and U21D (LM324), a2 pin of the operational amplifier U21A is connected to a negative electrode of a resistor R16 through a resistor R12(15K) and is connected to MICOUT through a resistor R67(47K), a3 pin is connected to 2.5V, a4 pin is connected to 5V, a 11 pin is grounded, a1 pin is connected to a2 pin of the interface AOUT through a capacitor C15(47U), the 1 pin and the 2 pin are connected in parallel through a resistor R14(150K), and two ends of the resistor R14 are connected in parallel to a capacitor C14 (22P);

the 12 pins of the operational amplifier U21D are connected with 2.5V, the 13 pins are connected with the negative electrode of the resistor 62 through a resistor R13(15K) and connected with MICOUT through a resistor R68(47K), the 14 pins are connected with the 3 pins of the interface AOUT through a capacitor C16(47U), the 13 pins and the 14 pins are connected in parallel through a resistor R16(150K), two ends of the resistor R16 are connected with a capacitor 61(22P) in parallel, and the interface AOUT is externally connected with a loudspeaker.

As shown in fig. 8, the power amplifying circuit further provides the output signal to a power integrated circuit, the power integrated circuit includes a power integrated chip U15(TEA2025), pin 10 of U15 is connected to the output terminal of the capacitor C16 through a capacitor C17(1U) and a resistor R17(150K), pin 7 is connected to the output terminal of the capacitor C15 through a capacitor C18(1U) and a resistor R59(150K), the cathode of the resistor R17 is grounded through a resistor R18(20K), the cathode of the resistor R59 is grounded through a resistor R19(20K), pin 11 of U15 is grounded through a capacitor C19(100U), pin 6 is grounded through a capacitor C20(100U), pin 8 is grounded through a capacitor C23(100U), pin 2 is connected to the earphone interface SP2 through a capacitor C15(470U) and is grounded through a capacitor C32(0.22U), pin 3 is connected to the earphone interface SP 2(100U) through a capacitor C22, pin is connected to the earphone interface 3615U) in parallel with the earphone interface 1U and the earphone interface 3646 (3680), pin 14 is connected in parallel with pin 15 through a capacitor C21(100u), pin 16 is connected to 9V, grounded through a capacitor C26(100u) and grounded through a capacitor C66(0.1 u); the headset interfaces SP2 and SP1 are external to the headset.

As shown in fig. 6, the clock driving circuit includes a decoder U8(74HC138), a nand gate chip U7A (74HC00), and not gate chips U5B and U5C (4069), where pin 1 of the not gate chip U7A is connected to pin 17 of the main control chip U1, pin 2 is connected to pin 16 of the main control chip, pin 3 is connected to pin 6 of the decoder U8, and pin 5 of the decoder U8 is connected to pin 8 of the main control chip through the not gate chip U5B;

pins 1 and 16 of the nand gate chip U7A and a read enable signal pin OE of the static memory U6 are respectively connected with a pin 2 of the nand gate chip U7A and a write enable signal pin WE of the static memory U6, a pin 4 is connected with a chip select signal pin CS1 of the static memory U6 through the not gate chip U5C, a pin 1 is respectively connected with a pin Q0 of the latch U2, a pin a0 of the memory chip U3 and a pin a0 of the static memory U6, a pin 2 is respectively connected with a pin Q1 of the latch U2, a pin a1 of the memory chip U3 and a1 of the static memory U6, and a pin 3 is respectively connected with a pin Q3 of the latch U2, a pin A3 of the memory chip U3 and a pin A3 of the static memory U6, and pins 11-15 output CS0-CS 4.

As shown IN fig. 9, the POWER circuit includes a POWER converter U22(MC34063A), a voltage regulator U23(MC7805), diodes D4-D7(IN4007), a loop formed by diodes D6 and D4 connected IN series is connected IN parallel with a loop formed by D7 and D5 connected IN series, the anode of D4 and the anode of D5 are both grounded, the anode of D6 is connected to pin 2 of interface POWER1, the anode of D7 is connected to pin 1 of interface POWER1, interface POWER1 is connected to an external POWER line, the cathode of diode D1 is output 9V, grounded through a capacitor C1 (2200U/16V) and connected to pin 6 of POWER converter U1 through a resistor R1 (1), the pin 6 of POWER converter U1 is grounded through a capacitor C1 (1000U/16V) and connected IN parallel with pin 7 through a resistor R1 (1), and the resistor R1 (1) is connected IN parallel with pin P1 and pin 1 (P1) and pin (P1) and P (1) are connected IN parallel with pin 1 and pin P (1), the 4 pins are grounded, the 2 pin is output VCC through an inductor L1(220uH) and is grounded through a resistor R51(2K), a resistor R50(1K) and a resistor R63(1K), the 5 pin is connected with the anode of a resistor R63, the input end of the inductor L1 is grounded through a diode D8(IN5819), and the output end is grounded through a capacitor C58(1000 u);

the 1 pin input 9V and the 2 pin input are grounded, the 3 pin output 5V of the voltage stabilizer U23 is grounded through a capacitor C68(10U) and is grounded through a resistor R10(10K) and a resistor R11(10K), a capacitor C63(0.1U) and a capacitor C65(0.1U) are respectively connected with two ends of the capacitor C68 in parallel, the negative pole output 2.5V of the resistor R10, and a capacitor C12(10U) and a capacitor C67(0.1U) are respectively connected with two ends of the resistor R11 in parallel.

The power supply circuit further comprises a triode Q2(9013) and a Q3(9013), the base electrode of the triode Q2 is grounded through a light emitting diode LED2(RED) and an LED1(RED), the collector electrode is connected with VDD, the emitter electrode outputs 3V, and a resistor R60(1K) is connected between the base electrode and the collector electrode in parallel;

the base of the transistor Q3 is grounded through the light emitting diode LED4(RED) and LED3(RED), the collector inputs 5V, the emitter outputs A3V is grounded through the capacitor C64(0.1u) and through the capacitor C11(470u), the resistor R79(2K) is connected IN parallel between the base and the collector, and the diode D11(IN4007) is connected IN parallel between the collector and the emitter.

As shown in fig. 6, the scan circuit includes a flip-flop U (74HC373), and a connector CON, where an input pin D-D of the flip-flop U, and an input pin D-D of the flip-flop U are respectively connected in parallel with an input pin D-D of the latch U, an output pin Q-Q of the flip-flop U, and an output pin Q-Q of the flip-flop U are respectively connected to pins 2 to 25 of the connector CON, a pin 1 of the flip-flop U is connected to VCC, a pin 11 is connected to a CS pin through a nor chip U5 (4069), a pin 1 of the flip-flop U is connected to VCC, a pin 11 is connected to a CS pin through a nor chip U5, and a pin CS1 of the flip-flop U is connected to VCC through a nor chip U5.

The acquisition circuit comprises a first signal acquisition circuit, a second signal acquisition circuit and a power supply conversion circuit, wherein the number of the pointer is two, and the first signal acquisition circuit and the second signal acquisition circuit correspond to one pointer respectively;

as shown in fig. 10, the first signal acquisition circuit includes operational amplifiers U17A-U17D (TL084), pin 2 of the input end of the operational amplifier U17A is connected to pin 2 of the interface JB1 through a resistor R28(47K), pin 3 is connected to VGND through a resistor R29(47K), pin 11 is grounded, pin 4 is connected to JB5V, pin 1 of the output end is connected to pin 5 of the interface JB 17B through a resistor R43(20K) and a capacitor C48(1000P), a resistor R34(1M) is connected in parallel between pin 1 and pin 2, a resistor C39(0.01U), a capacitor C35(0.01U) and a resistor C36(0.01U) are connected in series between pin R28 and pin 2 of the interface JB1, a resistor R23(330K) and a resistor R23(330K) connected in series are connected in parallel between the positive pole of the capacitor C36 and the negative pole of the interface JB 35, a resistor R23 (23) is connected in parallel to the ground through a resistor R23 (23K) and a resistor 6857, a resistor 23 (23) connected in parallel between the negative pole of the interface JB 685) and the resistor R23 (23) and the ground (23K) are connected in parallel, the cathode of the resistor R43 is connected with VGND through a capacitor C49(220P), the cathode of the capacitor C48 is connected with VGND through a resistor R38(20K), the 6 pin of the operational amplifier U17B is connected with VGND through a resistor R48(27K), a resistor R30(47K) is connected between the 6 pin and the 7 pin in parallel, the 7 pin is connected with the 9 pin of the operational amplifier U17C through a capacitor C40(0.01U) and a resistor R36(4.7K), the 10 pin of the operational amplifier U17C is connected with VGND through a resistor R53(15K), a capacitor C52(27P) is connected between the 9 pin and the 8 pin in parallel, the 8 pin is connected with the 13 pin of the operational amplifier U17D through a capacitor C41(0.1U), a resistor R55(20K) and a rheostat RV (47K) which are connected in series are connected at two ends of the capacitor C52, the cathode of the capacitor C41 is connected with the ground through a resistor R44(47K) and the operational amplifier U3646K and connected with the operational amplifier ND 17 ND through a resistor JB 77K, pin 14 outputs JB1, pin 1 of interface JB1 is grounded, and pin 3 and pin 4 respectively output JB1UP and JB1 DN;

the device comprises a U17A and a U17B, wherein the U17A and the U17B form band-pass filtering amplification, the U17C is adjustment of the induction sensitivity of a pointer, the U17D is a signal acquisition threshold gate, and when the amplitude of an acquired signal is larger than a threshold voltage, the signal is adopted and subjected to sound selection processing;

as shown in fig. 11, the second signal acquisition circuit includes an operational amplifier U18A-U18D (TL084), a pin 13 of an input terminal of the operational amplifier U18D is connected to a pin 2 of an interface JB2 through a resistor R31(47K), a pin 12 is connected to VGND through a resistor R32(47K), a pin 14 of an output terminal is connected to a pin 10 of the interface JB 18C through a resistor R39(20K) and a capacitor C47(1000P), a resistor R35(1M) is connected in parallel between the pin 13 and the pin 14, a capacitor C42(0.01U), a capacitor C37(0.01U) and a capacitor C38(0.01U) are connected in series between the pin R31 and the pin 2 of the interface 2, a resistor R25(330K) and a resistor R24(330K) are connected in series between an anode of the capacitor C38 and a cathode of the C37, a cathode of the resistor R25 is connected in parallel to a resistor R24 (38K) and a cathode of the operational amplifier U38 through a resistor C34 (38) and a resistor R38), the negative pole of the resistor R39 is connected with VGND through a capacitor C46(220P), the negative pole of the capacitor C47 is connected with VGND through a resistor R41(20K), the 9 pin of the operational amplifier U18C is connected with VGND through a resistor R49(27K), a resistor R33(47K) is connected between the 9 pin and the 8 pin in parallel, the 8 pin is connected with the 2 pin of the operational amplifier U18A through a capacitor C43(0.01U) and a resistor R42(4.7K), the 11 pin of the operational amplifier U A is grounded, the 3 pin is connected with VGND through a resistor R52(15K), the 4 pin is connected with JB5 JB V, a capacitor C51(27P) is connected between the 2 pin and the 1 pin in parallel, the 1 pin is connected with the 6 pin of the operational amplifier U18B through a capacitor C44(0.1U), the two ends of the capacitor C51 are connected with a resistor R54 RV (20K) and a rheostat 2(47K) in parallel, the negative pole of the capacitor C44 is connected with a resistor R3646 and a resistor R3646, a pin 5 of the operational amplifier U18B is connected with VGND, a pin 7 outputs JB2, a pin 1 of the interface JB2 is grounded, and a pin 3 and a pin 4 respectively output JB2UP and JB2 DN;

the device comprises a U18D and a U18C, wherein the U18D and the U18C form band-pass filtering amplification, the U17A is used for adjusting the induction sensitivity of a pointer, the U17B is used for acquiring a threshold value gate of a signal, and when the amplitude of the acquired signal is larger than the threshold value voltage, the acquired signal is adopted and subjected to sound selection processing; wherein, the interfaces JB1 and JB2 are both used for externally connecting a pointer, and in this embodiment, two pointers are taken as an example;

as shown in fig. 12, the power conversion circuit includes resistors R9(4.7), R46(10K), R47(10K), capacitors C13(220u) and C50(10u), a resistor R9 is connected in series with the capacitor C13, a positive input VCC of the resistor R9, a negative output JB5V, a negative ground of the capacitor C13, a resistor R46 is connected in series with a resistor R47, a capacitor C50 is connected in parallel across the resistor R47, a positive input JB5V of the resistor R46, and a negative output VGND;

the scanning and picking circuit comprises a pointer receiving circuit and a pointer lifting sound control circuit;

as shown in fig. 6, the pointer receiving circuit includes a driving signal chip U12(74HC244) and a counter U12(74HC 393), wherein pin 1 and pin 19 of the driving signal U12 are connected in parallel and then connected to pin 12 of the decoder U12, pin 1Y 12-1Y 12, pin 2Y 12-2Y 12 and pin 1Y 12-1Y 12, and pin 2Y 12-2Y 12 of the U12 are connected in parallel with pin D12-D12 of the latch U12, pin 1a 12-1 a12 of the driving signal chip U12 are connected to pin Q12-Q12 of the counter U12, pin 2a 12-2 a12 are connected to pin Q12-Q12 of the counter U12, a clock input pin of the counter U14 JB 12 is connected to pin Q12 of the counter 12, a reset input pin is connected to pin U12 of the U14 and connected to pin 7 of the main control circuit U12 in parallel, and pin JB 12 is connected to pin 12 of the clock input pin 12 of the U12;

as shown in fig. 6, the pointer lift-and-fall control circuit includes a driving signal chip U13, a pin 1 and a pin 19 of the driving signal chip U13 are connected in parallel and then connected to a pin 11 of a decoder U8, an input pin IA1 is connected to VCC through a resistor R2(4.7K), is connected to ground through a capacitor C7(1U) and is connected to JB2UP, the input pin IA2 is connected to VCC through a resistor R3(4.7K), is connected to ground through a capacitor C8(1U) and is connected to JB2DN, an input pin IA3 is connected to VCC through a resistor R4(4.7K), is connected to ground through a capacitor C9(1U) and is connected to JB1UP, the input pin IA4 is connected to VCC through a resistor R5(4.7K), is connected to ground through a capacitor C10(1U) and is connected to JB1DN, and output pins IY1-2Y4 are connected in parallel to input pins D0-D7 of a latch U2.

While this specification contains many specific implementation details, these should not be construed as limitations on the scope of any inventions or of what may be claimed, but rather as descriptions of features that may embody particular implementations of particular inventions. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in combination and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

In certain situations, multitasking and parallel processing may be advantageous. Moreover, the separation of various system modules and components in the embodiments described above should not be understood as requiring such separation in all embodiments.

Particular embodiments of the subject matter have been described. Other implementations are within the scope of the following claims. For example, the activities recited in the claims can be performed in a different order and still achieve desirable results. As one example, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In certain implementations, multitasking and parallel processing may be advantageous.

Claims (10)

1. A music theory electronic organ for teaching is characterized by comprising a foldable organ body, wherein a staff table for handwriting is arranged on the organ body, a plurality of metal wires which are parallel to spectral lines correspondingly are arranged on the back of the staff table, a circuit board is arranged in the organ body, and a main control circuit, a clock driving circuit, a scanning circuit and a scanning and picking circuit which are communicated with the main control circuit are integrated on the circuit board;

the clock driving circuit is used for providing clock input signals for the scanning circuit and the scanning pick-up circuit, the scanning circuit is used for receiving signals output by the main control circuit and introducing pulse current to the metal wire embedded under the staff gauge in real time to generate corresponding scanning pulse signals, the scanning pick-up circuit is used for receiving the scanning pulse signals and sending the scanning pulse signals to the main control circuit when in work, and the main control circuit is used for processing the scanning pulse signals and outputting reading and writing signal pulses to the clock driving circuit.

2. A teaching musical theory electronic organ according to claim 1, further comprising a pointer, said body being electrically connected to said pointer; the pointer is characterized in that a metal receiving head is arranged at the head of the pointer, an acquisition circuit is integrated in the pointer, and the acquisition circuit is used for receiving scanning pulse signals sent by the metal wires when the metal receiving head is close to or contacts the staff and sending the scanning pulse signals to a scanning and picking circuit.

3. A teaching musical theory electronic organ according to claim 2, wherein a music synthesizing circuit, a power amplifying circuit and a power supply circuit are further integrated on the circuit board; the main control circuit processes the scanning pulse signal and outputs a midi signal to the music synthesis circuit, the music synthesis circuit is used for synthesizing the midi signal into a digital audio stream signal and converting the digital audio stream signal into an analog quantity signal, the power amplification circuit is used for amplifying the analog quantity signal and outputting the analog quantity signal to a loudspeaker for playing, and the power supply circuit is used for converting input alternating current into working voltage for supplying power.

4. A music theory electronic organ for teaching aid according to claim 3, wherein the main control circuit comprises a main control chip U1, a latch U2, a memory chip U3 and a static memory U6, pin 31 of the main control chip U1 is connected with VCC, pin 19 is grounded through a capacitor C1, pin 18 is grounded through a capacitor C2, a crystal oscillator Y1 is connected in parallel between pin 18 and pin 19, pin 9 is connected with the output terminal of the inverter chip U5A, the input terminal of U5A is respectively connected with VCC through a diode D1 and grounded through a capacitor C4, two ends of a diode D1 are connected with a resistor R1 in parallel, pin 10 of U1 receives an input signal, pin 11 outputs a midi signal, pin 30 is connected with the LE pin of the latch U2, pins 32-39 are respectively connected with the input pins D7-D0 of the latch U2 correspondingly, and pins 21-28 are respectively connected with an address line A8-A15 of the memory chip U3, pins 17 are connected to an OE pin of the memory chip U3, a read enable signal pin OE of the static memory U6 and a clock driving circuit, pins 16 are connected to a write enable signal pin WE of the static memory U6 and a clock driving circuit, pins 1-3 are connected to address line pins A16-A18 of the memory chip U3, pins 8 are connected to a CE pin of the memory chip U3, a chip select signal pin CS2 of the static memory U6 and a clock driving circuit, the OE pin of the latch U2 is grounded, output pins Q2-Q2 are connected to address line pins A2-A2 of the memory chip U2, address line pins A2-A2 of the static memory U2 correspond to the address line pins A2-A2 of the memory chip U2 in parallel, data line pins DQ 4-D2 of the memory chip U2 and D2-D2 of the memory chip U2 are connected in parallel to the input pins D2-D2 of the latch U2, and the WE pin of the memory chip U3 is connected to VCC.

5. A music theory electronic organ for teaching purpose according to claim 4, wherein the music composing circuit comprises a music synthesizer U19 and a digital-to-analog converter U20, pin 20 of the music synthesizer U19 inputs midi signals, pin 24 is connected to 3V through a resistor R58, pin 3V through a diode D3 and ground through a capacitor C35, pin 23 is connected to 3V through a resistor R56, pin 19, pin 22, pin 8 and pin 5 are grounded, pin 9 and pin 21 are connected to 3V, pin 6 is grounded through a capacitor C53, pin 7 is grounded through a capacitor C54 and connected to pin 4 of a digital-to-analog converter U20, pin 6 and pin 7 are connected in parallel with a crystal oscillator XTAL1, pin 10 and pin 11 are connected to pin 3V and pin 1 of a digital-to analog-to-analog converter U20 respectively, pin 2 of the digital-to-analog converter U20 is connected to 3V through a resistor R57, pin 6 is grounded, pin 7 is connected to A3V, pin 5 is connected in series with a capacitor C5 and a resistor R61, the 8 pins are connected in series with a capacitor C6 and a resistor R62, the negative pole of the resistor 61 is connected with the power amplification circuit and is grounded through a capacitor C56, and the negative pole of the resistor R62 is connected with the power amplification circuit and is grounded through a capacitor C57.

6. A music theory electronic organ for teaching purpose according to claim 5, wherein said power amplifying circuit comprises operational amplifiers U21A and U21D, 2 pins of the operational amplifier U21A are connected with the negative pole of the resistor R16 through the resistor R12 and with MICOUT through the resistor R67, 3 pins are connected with 2.5V, 4 pins are connected with 5V, 11 pins are grounded, 1 pin is connected with 2 pins of the interface AOUT through the capacitor C15, and the 1 pin and the 2 pins are connected in parallel through the resistor R14, and the two ends of the resistor R14 are connected in parallel with the capacitor C14;

the 12 pins of the operational amplifier U21D are connected with 2.5V, the 13 pins are connected with the negative electrode of the resistor 62 through a resistor R13 and connected with MICOUT through a resistor R68, the 14 pins are connected with the 3 pins of the interface AOUT through a capacitor C16, the 13 pins and the 14 pins are connected in parallel through a resistor R16, two ends of a resistor R16 are connected with a capacitor 61 in parallel, and the interface AOUT is connected with an external loudspeaker.

7. A music theory electronic organ for teaching according to claim 6, wherein the clock driving circuit comprises a decoder U8, a NAND gate chip U7A and NOT gate chips U5B and U5C, a pin 1 of the NOT gate chip U7A is connected with a pin 17 of a main control chip U1, a pin 2 is connected with a pin 16 of the main control chip, a pin 3 is connected with a pin 6 of the decoder U8, and a pin 5 of the decoder U8 is connected with a pin 8 of the main control chip through the NOT gate chip U5B;

pins 1 and 16 of the nand gate chip U7A and a read enable signal pin OE of the static memory U6 are respectively connected with a pin 2 of the nand gate chip U7A and a write enable signal pin WE of the static memory U6, a pin 4 is connected with a chip select signal pin CS1 of the static memory U6 through the not gate chip U5C, a pin 1 is respectively connected with a pin Q0 of the latch U2, a pin a0 of the memory chip U3 and a pin a0 of the static memory U6, a pin 2 is respectively connected with a pin Q1 of the latch U2, a pin a1 of the memory chip U3 and a1 of the static memory U6, and a pin 3 is respectively connected with a pin Q3 of the latch U2, a pin A3 of the memory chip U3 and a pin A3 of the static memory U6, and pins 11-15 output CS0-CS 4.

8. A Lebang teaching electronic organ as claimed in claim 7, wherein said POWER supply circuit includes a POWER converter U22, a voltage regulator U23, diodes D4-D7, a loop formed by diodes D6 and D4 connected in series is connected in parallel with a loop formed by diodes D7 and D5 connected in series, the anode of D4 and the anode of D5 are both grounded, and the anode of D6 is connected to pin 2 of interface POWER1, the anode of D7 is connected to pin 1 of interface POWER 7, interface POWER 7 is connected to the external POWER line, the cathode output 9V of diode D7 is connected in parallel with the ground through a capacitor C7 and the pin 6 of POWER converter U7 through a resistor R7, pin 6 of POWER converter U7 is grounded through a capacitor C7 and is connected in parallel with pin 7 through resistors R7 and R7, resistors R7 and R7 are connected in parallel with the two ends of resistors R7, pin 8 and pin 1 of U7 are connected in parallel with pin 7, pin 3 is connected to pin C7 through a capacitor C7, pin is connected to ground, pin is connected to pin L7 through a ground, and pin L7 is connected to the ground through a resistor L7 and a resistor L is connected to the output pin 2 and a resistor R7 is connected to the pin, The R50 and the R63 are grounded, the pin 5 is connected with the anode of the resistor R63, the input end of the inductor L1 is grounded through a diode D8, and the output end of the inductor L1 is grounded through a capacitor C58;

the voltage stabilizer U23 is characterized in that a pin 1 inputs 9V, a pin 2 is grounded, a pin 3 outputs 5V, the pin is grounded through a capacitor C68 and resistors R10 and R11, a capacitor C63 and a capacitor C65 are respectively connected in parallel to two ends of the capacitor C68, a cathode of the resistor R10 outputs 2.5V, and the capacitor C12 and the capacitor C67 are respectively connected in parallel to two ends of the resistor R11;

the power supply circuit further comprises triodes Q2 and Q3, the base electrode of the triode Q2 is grounded through a light-emitting diode LED2 and an LED1, the collector electrode is connected with VDD, the emitter electrode outputs 3V, and a resistor R60 is connected between the base electrode and the collector electrode in parallel;

the base of the triode Q3 is grounded through the light emitting diode LED4 and the LED3, the collector inputs 5V, the emitter outputs A3V are grounded through the capacitor C64 and the capacitor C11, the resistor R79 is connected in parallel between the base and the collector, and the diode D11 is connected in parallel between the collector and the emitter.

9. A teaching musical theory electronic organ according to claim 8, wherein said scanning circuit includes flip-flops U9, U10, U11 and a connector CON26, the input pins D1-D8 of the flip-flop U9, the input pins D1-D8 of the flip-flop U10 and the input pins D1-D8 of the flip-flop U11 are respectively connected in parallel with the input pins D0-D7 of the latch U2, the output pins Q1-Q8 of the flip-flop U11, the output pins Q1-Q8 of the flip-flop U10 and the output pins Q1-Q8 of the flip-flop U9 are respectively connected with the pins 2-25 of the connector CON26, the pin 1 of the flip-flop U11 is connected with VCC, the pin 11 is connected with the pin CS0 through the NOT chip U5D, the pin 1 of the flip-flop U10 is connected with VCC, the pin 11 is connected with the pin CS1 through the NOT chip U5E, the pin 1 of the flip-flop U9 is connected with VCC, and the pin 11 is connected with the pin 2 through the NOT chip U5F.

10. A teaching music theory electronic organ according to claim 9, wherein the collection circuits include a first signal collection circuit, a second signal collection circuit and a power conversion circuit, wherein there are two said ferule, and the first signal collection circuit and the second signal collection circuit correspond to one ferule respectively;

the first signal acquisition circuit comprises operational amplifiers U17A-U17A, wherein a pin 2 at an input end of the operational amplifier U17A is connected with a pin 2 of an interface JB A through a resistor R A, a pin 3 is connected with VGND through a resistor R A, a pin 11 is grounded, a pin 4 is connected with the JB 5A, a pin 1 at an output end is connected with a pin 5 of the U17A through a resistor R A and a capacitor C A, a resistor R A is connected in parallel between the pin 1 and the pin 2, capacitors C A, C A and C A are connected in series between the resistor R A and the pin 2 of the interface JB A, a resistor R A and R A which are connected in series are connected in parallel between a positive pole of the capacitor C A and a negative pole of the C A, a negative pole of the resistor R A is grounded through a capacitor C A, a negative pole of the capacitor C A is grounded through a resistor R A, a negative pole of the resistor R A is connected in parallel between the negative pole of the operational amplifier U A and the pin 7, a negative pole of the operational amplifier U A is connected with the VGR A through a resistor ND through the resistor A, and the pin ND is connected with the resistor A through the resistor A, and the resistor ND through the resistor A, and the resistor VGR A, and the pin ND are connected through the resistor A, a resistor R30 is connected in parallel between the pin 6 and the pin 7, the pin 7 is connected with the pin 9 of the operational amplifier U17C through a capacitor C40 and a resistor R36, the pin 10 of the operational amplifier U17C is connected with VGND through a resistor R53, a capacitor C52 is connected in parallel between the pin 9 and the pin 8, the pin 8 is connected with the pin 13 of the operational amplifier U17D through a capacitor C41, two ends of the capacitor C52 are connected in parallel with a resistor R55 and a rheostat RV1 which are connected in series, the cathode of the capacitor C41 is grounded through a resistor R44 and connected with JB5V through a resistor R77, the pin 12 of the operational amplifier U17D is connected with VGND, the pin 14 outputs JB1, the pin 1 of the interface JB1 is grounded, and the pin 3 and the pin 4 output JB1UP and JB1DN respectively;

the second signal acquisition circuit comprises operational amplifiers U18A-U18A, wherein a pin 13 of an input end of the operational amplifier U18A is connected with a pin 2 of an interface JB A through a resistor R A, a pin 12 is connected with VGND through a resistor R A, a pin 14 of the output end is connected with a pin 10 of the U18A through a resistor R A and a capacitor C A, a resistor R A is connected in parallel between the pin 13 and the pin 14, capacitors C A, C A and C A are connected in series between the resistor R A and the pin 2 of the interface JB A, a resistor R A and R A connected in series are connected in parallel between a positive pole of the capacitor C A and a negative pole of the C A, a negative pole of the resistor R A is connected with ground through the capacitor C A, a negative pole of the capacitor C A is connected with the ground through the resistor R A, a negative pole of the resistor R A is connected with the VGND through the capacitor C A, a negative pole of the capacitor C A is connected with the pin ND through the resistor ND and the pin ND 9, and the pin ND are connected in parallel between the pin A and the pin ND 9, pin 8 is connected with pin 2 of operational amplifier U18A through capacitor C43 and resistor R42, pin 11 of operational amplifier U18A is grounded, pin 3 is connected with VGND through resistor R52, pin 4 is connected with JB5V, capacitor C51 is connected in parallel between pin 2 and pin 1, pin 1 is connected with pin 6 of operational amplifier U18B through capacitor C44, two ends of capacitor C51 are connected in parallel with resistor R54 and rheostat RV2 which are connected in series, the negative pole of capacitor C44 is grounded through resistor R45 and connected with JB5V through resistor R78, pin 5 of operational amplifier U18B is connected with VGND, pin 7 outputs JB2, pin 1 of interface JB2 is grounded, and pin 3 and pin 4 output JB2UP and JB2DN respectively;

the power supply conversion circuit comprises resistors R9, R46, R47, capacitors C13 and C50, a resistor R9 is connected in series with the capacitor C13, the anode of the resistor R9 is input with VCC, the cathode of the resistor R9 is output with JB5V, the cathode of the capacitor C13 is grounded, the resistor R46 is connected in series with the resistor R47, the capacitor C50 is connected in parallel with two ends of the resistor R47, the anode of the resistor R46 is input with JB5V, and the cathode of the resistor R46 is output with VGND;

the scanning and picking circuit comprises a pointer receiving circuit and a pointer lifting sound control circuit;

the pointer receiving circuit comprises a driving signal chip U12 and a counter U12, wherein a pin 1 and a pin 19 of the driving signal U12 are connected in parallel and then are connected with a pin 12 of a decoder U12, output pins 1Y 12-1Y 12, 2Y 12-2Y 12 and output pins 1Y 12-1Y 12 and 2Y 12-2Y 12 of the U12 are respectively connected with an input pin D12-D12 of the latch U12 in parallel, input pins 1A 12-1A 12 of the driving signal chip U12 are respectively connected with output pins Q12-Q12 of the counter U14 12, input pins 2A 12-2A 12 are respectively connected with output pins Q12-Q12 of the counter U14 12, a reset input pin is connected with a reset input pin of the U14 in parallel and is connected with a pin 7 of the main control chip U12, and a clock input pin JB 12 of the U14 JB 12 is connected with a 12;

the pointer lifting tone control circuit comprises a driving signal chip U13, wherein a pin 1 and a pin 19 of the driving signal chip U13 are connected in parallel and then connected with a pin 11 of a decoder U8, an input pin IA1 is connected with VCC through a resistor R2, is grounded through a capacitor C7 and is connected with JB2UP, the input pin IA2 is connected with VCC through a resistor R3, is grounded through a capacitor C8 and is connected with JB2DN, an input pin IA3 is connected with VCC through a resistor R4, is grounded through a capacitor C9 and is connected with JB1UP, the input pin IA4 is connected with VCC through a resistor R5, is grounded through a capacitor C10 and is connected with JB1DN, and output pins IY1-2Y4 are connected in parallel with input pins D0-D7 of a latch U2 respectively.

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