CN114528794B - Fractional order chaotic circuit design method based on hybrid memristor - Google Patents
Fractional order chaotic circuit design method based on hybrid memristor Download PDFInfo
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Abstract
A fractional order chaotic circuit design method based on a hybrid memristor is a five-dimensional integer order hybrid memristor circuit constructed by a magnetic control memristor and a charge control memristor, wherein a magnetic control memristor model contains a square root algorithm and an absolute value algorithm, and the charge control memristor is a novel generalized memristor model. According to the fractional calculus Grunwald-Letnikov definition, a fractional mixed memristor chaotic circuit model is deduced from an integer-order circuit model, and a 0-1 test, SALI detection, lyapunov index and a complexity method are adopted to verify that the fractional circuit has complex nonlinear dynamics behavior; the FPGA technology is combined, the fractional order mixed memristor chaotic model with the same order and different orders is designed, the hardware simulation is consistent with the numerical calculation result, and the method has wide application potential in the fields of complex dynamics and digital circuits.
Description
Technical Field
The invention belongs to the technical field of nonlinear chaotic dynamics and digital circuits, and relates to memristors, fractional order chaotic theory and fractional order chaotic circuit design and simulation implementation.
Background
Memristors are the fourth basic element of circuits, except capacitance, inductance, resistance, which describe charge q and magnetic fluxRelationship between them. In 1971, chua predicted the existence of memristor elements in theory according to the completeness principle of basic variable combinations in the circuit, and described the basic characteristics and functions of the memristor systematically. Successful physical implementation of nanoscale memristors was reported in the hewlett-packard laboratory in 2008 by Strukov. With the intensive research on memristors, the theory is expanded. Meanwhile, various types of memristor models are also researched, such as a generalized boundary condition memristor model, a magnetic control/electric control memristor model, a smooth generalized nonlinear memristor model, an exponential memristor model and the like. Memristors have nonlinear characteristics, and can generate chaotic behaviors in dynamic systems, wherein the chaotic behaviors depend on the number of positive Liidepunofu indexes, bifurcation diagrams, 0-1 testing methods, SALI detection and complexity and the like.
In recent years, with the intensive research of fractional calculus, a fractional chaotic system has attracted great interest to many researchers, and it can more accurately describe inherent characteristics and physical characteristics. By expanding the research of integer-order systems to fractional-order chaotic systems, various types of fractional-order chaotic systems have been proposed, such as a novel fractional-order chaotic system with two balances and no balances, a novel fractional-order hyperchaotic memristor oscillator, a fractional-order unbalanced chaotic system, a novel fractional-order chaotic system based on a fractional memristor, a novel variable-order fractional-order chaotic system, and the like. The analog circuit realizes that the chaotic system is influenced by external environment, such as temperature and the like, and meanwhile, the memristive chaotic circuit is extremely sensitive to circuit parameters and initial states, and the FPGA technology has the advantages of large capacity, high reliability, low power consumption and the like, and a mode of realizing the chaotic system and the fractional order chaotic system by adopting the digital circuit is more reliable and accurate. Many researchers have implemented digitization of chaotic systems and fractional order chaotic systems using FPGA technology, for example, FPGA implementation of fractional order Liu system, FPGA implementation of fractional order four-wing chaotic system, FPGA implementation of fractional order memristive chaotic system, and so on.
Disclosure of Invention
The invention aims to provide a fractional order chaotic circuit based on a hybrid memristor and an FPGA design method, wherein a five-dimensional integer order chaotic circuit is constructed by utilizing a charge-controlled memristor, an inductor, two capacitors, a resistor and a magnetic control memristor, so that nonlinear dynamics behavior of the model is analyzed; deducing a fractional order model from the integer order model, finding out that the integer order model has rich chaos phenomenon through numerical simulation, and researching the chaos characteristics and the complexity of the integer order model; finally, the fractional order mixed memristor circuit with the same fractional order and different fractional orders is designed by combining with the FPGA technology, and the fractional order mixed memristor circuit has wide application potential in the fields of nonlinear dynamics systems and safety communication.
The invention is realized by the following technical scheme.
The invention discloses a fractional order chaotic circuit design method based on a hybrid memristor, which comprises the following steps:
(S01): constructing a five-dimensional integer order memristor circuit model formed by mixing a magnetic control memristor and a charge control memristor;
(S02): numerical simulation (S01) of a nonlinear evolution track of an integer-order circuit model, and analyzing memristor chaotic characteristics of the hybrid memristor;
(S03): according to fractional calculus Grunwald-Letnikov definition, a five-dimensional fractional mixed memristor chaotic circuit model is deduced by combining (S01) an integer mixed memristor chaotic circuit model;
(S04): performing numerical simulation and complexity analysis on the (S03) fractional order mixed memristor chaotic circuit model, and verifying the existence of a chaotic phenomenon;
(S05): performing frequency domain-time domain conversion on the (S03) fractional order mixed memristor chaotic circuit by using a frequency domain method, and designing mixed memristor chaotic digital discrete models with the same fractional order and different fractional orders by using a DSP Builder technology;
(S06): and (S05) designing an FPGA input/output control submodule for the same-order and different-order digital discrete models, and adopting an FPGA development board and a digital-to-analog conversion board to realize the chaotic attractor same as the numerical calculation so as to verify the feasibility of the hardware system.
The step (S01) is to construct a five-dimensional integer order memristor circuit model formed by mixing a magnetic control memristor and a charge control memristor, and the method comprises the following steps of;
1) Designing an integer-order mixed memristor circuit diagram, and according to KVL and KCL theorem of kirchhoff, the circuit model expression is as follows:
Wherein V 1,V2 is voltage, i L is inductance current, q is charge quantity of the charge-controlled memristor, Magnetic flux of the magnetic control memristor, C 1,C2 is capacitance, L is inductance, R is resistance,/>The magnetic control memory guide is represented by M (q) as the charge control memory guide;
2) Magnetic flux The formed magnetic control memristor model is as follows:
Wherein v is voltage, i is current, and a 1,a2,a3,a4,a5 is internal parameter of the magnetic memristor;
3) The charge control memristor model formed by the charges q is as follows:
wherein v is voltage, i is current, and b 1,b2,b3,b4,b5,b6 is the internal parameter of the charge-controlled memristor;
4) Substituting the formulas (2) and (3) into the formula (1), and integrating the magnetic control memristor and the charge control memristor model to obtain a complete five-dimensional mixed memristor circuit model, namely:
The invention is characterized in that: in the constructed five-dimensional integer-order mixed memristor chaotic circuit, the magnetic control generalized memristor comprises a square root algorithm and an absolute value algorithm, and meanwhile, the load control memristor is a novel generalized memristor model; the Lyapunov index, bifurcation diagram, poincare diagram and characteristic curves of the magnetic control and charge control memristors of the integer-order mixed memristor chaotic circuit are researched, and the circuit is verified to have rich nonlinear dynamics behaviors; the fractional order mixed memristor chaotic circuit defined by Grunwald-Letnikov is subjected to numerical simulation; the method verifies that the fractional order mixed memristor chaotic circuit has complex chaotic characteristics by adopting a 0-1 test, SALI detection, lyapunov index and a complexity method; the DSP Builder technology and the FPGA technology are used for designing the mixed memristor chaotic circuit with the same order and different orders and fractions, and the consistency with the numerical simulation result is verified.
Drawings
FIG. 1 is a five-dimensional integer-order hybrid memristor chaotic circuit constructed in the present invention.
Fig. 2 is a graph of chaotic attractor trajectories for five different variables (x, y, z, w, u) of the present invention.
FIG. 3 is a Lyapunov exponent spectra of the integer-order hybrid memristor chaotic circuit of the present invention, with a small diagram nested in a large diagram being an enlarged diagram of a small virtual frame at the upper right corner of the large diagram.
FIG. 4 is a diagram of the chaotic characteristics of the integer-order hybrid memristor chaotic circuit of the present invention. Wherein, (a) is a Lyapunov exponent spectrum varying with the parameter b 2, (b) is a bifurcation diagram varying with the parameter b 2, and (c) is an x-u poincare diagram with y=0.
FIG. 5 is a graph of the characteristics of a magnetic memristor constructed in accordance with the present invention. Wherein, (a) is a v-i characteristic curve with frequency, and (b) is a v-i characteristic curve with amplitude.
FIG. 6 is a graph of characteristics of a charge-controlled memristor constructed in accordance with the present invention. Wherein (a) is an i-v characteristic curve with respect to frequency, and (b) is an i-v characteristic curve with respect to amplitude.
FIG. 7 is a state trace diagram of the same-order fractional order hybrid memristor chaotic circuit of the present disclosure. Wherein, (a) is a state trace of q i =0.925 (i=1, 2,3,4, 5), (b) is a state trace of q i =0.875 (i=1, 2,3,4, 5), (c) is a state trace of q i =0.78 (i=1, 2,3,4, 5), and (d) is a state trace of q i =0.74 (i=1, 2,3,4, 5).
FIG. 8 is a state trace diagram of a different order fractional order hybrid memristor chaotic circuit of the present invention. Wherein, (a) is the state trace of (q 1,q2,q3,q4,q5) = (0.51,0.95,0.95,0.95,0.85), (b) is the state trace of (q 1,q2,q3,q4,q5) = (0.5,0.95,0.95,0.95,0.85), (c) is the state trace of (q 1,q2,q3,q4,q5) = (0.9,0.5,0.7,0.95,0.85), (d) is the state trace of (q 1,q2,q3,q4,q5) = (0.9,0.95,0.95,0.95,0.85), (e) is the state trace of (q 1,q2,q3,q4,q5) = (0.9,0.45,0.95,0.95,0.85), (f) is the state trace of (q 1,q2,q3,q4,q5) = (0.9,0.95,0.63,0.95,0.85), (g) is the state trace of (q 1,q2,q3,q4,q5) = (0.9,0.95,0.95,0.8,0.85), and (h) is the state trace of (q 1,q2,q3,q4,q5) = (0.9,0.95,0.95,0.95,0.05).
Fig. 9 shows the relationship between the z-w state diagram and the 0-1 test result when the same order q i =0.95 (i=1, 2,3,4, 5) is adopted in the present invention, wherein (a) is the z-w state diagram (b 5 = -9), (b) is the z-w state diagram (b 5 = -7), (c) is the 0-1 test result of b 5 = -9, and (d) is the 0-1 test result of b 5 = -7.
Fig. 10 is a SALI detection chart of b 5 = -9 and b 5 = -7 when the same order q i =0.95 (i=1, 2,3,4, 5) of the present invention.
Fig. 11 is a Lyapunov exponent spectra of the same order q i =0.925 (i=1, 2,3,4, 5) using the FDE12 algorithm according to the present invention.
Fig. 12 is a graph of complexity as a function of parameter b 5 for the same order q i =0.95 (i=1, 2,3,4, 5) of the present invention. Wherein, (a) is SE complexity and (b) is C 0 complexity.
Fig. 13 is a graph of the complexity of the present invention as a function of the parameter q i (i=1, 2,3,4, 5). Wherein, (a) is SE complexity and (b) is C 0 complexity.
Fig. 14 is a complex chaotic phase diagram of the present invention with b 5 -q as a reference plane. Wherein, (a) is a complex chaotic phase diagram of SE complexity, and (b) is a complex chaotic phase diagram of C 0 complexity.
Fig. 15 is a graph of parameter values of a fractional order hybrid memristor chaotic circuit model (14) constructed in the present invention when the same order q i =0.925 (i=1, 2,3,4, 5).
Fig. 16 is a graph of parameter values of a fractional order hybrid memristor chaotic circuit model (15) constructed according to the present invention at different orders (q 1,q2,q3,q4,q5) = (0.9,0.95,0.95,0.95,0.85).
Fig. 17 is a same-order q i =0.925 (i=1, 2,3,4, 5) fractional order hybrid memristive chaotic digital circuit model of the DSP Builder design of the present invention.
Fig. 18 is a fractional order hybrid memristive chaotic digital circuit model of different orders (q 1,q2,q3,q4,q5) = (0.9,0.95,0.95,0.95,0.85) of the DSP Builder design of the present invention.
FIG. 19 is a diagram showing the connection of an FPGA development board, a digital-to-analog conversion board and an oscilloscope constructed by the invention.
Fig. 20 is a 14-bit precision chaotic attractor trace of the equal-order q i =0.925 (i=1, 2,3,4, 5) fractional order hybrid memristor chaotic circuit designed by the FPGA of the present invention. Wherein, (a) is a chaotic attractor track of x-y, (b) is a chaotic attractor track of z-w, (c) is a chaotic attractor track of y-w, and (d) is a chaotic attractor track of x-u.
Fig. 21 is a 14-bit precision chaotic attractor trace of a fractional order mixed memristor chaotic circuit of different orders (q 1,q2,q3,q4,q5) = (0.9,0.95,0.95,0.95,0.85) designed by the FPGA of the present invention. Wherein, (a) is a chaotic attractor track of x-y, (b) is a chaotic attractor track of z-w, (c) is a chaotic attractor track of y-w, and (d) is a chaotic attractor track of x-u.
Detailed Description
The present invention will be described in further detail below with reference to the drawings and examples.
Example 1: and (3) nonlinear evolution track and memristor chaotic characteristic analysis of an integer-order mixed memristor circuit design and an integer-order circuit model.
The integral-order mixed memristor circuit diagram is shown in fig. 1, and is a mixed memristor composed of a magnetic control memristor and a charge control memristor, and a resistor R, an inductor L and two capacitors C 1 and C 2 form a complete analog circuit, wherein corresponding circuit equations are obtained according to KVL and KCL theorem of kirchhoff, namely a formula (1), a magnetic control memristor model and a charge control memristor model are respectively described in formulas (2) and (3), and a five-dimensional mixed memristor circuit model constructed by the invention is described in a formula (4).
1) Selecting x (t) =v 1(t),y(t)＝V2(t),z(t)＝iL (t), w (t) =q (t),Meanwhile, setting parameters R＝1,α＝1/C1＝3,β＝1/C2＝7.8,γ＝1/L＝27,a1＝15,a2＝-1.5,a3＝2,a4＝-1, a5＝1,b1＝-0.5,b2＝-2.6,b3＝2,b4＝1,b5＝-9,b6＝1, to construct a five-dimensional integer-order circuit model, namely converting the formula (4) into:
Fig. 2 shows chaotic attractor state diagrams of five different variables (x, y, z, w, u) in the formula (5), fig. 3 shows a Lyapunov index diagram of an integer-order hybrid memristive chaotic circuit, and fig. 4 (a), (b), and (c) show a Lyapunov index diagram as a function of a parameter b 2, a bifurcation diagram as a function of a parameter b 2, and a poincare diagram with y=0, respectively.
2) Selecting an input voltage v=asin (2pi f 1 t), a characteristic curve of the magnetic memristor on the V-i plane can be obtained, fig. 5 (a) shows a characteristic curve with different frequency f 1＝0.056Hz,f1＝0.11Hz,f1 =0.5 Hz when the amplitude a=1v, and fig. 5 (b) shows a characteristic curve with different amplitude a=0.5v, a=0.8v and a=1v when the frequency f 1 =0.11 Hz; whereas, when the input current is i=bsin (2pi f 2 t), a characteristic curve of the charge-controlled memristor on the i-v plane can be obtained, fig. 6 (a) shows a characteristic curve at different frequencies f 2＝2Hz,f2＝8Hz, f2 =18 Hz, and fig. 6 (B) shows a characteristic curve at different amplitudes b=0.5a, b=1a, b=1.3a, when the frequency f 2 =2 Hz.
Example 2: and constructing a five-dimensional fractional order mixed memristor chaotic circuit model.
1) Fractional calculus Grunwald-Letnikov (GL) is defined as:
wherein Γ (·) is a Gamma function, n-1 is not less than q is not more than n, q is fractional order, and n is an integer.
2) According to the integer-order mixed memristor chaotic circuit model (5) in embodiment 1, a five-dimensional fractional-order mixed memristor chaotic circuit model can be obtained by adopting GL definition, namely:
Where q i (i=1, 2,3,4, 5) is the fractional order.
Example 3: and carrying out numerical simulation, chaotic characteristic and complexity analysis on the fractional order mixed memristor chaotic circuit.
1) Using Matlab numerical simulations, fig. 7 (a) to (d) can be obtained, which respectively show the state trace diagrams of the same fractional order:
● q i =0.925 (i=1, 2,3,4, 5) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -, - -fig. 7 (a)
● Q i = 0.875 (i = 1,2,3,4, 5) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -, fig. 7 (b)
● Q i =0.78 (i=1, 2,3,4, 5) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -, - -fig. 7 (c)
● Q i =0.74 (i=1, 2,3,4, 5) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -, - -FIG. 7 (d)
2) Likewise, using Matlab numerical simulations, fig. 8 (a) to (h) can be obtained, which respectively show state trajectories of different orders:
(q 1,q2,q3,q4,q5) = (0.51,0.95,0.95,0.95,0.85) - - - - - - - - - - - - - - - - - - -, fig. 8 (a) was obtained
(Q 1,q2,q3,q4,q5) = (0.5,0.95,0.95,0.95,0.85) - - - - - - - - - - - - - - - - - -, fig. 8 (b) was solid-phase @
(Q 1,q2,q3,q4,q5) = (0.9,0.5,0.7,0.95,0.85) - -, fig. 8 (c)
(Q 1,q2,q3,q4,q5) = (0.9,0.95,0.95,0.95,0.85) - -, fig. 8 (d)
(Q 1,q2,q3,q4,q5) = (0.9,0.45,0.95,0.95,0.85) - -, fig. 8 (e)
(Q 1,q2,q3,q4,q5) = (0.9,0.95,0.63,0.95,0.85) - - - - - - - - - - - - - - - - - -, fig. 8 (f) was solid-phase
(Q 1,q2,q3,q4,q5) = (0.9,0.95,0.95,0.8,0.85) - -, fig. 8 (g)
(Q 1,q2,q3,q4,q5) = (0.9,0.95,0.95,0.95,0.05) - - - - - - - - - - - - - - - - - - -, fig. 8 (h) was solid-phase
3) B 5 is selected as a reference parameter, and chaotic characteristic detection is carried out on the fractional order mixed memristor chaotic circuit through a 0-1 test method, a SALI detection method and an FDE12 algorithm.
Fig. 9 (a), (b), (c), (d) show the state diagram of z-w at b 5 = -9, z-w at b 5 = -7, the 0-1 test result of b 5 = -9, and the 0-1 test result of b 5 = -7, respectively, when q i = 0.95 (i = 1,2,3,4, 5).
Fig. 10 shows the corresponding SALI detection result of b 5＝-9,b5 = -7 when q i = 0.95 (i = 1,2,3,4, 5).
Fig. 11 shows the Lyapunov exponential spectrum of fractional order q i =0.925 (i=1, 2,3,4, 5), verifying the chaotic behavior of the fractional order hybrid memristive chaotic circuit.
4) According to the definition of SE complexity and C 0 complexity, b 5 is chosen as a reference parameter, and in fractional order q i =0.95 (i=1, 2,3,4, 5), it can be seen that fig. 12 (a) and (b) show SE complexity and C 0 complexity as a function of b 5, respectively; taking fractional order q i (i=1, 2,3,4, 5) as a reference parameter, at parameter b 5 = -9, it can be observed that fig. 13 (a), (b) show SE complexity and C 0 complexity as a function of q i (i=1, 2,3,4, 5), respectively; assuming b 5 -q as the reference plane, fig. 14 (a), (b) show complex chaos plots of SE complexity and C 0 complexity.
Example 4: and designing mixed memristor chaotic digital discretization models with the same fraction order and different fraction orders.
1) According to the Laplace frequency domain conversion property (8), frequency domain conversion is carried out on the fractional order mixed memristor chaotic circuit (7), so that the fractional order mixed memristor chaotic circuit in a frequency domain form can be obtained, namely:
Wherein,
Q(s)＝L[q(t)]＝L[z(t)w(t)]，
R(s)＝L[r(t)]＝L[z(t)w(t)w(t)],
O(s)＝L[o(t)]＝L[z(t)z(t)],
V(s)＝L[v(t)]＝L[x(t)u(t)]。
2) The frequency domain method is adopted to carry out time domain conversion on the frequency domain fractional order mixed memristor chaotic circuit, and a conversion function 1/s 0.95,1/s0.925,1/s0.9,1/s0.85 with the approximation error of 3dB is selected, namely:
let x 1 be =x, y1＝y,/>z1＝z,/>w1＝w,/>u1＝u,/>Substituting the formula (11) into the formula (9) can obtain the same-order fractional order mixed memristor chaotic circuit with time domain, namely:
The corresponding parameter values of group a, group B, group C, group D, and group E are shown in fig. 15.
Let x 1 be =x,y1＝y,/>z1＝z,/>w1＝w,/>u1＝u, Substituting the formulas (11), (12) and (13) into the formula (9) can obtain the time-domain different-order fractional order hybrid memristor chaotic circuit, namely:
the corresponding parameter values of group a, group B, group C, group D, and group E are shown in fig. 16.
3) The time-domain same-order fractional order hybrid memristor chaotic circuit (14) is realized as a digital circuit through an Euler algorithm, namely:
Where the sampling interval Δt=1×10 -4. Digital circuit design is carried out on the model (16) by using a DSP Builder technology, and figure 17 shows a mixed memristor chaotic digital circuit with the same order q i =0.925 (i=1, 2,3,4, 5),
The MATLAB/Simulink DSP Builder technology can implement an algorithm stage as a register conversion (RTL) stage, and design a model (16) by using an adder module, a multiplier module, a digital integration module, a square root module, an absolute value module, a bus module, an input/output module, a constant module, a gain module, a Signal Compiler module and the like in a DSP Builder library.
4) The same euler algorithm is adopted to realize the time-domain different-order fractional order mixed memristor chaotic circuit (15) as a digital circuit, the sampling interval is deltat=1×10 -4, the digital circuit design is carried out on the model (17) by utilizing the DSP Builder technology, fig. 18 shows the different-order (q 1,q2,q3,q4,q5) = (0.9,0.95,0.95,0.95,0.85) fractional order mixed memristor chaotic digital circuit, and the different-order fractional order mixed memristor chaotic digital circuit model is as follows:
Example 5: the FPGA realization of the mixed memristor chaotic digital circuit model with the same order and different orders is realized.
1) And converting the mdl file of the fractional order mixed memristor chaotic digital circuit into the VHDL file of the Quartz II software by using a Signal Compiler module in a DSP Builder library, analyzing, compiling and synthesizing the generated quartz II engineering project, designing a corresponding key output module and an output control module by using a Verilog HDL language, integrating all modules, and generating a complete fractional order mixed memristor chaotic digital circuit engineering.
2) And converting the mdl file into a VHDL file by using a Signal Compiler module, analyzing, compiling and synthesizing the file by using a quatus II software, designing a corresponding key output module, an output control module and a frequency division module, arranging all the modules, and connecting an FPGA development board, a digital-analog conversion board and an oscilloscope in a matching way.
3) Fig. 19 is a diagram showing a 14-bit-precision chaotic attractor trace presented by an oscilloscope when the sof file is burned into an FPGA development board when q i =0.925 (i=1, 2,3,4, 5) is the same order, as shown in fig. 20.
3) 14-Bit precision chaotic attractor track of different-order (q 1,q2,q3,q4,q5) = (0.9,0.95,0.95,0.95,0.85) fractional order mixed memristor chaotic circuit is shown in fig. 21. Obviously, the FPGA design of the mixed memristor chaotic circuit with different orders and fractions is more complex, and the emphasis is that the system (9) in the frequency domain form is approximated to the system (15) in the time domain through different frequency domain conversion functions.
According to the invention, an FPGA development board adopts a Cyclone IV series EP4CE115F29C7N chip, meanwhile, a digital-to-analog conversion board is a 14-bit high-performance high-speed double-channel digital-to-analog conversion chip AD9767, the clock frequency of the AD9767 and the clock frequency of the FPGA chip are synchronous to 50MHz, a sof file generated through Quartus II compiling is downloaded into the FPGA development board, and a corresponding output graph can be observed through an oscilloscope. Because the digital-to-analog conversion bit is 14 bits, the hardware experimental result and the digital simulation result are very identical and consistent as a whole, which shows that the fractional FPGA design of the invention can be practically applied in the future.
Claims (1)
1. A design method of a fractional order chaotic circuit based on a hybrid memristor is characterized by comprising the following steps:
(S01): constructing a five-dimensional integer order memristor circuit model formed by mixing a magnetic control memristor and a charge control memristor;
(S02): numerical simulation (S01) of a nonlinear evolution track of an integer-order circuit model, and analyzing memristor chaotic characteristics of the hybrid memristor;
(S03): according to fractional calculus Grunwald-Letnikov definition, a five-dimensional fractional mixed memristor chaotic circuit model is deduced by combining (S01) an integer mixed memristor chaotic circuit model;
(S04): performing numerical simulation and complexity analysis on the (S03) fractional order mixed memristor chaotic circuit model, and verifying the existence of a chaotic phenomenon;
(S05): performing frequency domain-time domain conversion on the (S03) fractional order mixed memristor chaotic circuit by using a frequency domain method, and designing mixed memristor chaotic digital discrete models with the same fractional order and different fractional orders by using a DSP Builder technology;
(S06): performing FPGA input/output control submodule design on the (S05) same-order and different-order digital discrete models, and adopting an FPGA development board and a digital-to-analog conversion board to realize the chaotic attractor same as numerical calculation so as to verify the feasibility of hardware system realization;
the step (S01) is to construct a five-dimensional integer order memristor circuit model formed by mixing a magnetic control memristor and a charge control memristor, and the method comprises the following steps:
1) Designing an integer-order mixed memristor circuit diagram, and according to KVL and KCL theorem of kirchhoff, the circuit model expression is as follows:
Wherein V 1,V2 is voltage, i L is inductance current, q is charge quantity of the charge-controlled memristor, Magnetic flux of the magnetic control memristor, C 1,C2 is capacitance, L is inductance, R is resistance,/>The magnetic control memory guide is represented by M (q) as the charge control memory guide;
2) Magnetic flux The formed magnetic control memristor model is as follows:
Wherein v is voltage, i is current, and a 1,a2,a3,a4,a5 is internal parameter of the magnetic memristor;
3) The charge control memristor model formed by the charges q is as follows:
wherein v is voltage, i is current, and b 1,b2,b3,b4,b5,b6 is the internal parameter of the charge-controlled memristor;
4) Substituting the formulas (2) and (3) into the formula (1), and integrating the magnetic control memristor and the charge control memristor model to obtain a complete five-dimensional mixed memristor circuit model, namely:
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| CN107947914A (en) * | 2017-12-25 | 2018-04-20 | 西安理工大学 | A kind of chaos circuit based on fractional order memristor |
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