CN1145211C - Polycrystal chip semiconductor package structure and making method - Google Patents

Polycrystal chip semiconductor package structure and making method Download PDF

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Publication number
CN1145211C
CN1145211C CNB981193471A CN98119347A CN1145211C CN 1145211 C CN1145211 C CN 1145211C CN B981193471 A CNB981193471 A CN B981193471A CN 98119347 A CN98119347 A CN 98119347A CN 1145211 C CN1145211 C CN 1145211C
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wafer
significant surface
semiconductor package
circuit
pin
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CN1248795A (en
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���ڽ���
陈宗杰
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DAZHONG COMPUTER Co Ltd
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DAZHONG COMPUTER Co Ltd
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
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    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Lead Frames For Integrated Circuits (AREA)

Abstract

The present invention relates to a structure and a manufacture method for packaging a semiconductor with multiple wafers. Two wafers are stacked in the same IC element by simultaneously combining LOC technology and BGA technology. One wafer becomes an interface by pins of a conducting wire frame, and is used for a circuit on the wafer to be connected with the outside. The other wafer becomes an interface by welding balls, and is used for a circuit on the wafer to be connected with the outside. The two wafers are supported and fixed by the conducting wire frame. The base plate element required by the publicly known BGA technology can be saved. The two wafers can respectively have different functions, and can also have the same function. The integral structure is simple, the manufacture is easy, and the cost is low. Compared with the publicly known technology, the integral area and the length of the IC element are reduced.

Description

A kind of polycrystal chip semiconductor package structure
Technical field
The invention relates to a kind of polycrystal chip semiconductor package structure.Especially refer to a kind of can be in same packing with the wafer stacking of identical or different function more than two, and one of them wafer be with the pin of lead frame as with the interface of external world's binding, another wafer then with the tin ball as with the polycrystal chip semiconductor package structure of the interface of external world's binding.
Background technology
In the trend that semiconductor is made now, how can in the little package semiconductor of healing, clamp-on logical circuit the more and cost can reduce relatively, be the global semiconductor practitioner the consistent problem of research with all strength, so the research in this field, competition are also so very fierce.The smallest elements size of circuit design, another kind can directly reach the mode of the memory capacity multiplication of single package semiconductor with least cost, is the wafer of clamp-oning in same packing more than two on dwindling wafer.
Figure 1 shows that an example of known polycrystal chip semiconductor package structure.Its mainly be by " on the pin in wafer (Lead On Chip; Abbreviation LOC) " technology is incorporated into two wafer 1a, 1b respectively on two lead frame 3a, the 3b with hot melt two- sided tape 2a, 2b; and weld the corresponding pin of the last circuit of (Bonding) coupled wafers 1a, 1b and lead frame 3a, 3b respectively with gold thread 4a, 4b (Gold Wire) after; again the pin on the lead frame 3a is set up on the pin 6 that is connected in lead frame 3b, pour into the semiconductor encapsulated element (IC) that potting resin 5 (Molding) is configured as one at last again.This kind merely is used as the circuit on a plurality of wafer 1a, the 1b and the disadvantage of extraneous UNICOM interface with the pin 6 of lead frame, be that therefore pin 6 quantity also must double, thereby cause [length] of this semiconductor encapsulated element will increase many because of the increase of pin number.Recently, the pin number of tradition single-chip potted element (for example 4MB DRAM IC) by 20 pin in past, 30 pin increase to gradually at present popular 42 pin even the IC of 50 pin, because each pin all has its fixing width, therefore make the length of present IC element also constantly extend, strengthen, if adopt known technology as shown in Figure 1 to carry out polycrystalline sheet encapsulation IC, then the quantity of its pin will even can reach 80 or even 100 more than the pin, its IC will certainly be long and seem practical not to the utmost.
As shown in Figure 2, the example of another kind of known polycrystal chip semiconductor package structure is to adopt [solder ball array contact (Ball Grid Array; Abbreviation BGA)] mutually combining two wafer 7a, 7b with elargol (often being called EPOXY) after, technology sticks in again on the substrate 8, and weld the corresponding weld pad of last circuit of (Bonding) coupled wafers 7a, 7b and substrate 8 respectively with gold thread 9a, 9b (GoldWire) after, via the circuit design on the substrate 8 or penetrate the conductive plugs design of substrate 8, the circuit that wafer 7a, 7b is last sees through gold thread 9a, 9b and connects on the corresponding tin ball 10 that is coupled in substrate 8 bottom surfaces, is configured as the semiconductor encapsulated element (IC) of one.This kind is used as the disadvantage of last circuit of a plurality of wafer 7a, 7b and extraneous UNICOM interface merely with the tin ball 10 on the substrate 8 of BGA technology, the area that is this substrate 8 will increase many, make that the area of this semiconductor encapsulated element is very big, and on manufacture craft, also inconvenience is arranged and be difficult to carry out.Because the technology of BGA all is that employing one substrate 8 supports, fixed wafer now, in substrate 8 back of the body (end) faces the contact that the tin ball becomes the signal transmission is set again.So the area of substrate is general, and the size than actual wafer is big much, adding piling up of polycrystalline sheet will more directly cause the increase of tin nodule number amount and the expansion of substrate area, will therefore reduce many on practicality.Another defective that this kind piles up the polycrystalline sheet with the BGA technology merely, it is the difficulty on the manufacture craft, the structure shown in Fig. 2 for example, the gold thread 9a that is connected between wafer 7a and the substrate 8 on it almost is the double length of gold thread 9b, long gold thread 9a will be very difficult to welding and more very easily because of external force or overheated (because of resistance value bigger) break; And in this kind structure, the size of wafer 7a must than wafer 7b littler and can't effective two same sizes or the wafer of specification pile up, cause the difficulty in the design; In addition, long and intensive gold thread 9a, 9b also usually can packed resin thrust to get loose and cause opening circuit when carrying out the process for filling colloid into of potting resin, so in practice very unfeasible (product percent of pass is low excessively).
So in fact aforementioned various known technologies can't satisfy aforementioned semiconductor element size and future trend that reduces cost and the demand of dwindling fully, can be for improving and still leave a space.
Summary of the invention
The present invention's main purpose promptly is to provide a kind of polycrystal chip semiconductor package structure and method for making, not only simple in structure, make easily, cost is lower, and the entire area of IC element, length all can more be dwindled than known technology.
Another object of the present invention is to provide a kind of polycrystal chip semiconductor package structure and method for making, by merging LOC technology and BGA technology two plates is stacked in the same IC element, not only overcome the many disadvantages of aforementioned known technology, and this two plates also can have different functions respectively, also can have identical functions.
In order to achieve the above object, in the preferred embodiment of polycrystal chip semiconductor package structure of the present invention, include at least two wafers (i.e. one first wafer and one second wafer), one has the lead frame of a plurality of pins, a plurality of tin balls and potting resin.Each wafer all has a significant surface and a non-significant surface, and is equipped with a plurality of connection gaskets to become the interface of circuit and extraneous binding on the wafer on the significant surface of each wafer.A plurality of connection gaskets on the significant surface of second wafer are to be coupled in respectively on the corresponding pin by a technological means, and the non-significant surface of first wafer is to be incorporated on the lead frame.These a plurality of tin balls directly are arranged on the significant surface of this first wafer on corresponding a plurality of connection gaskets.This potting resin then is to be used to coat aforementioned wafer and the semiconductor package that becomes one, and these a plurality of pins and tin ball are that to be exposed to potting resin outer to become the interface with extraneous binding.Because the present invention's polycrystal chip semiconductor package structure does not have the setting (two plates is to be subjected to lead frame institute support fixation) of known BGA substrate, therefore the area of IC element can greatly reduce, also because two plates is to utilize pin and tin ball to be used as contact respectively, therefore its pin number can be not too much yet, the length of IC element can be shorter, and the present invention's overall structure is simple, making is easy, and cost is also comparatively cheap.
For making purpose, feature and effect that further understanding and understanding can be arranged, now be described with reference to the accompanying drawings as the back to the present invention:
Description of drawings
Fig. 1 is the polycrystal chip semiconductor package structure figure of known technology;
Fig. 2 is another encapsulating structure figure of wafer semiconductor more than the known technology;
Fig. 3 is one of polycrystal chip semiconductor package structure for the present invention preferred embodiment figure;
Fig. 4 A-4F is the preferred embodiment for the manufacture craft flow process of structure embodiment illustrated in fig. 3.
Fig. 5 is another preferred embodiment figure for the present invention's polycrystal chip semiconductor package structure;
Fig. 6 A-6F is the preferred embodiment for the manufacture craft flow process of structure embodiment illustrated in fig. 5.
Embodiment
The invention relates to a kind of polycrystal chip semiconductor package structure and method for making, mainly be by merge simultaneously the LOC technology (on the pin in wafer: Lead On Chip; Be called for short LOC) and BGA technology (solder ball array contact: Ball Grid Array; Be called for short BGA) two plates is stacked in the same IC element, making a wafer wherein is to utilize pin to become the interface of circuit and extraneous binding on the wafer, another wafer then is to be used as the interface of circuit and extraneous binding on the wafer by the tin ball, and has more omitted the required base component of known BGA technology.So not only this two plates can have different functions respectively, also can have identical functions, and its integral body simple in structure, make easily, cost is lower, and the entire area of IC element, length all can more be dwindled than known technology.
Fig. 3 is one of the present invention's polycrystal chip semiconductor package structure preferred embodiment figure.Fig. 4 A-Fig. 4 F then is a preferred embodiment of manufacture craft flow process embodiment illustrated in fig. 3.
In preferred embodiment shown in Figure 3, this polycrystal chip semiconductor encapsulation (IC) structure 20 includes: a plurality of wafers, a lead frame 24, a plurality of tin ball 27 and potting resin 26.These a plurality of wafers are to include one first wafer 21 and one second wafer 22 in the present embodiment, each wafer 21,22 all have a significant surface 211,221 (Active Side) and a non-significant surface 212,222 (InactiveSide), this significant surface 211,221 are wafer 21, one side surface at 22 circuit design place, and, at each wafer 21, on 22 the significant surface 211,221 pre-position is equipped with a plurality of connection gaskets 213,223 to become wafer 21, the interface of circuit on 22 and extraneous binding, this connection gasket 213 in this preferred embodiment, 223 are metal gasket or the aluminium pad (Al Pad) that this area is commonly called as.
This lead frame 24 (Lead Frame) has a plurality of pins 241 (Lead), a plurality of connection gaskets 223 on the significant surface 221 of this second wafer 22 are to be coupled in respectively on the corresponding pin 241 by a technological means, and the non-significant surface 212 of first wafer 21 is to be incorporated on the lead frame 24.In this preferred embodiment, this technological means of connection gasket 223 and corresponding pin 241 of second wafer 22 of being used to be coupled is to be bonding wire 224 (Gold Wire Bonding), and the non-significant surface 212 of this first wafer 21 be by hot melt two-sided tape 23 (Dual-Sided Adhesive Tape) fit in lead frame 24 not with a side of second wafer, 22 bonding wires couplings on, the non-significant surface 222 of second wafer 22 then is to fit on the non-significant surface 212 of first wafer 21 by elargol 25 (EPOXY).Certainly, any personage who is familiar with semiconductor after consulting above stated specification, when can think easily and, and can select effective double faced adhesive tape to bring in conjunction with second wafer 22 and first wafer 21.
These a plurality of tin balls 27 (Solder Ball) are to be arranged at respectively on the significant surface 211 of this first wafer 21 on corresponding a plurality of connection gaskets 213, between tin ball 27 and connection gasket 213 and implant in advance and have endosphere 214 to be incorporated into medium on the connection gasket 213 to become tin ball 27.Then, encapsulate (Molding) with potting resin 26 again and coat aforementioned wafer 21,22 and the semiconductor packages IC structure 20 that becomes one, and this a plurality of pins 241 and tin ball 27 are that to be exposed to potting resin 26 outer to become the interface with external world's binding.
By structure as shown in Figure 3, because this second wafer 22 is to utilize the pin 241 of lead frame 24 to become the interface that the circuit on the wafer 22 is connected with the external world, this first wafer 21 then is to be used as circuit and the extraneous interface that is connected on the wafer 21 by tin ball 27, and, because first and second wafer 21,22 all is to be positioned on the lead frame 24 and more can to have omitted the required base component of BGA technology commonly used.So, the present invention's polycrystal chip semiconductor package structure 20 can be as shown in Figure 3, and not only Zheng Ti volume is less, the moderate IC of the making length of pin number can the area that be arranged so that IC long, that lacked known base component greatly reduce and more makes manufacturing cost more cheap because of the simplification of structure and number of elements.In addition, because this two plates 21, the 22nd, respectively by tin ball 27 and the interface of pin 241 as circuit on the two plates and extraneous binding, so, when the circuit on first wafer 21 directly with second wafer 22 on which couple and pin 241 when also directly being coupled with tin ball 27, this first wafer 21 and second wafer 22 can be the wafer with difference in functionality, for example, first wafer 21 can be the wafer of a logical circuit and second wafer 22 is the wafers for a memory circuitry, thereby can in same IC, include the wafer of several difference in functionalitys simultaneously, the design of IC and effective elasticity are greatly increased.Certainly, anyly be familiar with the personage of semiconductor after consulting above stated specification, when can think easily and, this first wafer 21 and second wafer 22 are for having the wafer of identical function and make, or design can intercouple the circuit on the win wafer 21 and second wafer 22 directly or indirectly.
In the embodiment of the following stated, being same as aforementioned element will be with identical numbering and name nominating, and no longer heavily covers and give unnecessary details its structure function.
Fig. 4 A-4F is a preferable manufacture craft flow implementation example of the method for making of polycrystal chip semiconductor package structure 20 embodiment illustrated in fig. 3, and it includes the following step:
(a) on the non-significant surface 212 of one first wafer 21 by two-sided tape 23 in conjunction with a lead frame 24 with a plurality of pins 241.
(b) the non-significant surface 222 with one second wafer 22 is incorporated on the non-significant surface 212 of first wafer 21 by elargol 25.
(c) carry out bonding wire and be coupled on the pin 241 of lead frame 24, make the circuit on second wafer 22 can be via pin 241 and extraneous UNICOM so that the connection gasket 223 on the significant surface 221 of second wafer 22 is connected by bonding wire 224.
(d) connection gasket 213 of the appropriate location on the significant surface 211 of first wafer 21 is implanted a plurality of endospheres 214, and the perfusion encapsulation of carrying out potting resin 26 simultaneously forms the semiconducter IC element of one to coat this first, second wafer 21,22, and this pin 241 and endosphere 214 all have at least a part to be exposed to outside the potting resin 26.
(e) implant a plurality of tin balls 27 on the position of these a plurality of endospheres 214, make the circuit on first wafer 21 can be via tin ball 27 and extraneous UNICOM.
(f) carry out the clubfoot processing and forming of pin 241, make pin 241 extend predetermined angle, length and a shape towards the direction of tool tin ball 27, can carry out the cutting and separating processing between a plurality of IC in case of necessity again, finish the manufacturing of the present invention's polycrystal chip semiconductor package structure 20.
Fig. 5 is another preferred embodiment figure of the present invention's polycrystal chip semiconductor package structure 40.Fig. 6 A-6F then is a preferred embodiment of manufacture craft flow process embodiment illustrated in fig. 5.
In preferred embodiment shown in Figure 5, this polycrystal chip semiconductor encapsulation (IC) structure 40 includes too: two wafers (first wafer 41 and second wafer 42), have lead frame 44, a plurality of tin ball 47 of a plurality of pins 441 and are used for the potting resin 46 of the IC structure that coating wafer 41,42 becomes one.This two plates 41,42 all has a significant surface 411,421 and one non-significant surface 412,422 too, and, on the significant surface 411,421 of each wafer 41,42, also be equipped with a plurality of connection gaskets 413,423.
This first wafer 41 also is to fit on one of lead frame 44 side by two-sided tape 43 in preferred embodiment shown in Figure 5, yet, any personage who is familiar with semiconductor after consulting above stated specification, when can think easily and, can select to make this first wafer 41 to conform on the lead frame 44 by elargol.On the another side of lead frame 44, be combined with this second wafer 42 with respect to first wafer 41, and the connection gasket 423 on the significant surface 421 of second wafer 42 is to be directly welded on the corresponding pin 441 by scolder 424 (for example tin ball), not only therefore 42 combinations of second wafer are fixed on the lead frame 44, and reach simultaneously the circuit on second wafer 42 by the purpose of pin 441 with extraneous UNICOM.As for 413 embodiment of the connection gasket on first wafer 41, be successively to be combined with endosphere 414 and tin ball 47 respectively, so that the circuit on first wafer 41 can be by tin ball 47 and extraneous UNICOM as Fig. 3.
Fig. 6 A-6F is a preferable manufacture craft flow implementation example of the method for making of polycrystal chip semiconductor package structure 40 embodiment illustrated in fig. 5, and it includes the following step:
(a) but a plurality of connection gaskets 423 places on the significant surface 421 of one second wafer 42 implant conductivity scolder 424 respectively.
(b) mode of 42 more than scolders 424 of second wafer with thermal welding (welding) is incorporated into respectively on 44 more than corresponding pins 441 of a lead frame, make pin 441 become the interface of circuit and extraneous binding on second wafer 42, at lead frame 44 with respect to the appropriate position on the another side of second wafer 42 and be provided with two-sided tape 43.
(c) the non-significant surface 412 with one first wafer 41 is incorporated on the two-sided tape 43 of this lead frame 44, and first wafer 41 is fixed on the lead frame 44.
(d) connection gasket 413 place implants endosphere 414 respectively more than on the significant surface 411 of first wafer 41, and the perfusion encapsulation of carrying out potting resin 46 to be coating this first, second wafer 41,42, and this pin 441 and endosphere 414 all have at least some to be exposed to outside the potting resin 46.
(e) implant a plurality of tin balls 47 on the position of these a plurality of endospheres 414, make tin ball 47 become the interface of circuit and extraneous binding on first wafer 41.
(f) carry out the clubfoot processing and forming of pin 441, make pin 441 extend predetermined angle, length and a shape, finish the manufacturing of the present invention's polycrystal chip semiconductor package structure 40 towards the direction of tool tin ball 47.
In sum, a kind of polycrystal chip semiconductor package structure of the present invention and method for making can improve effectively that the length of the semiconductor element that the known known polycrystal chip semiconductor IC encapsulating structure made from simple LOC or simple BGA technology had is oversize, area is too big, complicated integral structure, making difficulty, cost is higher, practicality is relatively poor etc. many disadvantages.And the present invention's polycrystal chip semiconductor package structure can select to be useful in the wafer (or also identical wafer) that includes several difference in functionalitys among the same IC simultaneously, design and the effective elasticity of IC are greatly increased, and its overall structure is very simple, the volume area is with length is all less, it is easy to make, cost is very cheap.
The above only is the present invention's preferred embodiment, when can not with the scope implemented of qualification the present invention.Promptly the equalization of being done according to claim scope of the present invention generally changes and modifies, and all should still belong in the scope that claim of the present invention contains.

Claims (4)

1, a kind of polycrystal chip semiconductor package structure, at least include one first wafer and one second wafer, each wafer all has a significant surface and a non-significant surface, and on the significant surface of each wafer, be equipped with a plurality of connection gaskets to become the interface of circuit and extraneous binding on the wafer, this two plates is coated by potting resin and is become the semiconductor package of one, it is characterized in that:
The non-significant surface of first wafer and the non-significant surface of second wafer are bonding by elargol, this first wafer is positioned at second wafer below, and the significant surface of first wafer is towards the below, a plurality of connection gaskets on the significant surface of first wafer are provided with a plurality of tin balls, and it is outer to become the interface of circuit and extraneous binding on first wafer that this tin ball is exposed to potting resin downwards; And, a plurality of connection gaskets on the second wafer significant surface are to be coupled in respectively more than the lead frame on the pin by bonding wire, and the non-significant surface of first wafer be by the hot melt two-sided tape fit in lead frame not with a side of second wafer bonding wire coupling on, this pin extension is exposed to outside the potting resin, and extend and to have one of tin ball side towards this semiconductor package, to become the interface of circuit and extraneous binding on second wafer; Wherein said significant surface is the face that is laid with integrated circuit, and described non-significant surface is the face of no integrated circuit.
2, polycrystal chip semiconductor package structure according to claim 1 is characterized in that: this connection gasket is to be the aluminium pad.
3, polycrystal chip semiconductor package structure according to claim 1 is characterized in that: the circuit on first wafer directly with second wafer on which couple, and the pin of lead frame directly is coupled with the tin ball.
4, polycrystal chip semiconductor package structure according to claim 1 is characterized in that: the function that this first wafer and second wafer are had can be different.
CNB981193471A 1998-09-21 1998-09-21 Polycrystal chip semiconductor package structure and making method Expired - Fee Related CN1145211C (en)

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KR100434201B1 (en) * 2001-06-15 2004-06-04 동부전자 주식회사 Semiconductor package and fabrication method
US7116002B2 (en) * 2004-05-10 2006-10-03 Taiwan Semiconductor Manufacturing Company, Ltd. Overhang support for a stacked semiconductor device, and method of forming thereof
CN100413067C (en) * 2006-01-06 2008-08-20 日月光半导体制造股份有限公司 Chip encapsulation structure and its crystal encapsulation forming method
CN101452919B (en) * 2007-12-07 2011-03-16 南茂科技股份有限公司 Multi-wafer intersecting stacking encapsulation construction
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Publication number Priority date Publication date Assignee Title
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