CN114520189A

CN114520189A - Method for manufacturing semiconductor device

Info

Publication number: CN114520189A
Application number: CN202110478868.2A
Authority: CN
Inventors: 周沛瑜; 李资良
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2021-01-14
Filing date: 2021-04-29
Publication date: 2022-05-20
Also published as: KR102590207B1; TW202230496A; US20230386848A1; US20220223422A1; KR20220102998A; DE102021105910A1; TWI784579B

Abstract

The present disclosure relates to a method of manufacturing a semiconductor device. A method, comprising: the method includes forming a dummy gate stack on a semiconductor fin, forming gate spacers on sidewalls of the dummy gate stack, forming a first interlayer dielectric, wherein the gate spacers and the dummy gate stack are located in the first interlayer dielectric, removing the dummy gate stack to form trenches between the gate spacers, forming a replacement gate stack in the trenches, and depositing a dielectric capping layer. A bottom surface of the dielectric cap layer contacts a first top surface of the replacement gate stack and a second top surface of the first interlayer dielectric. A second interlayer dielectric is deposited over the dielectric cap layer. Source/drain contact plugs are formed that extend into the second interlayer dielectric, the dielectric cap layer, and the first interlayer dielectric.

Description

Method for manufacturing semiconductor device

Technical Field

The present disclosure relates to a method of manufacturing a semiconductor device.

Background

Metal Oxide Semiconductor (MOS) devices are basic building blocks in integrated circuits. Recent developments in MOS devices include forming replacement gates that include a high-k gate dielectric and a metal gate electrode over the high-k gate dielectric. The formation of the replacement gate typically involves depositing a high-k gate dielectric layer and a metal layer over the high-k gate dielectric layer, and then performing Chemical Mechanical Polishing (CMP) to remove excess portions of the high-k gate dielectric layer and the metal layer. The remaining portion of the metal layer forms a metal gate. The metal gate may be recessed to form a recess between adjacent gate spacers, and then a self-aligned dielectric hard mask is formed in the trench.

Disclosure of Invention

According to an aspect of the present disclosure, there is provided a method of manufacturing a semiconductor device, including: forming a dummy gate stack on the semiconductor fin; forming gate spacers on sidewalls of the dummy gate stack; forming a first interlayer dielectric, wherein the gate spacer and the dummy gate stack are located in the first interlayer dielectric; removing the dummy gate stack to form trenches between the gate spacers; forming a replacement gate stack in the trench; depositing a dielectric cap layer, wherein a bottom surface of the dielectric cap layer contacts a first top surface of the replacement gate stack and a second top surface of the first interlayer dielectric; depositing a second interlayer dielectric over the dielectric cap layer; and forming source/drain contact plugs extending into the second interlayer dielectric, the dielectric capping layer, and the first interlayer dielectric.

According to another aspect of the present disclosure, there is provided a method of manufacturing a semiconductor device, including: forming a metal gate in the first interlayer dielectric (ILD); performing a planarization process to make a first top surface of the metal gate flush with a second top surface of the first ILD; depositing a dielectric cap layer, wherein the dielectric cap layer is over and in contact with both the first top surface and the second top surface; depositing a second ILD over the dielectric cap layer; and etching both the second ILD and the dielectric cap layer in an etching process to form a contact opening, wherein the contact opening passes through both the second ILD and the dielectric cap layer.

According to still another aspect of the present disclosure, there is provided a method of manufacturing a semiconductor device, including: forming a metal gate in the first interlayer dielectric (ILD); depositing a dielectric cap layer, wherein the dielectric cap layer is planar and is over and in contact with both the metal gate and the first ILD; depositing a second ILD over and in contact with the dielectric cap layer, wherein the first ILD and the second ILD are both thicker than the dielectric cap layer; etching both the second ILD and the dielectric cap layer to form a contact opening, wherein the etching is performed continuously until a top surface of an underlying feature is exposed; and forming a contact plug extending into the contact opening.

Drawings

Aspects of the disclosure are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1-6, 7A, 7B, and 8-19 illustrate perspective and cross-sectional views of intermediate stages in the formation of a fin field effect transistor (FinFET), according to some embodiments.

Fig. 20A and 20B illustrate structures and schematic oxygen distributions, respectively, according to some embodiments.

FIG. 21 shows a comparison of X-ray photoelectron spectroscopy results for samples with and without a capping layer, according to some embodiments.

Fig. 22 illustrates a process flow for forming a FinFET in accordance with some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to readily describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

A fin field effect transistor (FinFET) and a method of forming the same are provided. According to some embodiments of the present disclosure, a dielectric cap layer that is free of oxygen and has the ability to block oxygen diffusion is deposited over and in contact with the metal gate prior to forming the oxygen-containing interlayer dielectric. An interlayer dielectric is then deposited on the dielectric cap layer. The dielectric capping layer has the ability to block oxygen diffusion so that the underlying metal gate is not oxidized during the subsequent annealing process. The embodiments discussed herein will provide examples to enable or use the subject matter of the present disclosure, and one of ordinary skill in the art will readily appreciate modifications that can be made while remaining within the intended scope of the different embodiments. Like reference numerals are used to refer to like elements throughout the various views and illustrative embodiments. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

Fig. 1-6, 7A, 7B, and 8-19 illustrate cross-sectional and perspective views of intermediate stages in formation of a fin field effect transistor (FinFET), according to some embodiments of the present disclosure. The processes shown in these figures are also schematically reflected in the process flow 200 as shown in fig. 22.

In fig. 1, a substrate 20 is provided. The substrate 20 may be a semiconductor substrate, e.g., a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., with p-type or n-type dopants) or undoped. The semiconductor substrate 20 may be a portion of a wafer 10 (e.g., a silicon wafer). Typically, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a Buried Oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon substrate or a glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the semiconductor substrate 20 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or a combination thereof.

With further reference to fig. 1, a well region 22 is formed in the substrate 20. The corresponding process is shown as process 202 in process flow 200 shown in fig. 22. Well region 22 is an n-type well region formed by implanting n-type impurities (which may be phosphorus, arsenic, antimony, etc.) into substrate 20, according to some embodiments of the present disclosure. According to other embodiments of the present disclosure, the well region 22 is a p-type well region formed by implanting p-type impurities (which may be boron, indium, etc.) into the substrate 20. The resulting well region 22 may extend to the top surface of the substrate 20. The n-type or p-type impurity concentration may be 10 or less¹⁸cm^-3E.g. at about 10¹⁷cm^-3To about 10¹⁸cm^-3Within the range of (a).

Referring to fig. 2, an isolation region 24 is formed to extend from the top surface of the substrate 20 into the substrate 20. Hereinafter, the isolation region 24 is alternatively referred to as a Shallow Trench Isolation (STI) region. The corresponding process is shown as process 204 in process flow 200 shown in fig. 22. The portions of the substrate 20 between adjacent STI regions 24 are referred to as semiconductor strips 26. To form the STI regions 24, a pad oxide layer 28 and a hard mask layer 30 are formed on the semiconductor substrate 20, and then the pad oxide layer 28 and the hard mask layer 30 are patterned. The pad oxide layer 28 may be a thin film formed of silicon oxide. According to some embodiments of the present disclosure, the pad oxide layer 28 is formed in a thermal oxidation process, wherein a top surface layer of the semiconductor substrate 20 is oxidized. The pad oxide layer 28 serves as an adhesion layer between the semiconductor substrate 20 and the hard mask layer 30. The pad oxide layer 28 may also serve as an etch stop layer for etching the hard mask layer 30. According to some embodiments of the present disclosure, the hard mask layer 30 is formed of silicon nitride, for example, using Low Pressure Chemical Vapor Deposition (LPCVD). According to other embodiments of the present disclosure, the hard mask layer 30 is formed by thermal nitridation of silicon or Plasma Enhanced Chemical Vapor Deposition (PECVD). A photoresist (not shown) is formed on the hard mask layer 30 and then patterned. The hard mask layer 30 is then patterned using the patterned photoresist as an etch mask to form the hard mask 30 as shown in figure 2.

Next, the patterned hard mask layer 30 is used as an etch mask to etch the pad oxide layer 28 and the substrate 20, followed by filling the resulting trenches in the substrate 20 with dielectric material(s). A planarization process, such as a Chemical Mechanical Polishing (CMP) process or a mechanical grinding process, is performed to remove the excess portion of the dielectric material, and the remaining portion of the dielectric material(s) is the STI region 24. STI regions 24 may include a liner dielectric (not shown), which may be a thermal oxide formed by thermally oxidizing a surface layer of substrate 20. The liner dielectric may also be a deposited silicon oxide layer, silicon nitride layer, or the like formed using, for example, Atomic Layer Deposition (ALD), High Density Plasma Chemical Vapor Deposition (HDPCVD), or Chemical Vapor Deposition (CVD). STI regions 24 may also include a dielectric material over the liner oxide, wherein the dielectric material may be formed using Flowable Chemical Vapor Deposition (FCVD), spin-on coating, or the like. According to some embodiments, the dielectric material over the liner dielectric may comprise silicon oxide.

The top surface of hard mask 30 and the top surface of STI region 24 may be substantially flush with each other. Semiconductor strips 26 are between adjacent STI regions 24. According to some embodiments of the present disclosure, the semiconductor strips 26 are part of the original substrate 20, and thus the material of the semiconductor strips 26 is the same as the material of the substrate 20. According to an alternative embodiment of the present disclosure, semiconductor strips 26 are replacement strips formed by: portions of the substrate 20 between the STI regions 24 are etched to form recesses, and epitaxy is performed to regrow another semiconductor material in the recesses. Thus, semiconductor strips 26 are formed of a semiconductor material that is different from the semiconductor material of substrate 20. According to some embodiments, the semiconductor strips 26 are formed of silicon germanium, silicon carbon, or a III-V compound semiconductor material.

Referring to fig. 3, STI region 24 is recessed such that the top of semiconductor strip 26 protrudes above the top surface 24A of the remaining portion of STI region 24 to form protruding fin 36. The corresponding process is shown as process 206 in the process flow 200 shown in fig. 22. The etching may be performed using a dry etching process in which, for example, HF is applied₃And NH₃The mixture of (a) is used as an etching gas. During the etching process, a plasma may be generated. Argon may also be included. In accordance with an alternative embodiment of the present disclosure, the recessing of the STI regions 24 is performed using a wet etch process. For example, the etching chemistry may include HF.

In the above embodiments, the fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes (including double patterning or multiple patterning processes). Typically, double or multiple patterning processes combine lithography and self-aligned processes, allowing for the creation of patterns with, for example, pitches smaller than those obtainable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithographic process. Spacers are formed along the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the fins may then be patterned using the remaining spacers or mandrels (mandrel).

Referring to fig. 4, a dummy gate stack 38 is formed to extend over the top surface and sidewalls of the (protruding) fin 36. The corresponding process is shown as process 208 in the process flow 200 shown in fig. 22. The dummy gate stack 38 may include a dummy gate dielectric 40 (shown in fig. 7B) and a dummy gate electrode 42 over the dummy gate dielectric 40. The dummy gate electrode 42 may be formed using, for example, polysilicon or amorphous silicon, and other materials may also be used. Each dummy gate stack 38 may also include one (or more) hard mask layers 44 over the dummy gate electrode 42. The hard mask layer 44 may be formed of silicon nitride, silicon oxide, silicon carbonitride, or multilayers thereof. The dummy gate stack 38 may span over a single or multiple protruding fins 36 and/or STI regions 24. The dummy gate stack 38 also has a length direction that is perpendicular to the length direction of the protruding fins 36.

Next, gate spacers 46 are formed on the sidewalls of the dummy gate stack 38. The corresponding process is shown as process 208 in the process flow 200 shown in fig. 22. According to some embodiments of the present disclosure, the gate spacer 46 is formed of dielectric material(s) (e.g., silicon nitride, silicon carbonitride, etc.) and may have a single layer structure or a multi-layer structure including multiple dielectric layers.

The portions of the protruding fins 36 not covered by the dummy gate stack 38 and the gate spacers 46 are then etched, resulting in the structure shown in fig. 5. The corresponding process is shown as process 210 in process flow 200 shown in fig. 22. The recess may be anisotropic and thus the portion of fin 36 directly under dummy gate stack 38 and gate spacer 46 is protected and not etched. According to some embodiments, the top surface of the recessed semiconductor strips 26 may be lower than the top surface 24T of the STI regions 24. The recess 50 is formed accordingly. The recesses 50 include portions on opposite sides of the dummy gate stack 38 and portions between the remaining portions of the protruding fins 36.

Next, epitaxial regions (source/drain regions) 52 are formed by selectively growing (by epitaxy) a semiconductor material in the recesses 50, resulting in the structure in fig. 6. The corresponding process is shown as process 212 in process flow 200 shown in fig. 22. Depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET, either a p-type or n-type impurity may be doped in-situ as the epitaxy progresses. For example, when the resulting FinFET is a p-type FinFET, silicon germanium boron (SiGeB), silicon boron (SiB), or the like may be grown. In contrast, when the resulting FinFET is an n-type FinFET, silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), or the like may be grown. According to an alternative embodiment of the present disclosure, epitaxial region 52 comprises a group III-V compound semiconductor, such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, combinations thereof, or multilayers thereof. After the recess 50 is filled with the epi region 52, further epitaxial growth of the epi region 52 causes the epi region 52 to spread horizontally and facets may be formed. Further growth of the epitaxial regions 52 may also cause adjacent epitaxial regions 52 to merge with one another. A gap (air gap) 53 may be generated.

After the epitaxy step, the epitaxial region 52 may be further implanted with p-type or n-type impurities to form source and drain regions, which are also denoted with reference numeral 52. According to an alternative embodiment of the present disclosure, the implantation step is skipped when the epitaxial region 52 is in-situ doped with p-type or n-type impurities during the epitaxy.

Fig. 7A shows a perspective view of the structure after forming a Contact Etch Stop Layer (CESL)58 and an interlayer dielectric (ILD) 60. The corresponding process is shown as process 214 in the process flow 200 shown in fig. 22. Fig. 7B shows a vertical plane in the reference section B-B of the structure in fig. 7A. CESL58 may be formed of silicon oxide, silicon nitride, silicon carbonitride, aluminum oxide, aluminum nitride, or the like, and may be formed using CVD, ALD, or the like. The ILD 60 may comprise a dielectric material formed using, for example, PECVD, FCVD, spin-on coating, CVD, or another deposition method. According to some embodiments, the deposition of the ILD is performed using a plasma, such as when PECVD is used. The ILD 60 may be formed of an oxygen-containing dielectric material, which may be a silicon oxide-based material formed using Tetraethylorthosilicate (TEOS) as a precursor, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), and the like. A planarization process (e.g., a CMP process or a mechanical polishing process) may be performed to make the top surfaces of the ILD 60, dummy gate stack 38 and gate spacer 46 flush with one another.

After forming the structure shown in fig. 7A and 7B, the dummy gate stack 38 is replaced with replacement gate stacks that include replacement gate electrodes and replacement gate dielectrics, as shown in fig. 8 and 9. The sectional views shown in fig. 8 and 9 and subsequently fig. 10 to 19 are taken from the same vertical plane in the reference section B-B in fig. 7A. In fig. 7B and 8-19, the level of the top surface 24T and the level of the bottom surface 24B of the STI region 24 are shown, while the STI region 24 is not shown since it is not in the plane shown. Semiconductor fin 36 is above the level of top surface 24T.

When the gate stack is replaced, the hard mask layer 44, dummy gate electrode 42, and dummy gate dielectric 40 as shown in fig. 7A and 7B are first removed in one or more etching steps resulting in a trench/opening 62 as shown in fig. 8. The corresponding process is shown as process 216 in the process flow 200 shown in fig. 22. The top surface and sidewalls (not in the plane shown) of protruding semiconductor fin 36 are exposed to trench 62.

Next, replacement gate stacks 76 are formed. The corresponding process is shown as process 218 in the process flow 200 shown in fig. 22. Referring to fig. 9, a (replacement) gate dielectric 68 is formed that extends into trench 62 (fig. 8). According to some embodiments of the present disclosure, the gate dielectric 68 includes an Interfacial Layer (IL)64 as a lower portion thereof. IL 64 is formed on the exposed surface of protruding fin 36. Each IL 64 may include an oxide layer, such as a silicon oxide layer, formed by thermal oxidation, chemical oxidation process, or deposition process of the corresponding protruding fin 36. Gate dielectric 68 may also include a high-k dielectric layer 66 formed over a corresponding IL 64. The high-k dielectric layer 66 may be formed of or include: high-k dielectric materials such as hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, and the like. The high-k dielectric material has a dielectric constant (k value) higher than 3.9 and may be higher than about 7.0. A high-k dielectric layer 66 covers and may be in contact with IL 64. High-k dielectric layer 66 is formed as a conformal layer and, when deposited, extends over the sidewalls of protruding fin 36 and the top surface and sidewalls of gate spacer 46. According to some embodiments of the present disclosure, the high-k dielectric layer 66 is formed using ALD or CVD.

With further reference to fig. 9, a stack of layers 70 is deposited. The sublayers in the stack 70 are not shown separately, but may be distinguished from each other. The deposition may be performed using a conformal deposition process such as ALD, CVD, etc., such that the thickness of the vertical portions and the thickness of the horizontal portions of the stacked layer 70 (and each sub-layer) are substantially equal to each other. When deposited, stack 70 extends into trench 62 (fig. 8) and includes portions over ILD 60.

The stack of layers 70 may include a diffusion barrier layer and a work function layer(s) over the diffusion barrier layer. The diffusion barrier layer may be formed of titanium nitride (TiN), which may (or may not) be doped with silicon. The work function layer determines a work function of the gate electrode, and includes at least one layer, or a plurality of layers formed of different materials. The material of the work function layer is selected according to whether the corresponding FinFET is an n-type FinFET or a p-type FinFET. For example, when the FinFET is an n-type FinFET, the work function layer may include a TaN layer and a titanium aluminum (TiAl) layer over the TaN layer. When the FinFET is a p-type FinFET, the work function layer may include a TaN layer, a TiN layer over the TaN layer, and a TiAl layer over the TiN layer. After deposition of the work function layer(s), a conductive capping layer, which may be another TiN layer, is formed.

Next, a metallic fill material 72, which may be formed of, for example, tungsten or cobalt, is deposited. The fill material 72 completely fills the remaining trench 62 (fig. 8). The deposited gate dielectric 68, stack 70 and fill material 72 include portions in the trenches 62 and other portions over the ILD 60. In subsequent processes, a planarization step, such as a CMP process or a mechanical polishing process, is performed to remove portions of the deposited layer overlying ILD 60. As a result, a metal gate electrode 74 is formed, which includes the remaining portions of the stack of layers 70 and the fill material 72. The replacement gate dielectric 68 and the replacement gate electrode 74 are referred to hereinafter, in combination, as a replacement gate stack 76. As shown in fig. 9, the top surfaces of the replacement gate stack 76, gate spacers 46, CESL58, and ILD 60 may now be substantially coplanar. Thus, various layers in replacement gate stack 76, including high-k dielectric layer 66, stack layer 70 (including the work function layer and the metal cap layer), and fill material 72 are exposed.

Fig. 10 illustrates the formation of capping layer 78. The corresponding process is shown as process 220 in process flow 200 shown in fig. 22. According to some embodiments, capping layer 78 is formed of a material that does not contain oxygen, and may be formed of or include: silicon nitride (SiN), silicon carbide (SiC), silicon carbonitride (SiCN), and the like. The deposition of cap layer 78 may be performed using CVD, ALD, PECVD, Plasma Enhanced CVD (PECVD), PVD, or the like.

An ILD80 is formed over cap layer 78. The corresponding process is shown as process 222 in process flow 200 shown in fig. 22. The ILD80 may comprise a dielectric material formed using, for example, FCVD, spin-on coating, CVD, PECVD, or another deposition method. The ILD80 may be formed of or include an oxygen-containing dielectric material, which may be a silicon oxide-based material formed using TEOS as a precursor, PSG, BSG, BPSG, or the like. ILD80 may comprise Si, O, C, N, etc., and may comprise other elements.

It should be understood that the process performed after cap layer 78 is deposited may include multiple thermal treatments. If capping layer 78 is not formed and ILD80 contacts the top surface of gate electrode 74, the heat treatment may cause oxygen in ILD80 to diffuse into the top of metal gate electrode 74 and cause oxidation of the top of metal gate electrode 74. In addition, plasma may be used to perform the deposition of the ILD80, which accelerates the diffusion and oxidation processes. Oxidation of the metal gate electrode 74 may cause an undesirable shift in the threshold voltage of the resulting FinFET. In an embodiment of the present disclosure, capping layer 78 has the function of preventing oxygen in ILD80 from passing through the top of metal gate electrode 74 and oxidizing the top of metal gate electrode 74. The oxygen barrier capability of capping layer 78 is related to the material and thickness of capping layer 78. For example, silicon nitride-containing materials have good oxygen barrier capabilities and may be used to form capping layer 78. The capping layer 78 may not be too thin or too thick. When capping layer 78 is too thin (e.g., thinner than about 3nm), it does not have sufficient oxygen barrier capability. When the capping layer 78 is too thick (e.g., thicker than about 5nm), its oxygen barrier capability is saturated and negative effects begin to dominate. For example, negative effects include difficulty etching through the capping layer 78 in the etching process shown in fig. 11 and 15. In addition, since the capping layer 78 has a high dielectric constant value, a thick capping layer 78 may result in higher parasitic capacitance between adjacent conductive features. According to some embodiments, the thickness T1 of capping layer 78 is in a range between about 3nm to about 5 nm. The thickness T2 of ILD80 may be greater than about 30nm, or in a range between about 30nm and about 500 nm. The ratio T2/T1 may be greater than 10, and may be greater than 20.

Fig. 11 to 16 illustrate the formation of source/drain contact plugs and gate contact plugs. In the illustrated example, the source/drain contact plugs and the gate contact plugs are shown in the same plane. In other embodiments, the source/drain contact plugs and the gate contact plugs are formed in different planes such that they are spaced apart from each other far, in order to prevent electrical short between the adjacent source/drain contact plugs and the gate contact plugs.

Fig. 11 to 13 illustrate the formation of source/drain contact plugs. Referring to fig. 11, an etch mask 82 (which may be or may include photoresist) is applied/deposited and patterned. Next, an etch process 84 is performed to form source/drain contact openings 86. The corresponding process is shown as process 224 in the process flow 200 shown in fig. 22. The etching process 84 is anisotropic and may be, for example, a dry etching process performed using Reactive Ion Etching (RIE). The etch gas is selected according to the materials of ILD80, capping layer 78, ILD 60, and CESL 58.

According to some embodiments, the etch is through ILD80, capping layer 78, and ILD 60, and the etch process stops on CESL 58. During the etching process, the etching may not (or may not) stop on the cap layer 78 and not stop on the ILD 60. In other words, the etch process 84 may continue without stopping until CESL58 is reached. For example, the etching gas may comprise a mixture of a first etching gas for etching the ILD80 and 60 and a second etching gas for etching the cap layer 78. According to some embodiments, the first etch gas is capable of etching the ILD80 and 60 but not the cap layer 78, and the second etch gas is capable of etching the cap layer 78 but not the ILD80 and 60. The first etching gas may be selected from NF₃And NH₃Mixture of (2), HF and NH₃Mixtures of (a) or combinations thereof. Second etching gasMay be a fluorine-containing gas, e.g. CF₄、O₂And N₂NF of₃And O₂、SF₆Mixture of (1), SF₆And O₂Mixtures of (a) and (b), and the like. Additionally or alternatively, the bias power in the etch process may be increased to ensure that the etch does not stop on the capping layer 78 and ILD 60, and a process gas such as Ar may be added so that the etch does not stop on the capping layer 78. For example, ILDs 80 and 60 may be etched in a chemical reaction, while cap layer 78 is partially removed by bombardment effects during the etching process. The material of the CESL58 and the etch gas are selected so that the etch can stop on the CESL 58. Another etch process is then performed to etch through CESL 58. The etching of CESL58 may be performed using a dry etching process or a wet etching process, and may be anisotropic or isotropic. The etch gas used to etch CESL58 is different from the etch gas used to etch ILD80, capping layer 78, and ILD 60.

According to an alternative embodiment, the formation of the opening 86 includes a plurality of etching processes, including a first etching process for etching the ILD80, a second etching process for etching the capping layer 78, a third etching process for etching the ILD 60, and a fourth etching process for etching the CESL 58. The first, second, and third etching processes may be anisotropic (and dry) etching processes, and the fourth etching process may be a wet process or a dry process. After the opening 86 is formed, the etching mask 82 is removed. According to these embodiments, the etch gas for each of the cap layer 78, ILD 60, and CESL58 may be different from the etch gas used to etch the layer immediately overlying it.

Referring to fig. 12, according to some embodiments, dielectric contact spacers 88 are formed. The corresponding process is shown as process 226 in the process flow 200 shown in fig. 22. The formation process includes depositing a blanket dielectric layer, for example, using a conformal deposition method (e.g., CVD or ALD). The dielectric layer may be a high-k dielectric layer having a k value greater than 3.9, thereby having good isolation capability. Candidate materials include Al_xO_y、HfO₂SiN, SiOCN, etc. The thickness of the dielectric layer may range between about 2nm to about 4nm. The dielectric layer may also comprise silicon oxide or a low-k dielectric layer to reduce parasitic capacitance, depending on the particular requirements of the circuit. An anisotropic etch is then performed to remove horizontal portions of the dielectric layer and the remaining vertical portions in the openings 86 form contact spacers 88, each contact spacer 88 forming a ring when viewed from the top of the wafer 10. According to an alternative embodiment, the formation of the dielectric contact spacers 88 is skipped.

Fig. 13 illustrates the formation of source/drain contact plugs 96. The corresponding process is shown as process 228 in the process flow 200 shown in fig. 22. In a corresponding formation process, a metal layer 90 (e.g., a titanium layer or a cobalt layer) is deposited, for example using PVD, the metal layer 90 being formed as a blanket layer including portions extending into the openings 86 (fig. 12) to contact the source/drain regions 52 and portions overlying the ILD 80. A barrier layer 92 is then formed over the metal layer 90, the barrier layer 92 being a metal nitride layer such as a titanium nitride layer or a tantalum nitride layer. Barrier layer 92 may be formed by nitriding the top layer of metal layer 90 while the bottom layer of metal layer 90 is not nitrided, or barrier layer 92 may be formed using a deposition method such as CVD. Both layers 90 and 92 are conformal and extend into opening 86.

An annealing process is then performed to form source/drain silicide regions 97. The annealing process may be performed by Rapid Thermal Annealing (RTA), furnace annealing (furnaceanneal), or the like. Thus, the bottom of the metal layer 90 reacts with the source/drain regions 52 to form silicide regions 97. Sidewall portions of the metal layer 90 remain after the silicidation process. According to some embodiments of the present disclosure, the top surface of silicide region 97 is in contact with the bottom surface of barrier layer 92.

Next, as also shown in fig. 13, a metallic material 94 is deposited over barrier layer 92 and in contact with barrier layer 92. Metallic material 94 may include tungsten, cobalt, or the like. A planarization process, such as a CMP process or a mechanical polishing process, is then performed to remove the portions of

layers

90, 92, and 94 that are over ILD 80. The remaining portions of

layers

90, 92 and 94 are referred to as source/drain contact plugs 96. Thus forming FinFET 95.

Fig. 14 illustrates the formation of an Etch Stop Layer (ESL)98 and a dielectric layer (ILD) 100. The corresponding process is shown as process 230 in the process flow 200 shown in fig. 22. The etch stop layer 98 may be oxygen-containing or oxygen-free, and may be formed of aluminum nitride, aluminum oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, or the like, or multilayers thereof, and may be formed using a deposition method such as CVD, ALD, or the like. The ILD 100 may comprise a material selected from PSG, BSG, BPSG, fluorine doped silicon glass (FSG), silicon oxide, and the like. Dielectric layer 100 may be formed using spin coating, FCVD, or the like, or by a deposition process such as PECVD or LPCVD.

Referring to fig. 15, ILD 100 and etch stop layer 98 are etched to form

openings

102, 104 and 106. The corresponding process is shown as process 232 in the process flow 200 shown in fig. 22. An etch mask 101, which may comprise photoresist, is formed and patterned. The etching process is shown as etching process 108. It should be understood that although the

openings

102, 104, and 106 are shown as tapered, they may also have vertical edges. The etching process 84 may be anisotropic and may be, for example, a dry etching process performed using RIE. The etch gas is selected according to the materials of the ILD 100, etch stop layer 98, ILD80, and CESL 78. According to some embodiments, the openings 106 include portions 106A and portions 106B, wherein the portions 106A extend to the respective underlying gate electrodes 74 and the portions 106B extend to the respective underlying source/drain contact plugs 96.

In accordance with some embodiments, to form opening 104 and opening portion 106B, the dielectric layers (including ILD 100, etch stop layer 98, ILD80, and capping layer 78) are etched through without stopping during the etch process, and the etch process stops on gate electrode 74. For example, the etching gas may comprise a mixture of a first etching gas for etching the

ILDs

100 and 80 and a second etching gas for etching the etch stop layer 78. According to some embodiments, the first etch gas is capable of etching

ILDs

100 and 80 but not ILD 98 and cap layer 78, and the second etch gas is capable of etching ILD 98 and cap layer 78 but not ILDs 100 and 80. The first etching gas may be selected from NF₃And NH₃Mixture of (2), HF and NH₃Mixtures of (a) or combinations thereof. The second etching gas may be a fluorine-containing gas, such as CF₄、O₂And N₂NF of₃And O₂、SF₆Mixture of (1), SF₆And O₂Mixtures of (a) and (b), and the like.

According to an alternative embodiment, to form opening 104 and opening portion 106A, the dielectric layer (including ILD 100, etch stop layer 98, and ILD 80) is etched through without stopping during the etch process, and the etch process stops on cap layer 78. According to these embodiments, capping layer 78 is formed of a different material than the materials of ILD 100, etch stop layer 98, and ILD 80. For example, the etching gases may include a first etching gas for etching the

ILDs

100 and 80 and a second etching gas for etching the etch stop layer 98, neither of which etches the cap layer 78. The first etching gas may be selected from NF₃And NH₃Mixture of (2), HF and NH₃Mixtures of (a) or combinations thereof. The second etching gas may be a fluorine-containing gas, such as CF₄、O₂And N₂NF of₃And O₂、SF₆Or SF₆And O₂Mixtures of (a) and (b), and the like. After the etch stops on the cap layer 78, another etch process is performed to etch through the cap layer 78 using a different etch gas than the etch gas used to etch the ILD 100, etch stop layer 98 and ILD 58. The etching of capping layer 78 may be performed using a dry etch process or a wet etch process, and may be anisotropic or isotropic.

According to an alternative embodiment, the formation of

openings

102, 104, and 106B includes a plurality of etching processes, including a first etching process for etching ILD 100, a second etching process for etching etch stop layer 98, a third etching process for etching ILD80, and a fourth etching process for etching cap layer 78. The first, second, and third etching processes may be anisotropic (and dry) etching processes, and the fourth etching process may be a wet process or a dry process. After the

openings

102, 104, and 106 are formed, the etching mask 101 is removed.

The formation of the opening 102 and the opening portion 106B may be performed using the same etching mask (as shown in fig. 15), or alternatively, the opening 102 is formed using the same etching mask as the opening 104 and the opening portion 106A, and the opening portion 106B is formed using a separate etching mask. The etch stop layer 98 may be used for etch stop while etching the opening 102 (and possibly also the opening portion 106B), and the etching includes etching the ILD 100 and stopping on the etch stop layer 98, and then etching through the etch stop layer 98 in another etching process using a different etching chemistry (gas or chemical solution) than the etching gas used to etch the ILD 100.

In a subsequent process, the

openings

102, 104, and 106 are filled with conductive material(s) to form contact plugs 108, 110, and 112, as shown in fig. 16. The corresponding process is shown as process 234 in the process flow 200 shown in fig. 22. The formation process includes depositing the desired conductive material/layer and then performing a planarization process to remove excess material. According to some embodiments, the contact plugs 108, 110, and 112 are formed of a homogenous conductive material, and the entire conductive material has the same composition, and may be formed of titanium nitride, tungsten, cobalt, or the like. According to an alternative embodiment, each of the contact plugs 108, 110, and 112 has a composite structure including, for example, a barrier layer and a metal material located over the barrier layer. The barrier layer may be formed of titanium nitride, titanium, tantalum nitride, tantalum, or the like, and the metal material may be formed of tungsten, cobalt, copper, or the like. Contact plugs 112 electrically and physically interconnect gate electrode 74 and source/drain contact plugs 96.

Fig. 17 illustrates the formation of an etch stop layer 114, a dielectric layer 116, also referred to as an inter-metal dielectric (IMD), and a metal line 118. The etch stop layer 114 may be formed of SiON, aluminum oxide, aluminum nitride, or the like, or a composite layer thereof. According to some embodiments of the present disclosure, the dielectric layer 116 may be formed of a low-k dielectric material having a dielectric constant (k value) below about 3.0. The dielectric layer 116 may be formed of or include: black Diamond (registered trademark of applied materials corporation), carbon-containing low-k dielectric materials, Hydrogen Silsesquioxane (HSQ), Methyl Silsesquioxane (MSQ), and the like. According to some embodiments of the present disclosure, the formation of the dielectric layer 116 includes depositing a porogen-containing dielectric material and then performing a curing process to drive off the porogen, and thus the remaining dielectric layer 116 is porous.

Metal lines 118 are formed in the dielectric layer 116. The formation process may include a damascene process, for example, a single damascene process as shown in fig. 17. The forming process may include: etching the dielectric layer 116 and the etch stop layer 114 to form a trench; filling a conductive material into the trench; and performing a CMP process to remove the excess conductive material. Each metal line 118 may include a diffusion barrier layer and a metal material located over the diffusion barrier layer. The diffusion barrier layer may be formed of or include: titanium nitride, tantalum nitride, titanium, tantalum, and the like. The metallic material may include copper or a copper alloy.

Fig. 18 illustrates the formation of an etch stop layer 120, a dielectric layer 122, and a via 124. The etch stop layer 120 may be formed of a material similar to that of the etch stop layer 114. The dielectric layer 122 may be formed of a material similar to that of the dielectric layer 116. The vias 124 may be formed using a similar process used to form the metal lines 118, and the vias 124 may be formed using a single damascene process. The structure and material of the vias 124 may be similar to the structure and material of the metal lines 118, except that the metal lines 118 are longer than the vias 124.

Fig. 19 illustrates the formation of an etch stop layer 126, a dielectric layer 128, vias 130, and metal lines 132. Etch stop layer 126 may be formed from a material similar to that of etch stop layer 114 and/or etch stop layer 120. Dielectric layer 128 may be formed from a material similar to the material of dielectric layer 116 and/or dielectric layer 122. The vias 130 and metal lines 132 may be formed using a dual damascene process, which includes: via openings and trenches are formed, the via openings and trenches are filled with a diffusion barrier layer and a copper-containing material, and then a CMP process is performed.

Fig. 20A shows a portion of a structure including gate stack 76 and STI region 24. The gate stack as shown in fig. 19 is elongated and extends over the STI region 24, with the cross-sectional view shown in fig. 20A showing the corresponding portions. Fig. 20B shows an exemplary atomic percentage of oxygen as a function of depth (as indicated by arrow 81) from the top surface of ILD80 to gate electrode 74. The extent of ILD80, capping layer 78 and gate electrode 74 are schematically shown. It should be understood that cap layer 78 may be free of oxygen as deposited. However, after subsequent processing (which may include thermal processing and/or plasma processing), oxygen diffuses down into capping layer 78 and gate electrode 74. Therefore, as shown in fig. 20B, the oxygen atom percentage decreases in the direction of the arrow 81 (fig. 20A). It should be appreciated that, according to some embodiments, the oxygen profile as shown in FIG. 20B may also be obtained along arrow 81' as shown in FIG. 19.

Fig. 21 shows X-ray photoelectron spectroscopy (XPS) spectra of several samples with different structures. Line 140 is the spectrum of tungsten deposited (without heat treatment) that is used in the gate electrode. Line 142 is using N₂O spectra of surface portions of deposited tungsten after the treatment, which simulates the results of oxygen diffusion from the ILD into the underlying metal gate electrode under the influence of plasma deposition of the ILD. Two peaks 144 were found, which are peaks of tungsten oxide. Line 146 is an XPS spectrum of the top of the gate electrode with corresponding samples including a SiN cap layer, where N was performed after deposition of the SiN cap layer₂And (4) O treatment. It can be observed that in line 146, there is no longer a tungsten oxide peak, indicating that the SiN capping layer is effective to prevent oxidation of the metal gate electrode.

Multiple samples were also formed to determine the effect of the dielectric cap layer 78 on the threshold voltage of the corresponding transistor. The samples included n-type finfets and p-type finfets. The sample includes reference n-type finfets and p-type finfets where no capping layer is formed and the ILD80 is in direct contact with the corresponding underlying metal gate electrode 74 and thus the metal oxide is formed, as shown in fig. 21. The threshold voltages of the reference n-type FinFET and the p-type FinFET will be referred to hereinafter as the reference n-type threshold voltage and the reference p-type threshold voltage, respectively. Experimental results show that when 2nm and 3nm SiN capping layers are formed, the threshold voltage of the resulting sample n-type FinFET is reduced by 67mV and 18mV, respectively, compared to the reference n-type threshold voltage, which indicates that the capping layers can significantly increase the threshold voltage of the n-type FinFET. Experimental results also show that when 2nm and 3nm capping layers are formed, the threshold voltage of the resulting p-type FinFET is increased by 11mV and 5mV, respectively, compared to the reference p-type threshold voltage, which indicates that the capping layers can also significantly increase the threshold voltage of the p-type FinFET. The results also show that both the 2nm cap layer and the 3nm cap layer can improve the corresponding FinFET, with the 3nm cap layer having significantly better results than the 2nm cap layer. The results discussed above were obtained from short channel finfets. Sample long channel finfets were also formed and the results were similar to those obtained from short channel finfets.

Embodiments of the present disclosure have some advantageous features. By forming a capping layer having the ability to block oxygen diffusion to the metal gate electrode, oxidation of the metal gate electrode is reduced. The detrimental shift in threshold voltage caused by oxidation of the metal gate electrode is eliminated or at least reduced.

According to some embodiments of the disclosure, a method comprises: forming a dummy gate stack on the semiconductor fin; forming gate spacers on sidewalls of the dummy gate stack; forming a first interlayer dielectric, wherein the gate spacer and the dummy gate stack are located in the first interlayer dielectric; removing the dummy gate stack to form trenches between the gate spacers; forming a replacement gate stack in the trench; depositing a dielectric cap layer, wherein a bottom surface of the dielectric cap layer contacts a first top surface of the replacement gate stack and a second top surface of the first interlayer dielectric; depositing a second interlayer dielectric over the dielectric cap layer; and forming source/drain contact plugs extending into the second interlayer dielectric, the dielectric cap layer, and the first interlayer dielectric. In one embodiment, forming the source/drain contact plugs comprises: a first etch process is performed to etch the second interlayer dielectric, the dielectric cap layer, and the first interlayer dielectric to form a contact opening, wherein the second interlayer dielectric, the dielectric cap layer, and the first interlayer dielectric are etched using the same process gas. In one embodiment, the same process gas includes a first etch gas for etching the second interlayer dielectric and the first interlayer dielectric, and a second etch gas for etching the dielectric cap layer. In one embodiment, the method further comprises: prior to forming the first interlayer dielectric, depositing a contact etch stop layer, wherein the contact etch stop layer contacts the source/drain regions flanking the replacement gate stack, and wherein the first etch process stops on the contact etch stop layer. In one embodiment, the first etch process does not stop on the dielectric cap layer and the first interlayer dielectric. In one embodiment, the method further comprises: etching the second interlayer dielectric and the dielectric cap layer to form a gate contact opening, wherein the second interlayer dielectric and the dielectric cap layer are etched in a continuous etching process using the same process gas; and forming a gate contact plug filling the gate contact opening. In one embodiment, forming the dielectric cap layer includes depositing a non-oxygen containing dielectric layer, and depositing the second interlayer dielectric includes depositing an oxygen containing dielectric layer. In one embodiment, forming the dielectric cap layer includes depositing silicon nitride. In one embodiment, forming the dielectric cap layer includes depositing silicon carbide. In one embodiment, the dielectric capping layer has a thickness in a range between about 3nm to about 5 nm.

In one embodiment, depositing the dielectric cap layer is performed using atomic layer deposition. In one embodiment, forming the replacement gate stack comprises: depositing a gate dielectric layer and a stacked conductive layer into the trench; and performing a planarization process to remove the gate dielectric layer and an excess portion of the stacked conductive layer, wherein a dielectric cap layer is deposited on the planarized top surface of the stacked conductive layer.

According to some embodiments of the disclosure, a method comprises: forming a metal gate in the first ILD; performing a planarization process to make a first top surface of the metal gate flush with a second top surface of the first ILD; depositing a dielectric cap layer, wherein the dielectric cap layer is located over and in contact with both the first top surface and the second top surface; depositing a second ILD over the dielectric cap layer; and etching both the second ILD and the dielectric cap layer in an etching process to form a contact opening, wherein the contact opening passes through both the second ILD and the dielectric cap layer. In one embodiment, the second ILD and the dielectric cap layer are etched using the same etch gas. In one embodiment, the same etch gas includes a first etch gas for etching the second ILD and a second etch gas for etching the dielectric cap layer. In one embodiment, the etching process is performed continuously without stopping on the dielectric cap layer. In one embodiment, the etching process is performed until the metal gate is exposed. In one embodiment, the contact opening further penetrates the first ILD, and the etch process stops on a contact etch stop layer below the first ILD, and the method further comprises: in an additional etch process, the etch is performed through the contact etch stop layer to expose the source/drain regions at the sides of the metal gate.

According to some embodiments of the disclosure, a method comprises: forming a metal gate in the first ILD; depositing a dielectric cap layer, wherein the dielectric cap layer is planar and is located over and in contact with both the metal gate and the first ILD; depositing a second ILD over and in contact with the dielectric cap layer, wherein the first ILD and the second ILD are both thicker than the dielectric cap layer; etching both the second ILD and the dielectric cap layer to form a contact opening, wherein the etching is performed continuously until a top surface of the underlying feature is exposed; and forming a contact plug extending into the contact opening. In one embodiment, the underlying feature comprises a metal gate, and the etching stops on the metal gate.

According to some embodiments of the disclosure, a device comprises: a semiconductor region; a gate stack over the semiconductor region, wherein the gate stack includes a gate electrode; a gate spacer on a sidewall of the gate stack; a first interlayer dielectric, wherein the gate stack and the gate spacer are located in the first interlayer dielectric; a dielectric cap layer including a bottom surface in contact with the top surfaces of the gate electrode, the gate spacer, and the first interlayer dielectric; and a second interlayer dielectric over the dielectric cap layer. In one embodiment, the device further comprises: a source/drain contact plug extending continuously into the second interlayer dielectric, the dielectric cap layer and the first interlayer dielectric. In one embodiment, the atomic percentage of oxygen in the dielectric cap layer continuously decreases from the top surface to the bottom surface of the dielectric cap layer in a region directly above the gate stack. In one embodiment, the second interlayer dielectric has a first atomic percent of oxygen equal to a second atomic percent of oxygen on top of the dielectric cap layer.

According to some embodiments of the disclosure, a device comprises: a semiconductor region; a gate stack located over the semiconductor region; first and second gate spacers contacting opposite sidewalls of the gate stack; a first interlayer dielectric on an opposite side of the gate stack; a dielectric cap layer in contact with the gate stack, wherein the dielectric cap layer also extends into a region directly above the first interlayer dielectric; and a second interlayer dielectric over and in physical contact with the dielectric cap layer, wherein the dielectric cap layer has a lower atomic percent of oxygen than the second interlayer dielectric layer. In one embodiment, the dielectric cap layer comprises silicon nitride and the atomic percent of oxygen in the dielectric cap layer decreases continuously from the top surface to the bottom surface of the dielectric cap layer. In one embodiment, the device further includes source/drain contact plugs that extend continuously into the second interlayer dielectric, the dielectric cap layer, and the first interlayer dielectric. In one embodiment, the dielectric cap layer comprises silicon carbide and the atomic percent of oxygen in the dielectric cap layer decreases continuously from the top surface to the bottom surface of the dielectric cap layer.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

Example 1. a method of manufacturing a semiconductor device, comprising: forming a dummy gate stack on the semiconductor fin; forming gate spacers on sidewalls of the dummy gate stack; forming a first interlayer dielectric, wherein the gate spacer and the dummy gate stack are located in the first interlayer dielectric; removing the dummy gate stack to form trenches between the gate spacers; forming a replacement gate stack in the trench; depositing a dielectric cap layer, wherein a bottom surface of the dielectric cap layer contacts a first top surface of the replacement gate stack and a second top surface of the first interlayer dielectric; depositing a second interlayer dielectric over the dielectric cap layer; and forming source/drain contact plugs extending into the second interlayer dielectric, the dielectric cap layer, and the first interlayer dielectric.

Example 2. the method of example 1, wherein forming the source/drain contact plugs comprises: performing a first etch process to etch the second interlayer dielectric, the dielectric capping layer, and the first interlayer dielectric to form a contact opening, wherein the second interlayer dielectric, the dielectric capping layer, and the first interlayer dielectric are etched using a same process gas.

Example 3. the method of example 2, wherein the same process gas includes a first etch gas to etch the second interlayer dielectric and the first interlayer dielectric, and a second etch gas to etch the dielectric cap layer.

Example 4. the method of example 2, further comprising: depositing a contact etch stop layer prior to forming the first interlayer dielectric, wherein the contact etch stop layer is in contact with source/drain regions flanking the replacement gate stack, and wherein the first etch process stops on the contact etch stop layer.

Example 5. the method of example 4, wherein the first etch process does not stop on the dielectric cap layer and the first interlayer dielectric.

Example 6. the method of example 1, further comprising: etching the second interlayer dielectric and the dielectric cap layer to form a gate contact opening, wherein the second interlayer dielectric and the dielectric cap layer are etched in a continuous etching process using the same process gas; and forming a gate contact plug filling the gate contact opening.

Example 7. the method of example 1, wherein forming the dielectric cap layer includes depositing a non-oxygen containing dielectric layer, and depositing the second interlayer dielectric includes depositing an oxygen containing dielectric layer.

Example 8 the method of example 7, wherein forming the dielectric cap layer includes depositing silicon nitride.

Example 9. the method of example 1, wherein forming the dielectric cap layer comprises depositing silicon carbide.

Example 10. the method of example 1, wherein the dielectric cap layer has a thickness in a range between 3nm and 5 nm.

Example 11 the method of example 1, wherein depositing the dielectric cap layer is performed using a process selected from atomic layer deposition, chemical vapor deposition, and physical vapor deposition.

Example 12. the method of example 1, wherein forming the replacement gate stack comprises: depositing a gate dielectric layer and a stacked conductive layer into the trench; and performing a planarization process to remove excess portions of the gate dielectric layer and the stacked conductive layers, wherein the dielectric cap layer is deposited on the planarized top surface of the stacked conductive layers.

Example 13 a method of fabricating a semiconductor device, comprising: forming a metal gate in the first interlayer dielectric (ILD); performing a planarization process to make a first top surface of the metal gate flush with a second top surface of the first ILD; depositing a dielectric cap layer, wherein the dielectric cap layer is over and in contact with both the first top surface and the second top surface; depositing a second ILD over the dielectric cap layer; and etching both the second ILD and the dielectric cap layer in an etching process to form a contact opening, wherein the contact opening passes through both the second ILD and the dielectric cap layer.

Example 14. the method of example 13, wherein the second ILD and the dielectric cap layer are etched using a same etch gas.

Example 15 the method of example 14, wherein the same etch gas includes a first etch gas to etch the second ILD and a second etch gas to etch the dielectric cap layer.

Example 16. the method of example 13, wherein the etching process is performed continuously without stopping on the dielectric cap layer.

Example 17. the method of example 13, wherein the etching process is performed until the metal gate is exposed.

The method of example 13, wherein the contact opening further passes through the first ILD and the etching process stops on a contact etch stop layer below the first ILD, and further comprising: in an additional etch process, the contact etch stop layer is etched through to expose source/drain regions flanking the metal gate.

Example 19 a method of manufacturing a semiconductor device, comprising: forming a metal gate in the first interlayer dielectric (ILD); depositing a dielectric cap layer, wherein the dielectric cap layer is planar and is over and in contact with both the metal gate and the first ILD; depositing a second ILD over and in contact with the dielectric cap layer, wherein the first ILD and the second ILD are both thicker than the dielectric cap layer; etching both the second ILD and the dielectric cap layer to form a contact opening, wherein the etching is performed continuously until a top surface of an underlying feature is exposed; and forming a contact plug extending into the contact opening.

Example 20. the method of example 19, wherein the underlying feature includes the metal gate, and the etching stops on the metal gate.

Claims

1. A method of manufacturing a semiconductor device, comprising:

forming a dummy gate stack on the semiconductor fin;

forming gate spacers on sidewalls of the dummy gate stack;

forming a first interlayer dielectric, wherein the gate spacer and the dummy gate stack are located in the first interlayer dielectric;

removing the dummy gate stack to form trenches between the gate spacers;

forming a replacement gate stack in the trench;

depositing a dielectric cap layer, wherein a bottom surface of the dielectric cap layer contacts a first top surface of the replacement gate stack and a second top surface of the first interlayer dielectric;

depositing a second interlayer dielectric over the dielectric cap layer; and

forming source/drain contact plugs extending into the second interlayer dielectric, the dielectric cap layer, and the first interlayer dielectric.

2. The method of claim 1, wherein forming the source/drain contact plugs comprises:

performing a first etch process to etch the second interlayer dielectric, the dielectric capping layer, and the first interlayer dielectric to form a contact opening, wherein the second interlayer dielectric, the dielectric capping layer, and the first interlayer dielectric are etched using a same process gas.

3. The method of claim 2, wherein the same process gas comprises a first etch gas for etching the second interlayer dielectric and the first interlayer dielectric, and a second etch gas for etching the dielectric cap layer.

4. The method of claim 2, further comprising:

depositing a contact etch stop layer prior to forming the first interlayer dielectric, wherein the contact etch stop layer is in contact with source/drain regions flanking the replacement gate stack, and wherein the first etch process stops on the contact etch stop layer.

5. The method of claim 4, wherein the first etch process does not stop on the dielectric cap layer and the first interlayer dielectric.

6. The method of claim 1, further comprising:

etching the second interlayer dielectric and the dielectric cap layer to form a gate contact opening, wherein the second interlayer dielectric and the dielectric cap layer are etched in a continuous etching process using the same process gas; and

and forming a gate contact plug filling the gate contact opening.

7. The method of claim 1, wherein forming the dielectric cap layer comprises depositing a non-oxygen containing dielectric layer and depositing the second interlayer dielectric comprises depositing an oxygen containing dielectric layer.

8. The method of claim 7, wherein forming the dielectric cap layer comprises depositing silicon nitride.

9. A method of manufacturing a semiconductor device, comprising:

forming a metal gate in the first interlayer dielectric (ILD);

performing a planarization process to make a first top surface of the metal gate flush with a second top surface of the first ILD;

depositing a dielectric capping layer, wherein the dielectric capping layer is over and in contact with both the first top surface and the second top surface;

depositing a second ILD over the dielectric capping layer; and

in an etching process, both the second ILD and the dielectric cap layer are etched to form a contact opening, wherein the contact opening passes through both the second ILD and the dielectric cap layer.

10. A method of manufacturing a semiconductor device, comprising:

forming a metal gate in the first interlayer dielectric (ILD);

depositing a dielectric cap layer, wherein the dielectric cap layer is planar and is over and in contact with both the metal gate and the first ILD;

depositing a second ILD over and in contact with the dielectric cap layer, wherein both the first and second ILDs are thicker than the dielectric cap layer;

etching both the second ILD and the dielectric capping layer to form a contact opening, wherein the etching is performed continuously until a top surface of an underlying feature is exposed; and

forming a contact plug extending into the contact opening.