CN114519330A

CN114519330A - Integrated circuit adjusting method and device, storage medium and terminal equipment

Info

Publication number: CN114519330A
Application number: CN202011309096.1A
Authority: CN
Inventors: 林智远; 唐振宇; 唐延民
Original assignee: TCL Technology Group Co Ltd
Current assignee: TCL Technology Group Co Ltd
Priority date: 2020-11-19
Filing date: 2020-11-19
Publication date: 2022-05-20

Abstract

The application discloses an adjusting method, an adjusting device, a storage medium and a terminal device of an integrated circuit, wherein the method comprises the steps of obtaining characteristic information corresponding to the integrated circuit, wherein the characteristic information comprises position parameters corresponding to a circuit layout of the integrated circuit and photoelectric characteristic information corresponding to the integrated circuit; and determining a target position parameter corresponding to the integrated circuit based on the characteristic information, and determining the adjusted integrated circuit based on the target position parameter, so that the position parameter is automatically adjusted based on the photoelectric characteristic to realize the automatic adjustment of the circuit layout, thereby improving the design efficiency of the circuit layout and improving the production efficiency of the integrated circuit.

Description

Integrated circuit adjusting method and device, storage medium and terminal equipment

Technical Field

The present disclosure relates to the field of integrated circuit technologies, and in particular, to an adjusting method and apparatus for an integrated circuit, a storage medium, and a terminal device.

Background

Electronic Design Automation (EDA) is widely used in the field of circuit Design, and the Design of a circuit is more efficient through the Electronic Design Automation. However, in the field of TFT circuit design, a professional is generally required to operate software to draw in the TFT layout design process, which makes the TFT circuit design highly dependent on manpower, thereby resulting in low production efficiency.

Disclosure of Invention

The present application provides an adjusting method and apparatus for an integrated circuit, a storage medium, and a terminal device, aiming at the deficiencies of the prior art.

In order to solve the foregoing technical problem, a first aspect of the embodiments of the present application provides a method for adjusting an integrated circuit, where the method includes:

acquiring characteristic information corresponding to an integrated circuit, wherein the characteristic information comprises position parameters corresponding to a circuit layout of the integrated circuit and photoelectric characteristic information corresponding to the integrated circuit;

and determining a target position parameter corresponding to the integrated circuit based on the characteristic information, and determining the adjusted integrated circuit based on the target position parameter.

The method for acquiring the photoelectric characteristic, wherein the determining the target position parameter corresponding to the integrated circuit based on the characteristic information specifically includes:

acquiring a reference position parameter corresponding to the position parameter, wherein the dimension of the reference position parameter is lower than that of the position parameter;

determining an optimized position parameter corresponding to the reference position parameter based on the photoelectric characteristic and the reference position parameter, wherein the dimension of the optimized position parameter is equal to that of the reference position parameter;

and determining a target position parameter corresponding to the position parameter based on the optimized position parameter.

The method for acquiring the photoelectric characteristic, wherein the determining the optimized position parameter corresponding to the reference position parameter based on the photoelectric characteristic and the reference position parameter specifically includes:

acquiring a target function corresponding to the integrated circuit, and determining a target value corresponding to the photoelectric characteristic based on the target function;

and optimizing the reference position parameter by adopting a Bayesian optimizer based on the target value to obtain an optimized position parameter.

The method for acquiring the photoelectric characteristic, wherein the determining the target position parameter corresponding to the position parameter based on the optimized position parameter specifically includes:

inputting the optimized position parameters into a trained third network model, and outputting target position parameters corresponding to the position parameters through the third network model.

The method for acquiring the photoelectric characteristics comprises the steps that the detection network model comprises a first network model and a second network model which are cascaded; the input item of the first network model is a first high-dimensional position parameter, and the output item of the first network model is a first low-dimensional position parameter; and the input item of the third network model is a second low-dimensional position parameter, the output item is a second high-dimensional position parameter, the dimensionality of the first high-dimensional position parameter is equal to the dimensionality of the second high-dimensional position parameter, and the dimensionality of the first low-dimensional position parameter is equal to the dimensionality of the second low-dimensional position parameter.

The method for acquiring the photoelectric characteristics includes that a training process of the third network model specifically includes:

inputting a first position parameter corresponding to each integrated circuit in a training sample into a trained first network model, and outputting a second position parameter through the first network model, wherein the first network model and the second network model are jointly trained;

inputting the second position parameter into a preset network model, and outputting a third position parameter through the preset network model;

and training the preset network model based on the first position parameter and the third position parameter to obtain a third network model.

The method for acquiring the optoelectronic characteristic, wherein after determining a target position parameter corresponding to the integrated circuit based on the characteristic information and determining the adjusted integrated circuit based on the target position parameter, the method further comprises:

and acquiring target photoelectric characteristics corresponding to the target position parameters, and storing circuit parameters formed by the target position parameters and the target photoelectric characteristics.

The method for acquiring the photoelectric characteristics includes, after acquiring the target photoelectric characteristics corresponding to the target position parameters and storing circuit parameters formed by the target position parameters and the target photoelectric characteristics, the method further includes:

selecting a target circuit parameter corresponding to the expected photoelectric characteristic from a plurality of prestored circuit parameters based on the preset expected photoelectric characteristic;

and determining the integrated circuit corresponding to the expected photoelectric characteristic based on the target position parameter in the target circuit parameter.

The method for acquiring the photoelectric characteristic, wherein selecting the target circuit parameter corresponding to the expected photoelectric characteristic from the pre-stored circuit parameters based on the preset expected photoelectric characteristic specifically includes:

acquiring a weight coefficient set corresponding to the expected photoelectric characteristic, wherein the weight coefficient set comprises weight coefficients corresponding to photoelectric parameters in the expected photoelectric characteristic;

based on the desired optoelectronic characteristic and the set of weight coefficients, a target circuit parameter is selected among the number of circuit parameters.

The method for acquiring the photoelectric characteristics comprises the step of storing a plurality of prestored circuit parameters in a KD tree form.

The method for obtaining the photoelectric characteristic, wherein the selecting a target circuit parameter from the plurality of circuit parameters based on the desired photoelectric characteristic and the set of weight coefficients specifically includes:

and performing KD tree search on the circuit parameters based on the expected photoelectric characteristics to obtain target circuit parameters corresponding to the expected photoelectric characteristics, wherein the searching range of the node photoelectric characteristics of the KD tree search in the backtracking process is determined based on the node photoelectric characteristics, the expected photoelectric characteristics and the weight coefficient set.

The method for acquiring the photoelectric characteristic is characterized in that the integrated circuit is a TFT circuit.

A second aspect of the embodiments of the present application provides an adjusting apparatus for an integrated circuit, the adjusting apparatus including:

the device comprises a first acquisition module, a second acquisition module and a third acquisition module, wherein the first acquisition module is used for acquiring characteristic information corresponding to an integrated circuit, and the characteristic information comprises position parameters corresponding to a circuit layout of the integrated circuit and photoelectric characteristic information corresponding to the integrated circuit;

and the first determining module is used for determining a target position parameter corresponding to the integrated circuit based on the characteristic information and determining the adjusted integrated circuit based on the target position parameter.

A third aspect of embodiments of the present application provides a computer-readable storage medium storing one or more programs, which are executable by one or more processors to implement steps in a method for tuning an integrated circuit as described in any one of the above.

A fourth aspect of the embodiments of the present application provides a terminal device, including: a processor, a memory, and a communication bus; the memory has stored thereon a computer readable program executable by the processor;

the communication bus realizes connection communication between the processor and the memory;

the processor, when executing the computer readable program, implements the steps in the tuning method of the integrated circuit as described in any one of the above.

Has the advantages that: compared with the prior art, the method comprises the steps of obtaining characteristic information corresponding to the integrated circuit, wherein the characteristic information comprises position parameters corresponding to a circuit layout of the integrated circuit and photoelectric characteristic information corresponding to the integrated circuit; and determining a target position parameter corresponding to the integrated circuit based on the characteristic information, and determining the adjusted integrated circuit based on the target position parameter, so that the position parameter is automatically adjusted based on the photoelectric characteristic to realize the automatic adjustment of the circuit layout, thereby improving the design efficiency of the circuit layout and improving the production efficiency of the integrated circuit.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without any inventive work.

Fig. 1 is a diagram illustrating an example of a prior art method for adjusting an integrated circuit according to the present application.

Fig. 2 is a flowchart of an adjusting method of an integrated circuit provided in the present application.

Fig. 3 is an exemplary diagram of a TFT circuit.

Fig. 4 is an exemplary diagram of a sub-pixel structure in a TFT circuit.

Fig. 5 is an exemplary diagram of a positional parameter of one component in a sub-pixel structure in a TFT circuit.

Fig. 6 is a diagram illustrating an example of a position parameter adjusting process of an adjusting method of an integrated circuit according to the present application.

Fig. 7 is a diagram illustrating an example of several reference position parameter obtaining processes of an adjusting method of an integrated circuit provided in the present application.

Fig. 8 is a diagram illustrating an example of a position parameter adjusting process of an adjusting method of an integrated circuit according to the present application.

Fig. 9 is a diagram illustrating an example of a process of acquiring a target photoelectric characteristic in an adjustment method of an integrated circuit provided in the present application.

Fig. 10 is a diagram illustrating an example of a process of acquiring a target photoelectric characteristic in an adjustment method of an integrated circuit provided in the present application.

Fig. 11 is a schematic structural diagram of an adjusting apparatus of an integrated circuit according to the present application.

Fig. 12 is a schematic structural diagram of a terminal device provided in the present application.

Detailed Description

In order to make the purpose, technical solution, and effect of the present application clearer and clearer, the present application is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or wirelessly coupled. As used herein, the term "and/or" includes all or any element and all combinations of one or more of the associated listed items.

It will be understood by those within the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. It should be understood that, the sequence numbers and sizes of the steps in this embodiment do not mean the execution sequence, and the execution sequence of each process is determined by its function and inherent logic, and should not constitute any limitation on the implementation process of this embodiment.

The inventor finds that Electronic Design Automation (EDA) is widely applied to the field of circuit Design, and the Design of a circuit is more efficient through the Electronic Design Automation. However, as shown in fig. 1, in the field of TFT circuit design, a professional is generally required to operate software to perform drawing in the TFT layout design process, which makes the TFT circuit design highly dependent on manpower, thereby causing low production efficiency.

In order to solve the above problem, in the embodiment of the present application, the feature information corresponding to the integrated circuit is obtained, the target position parameter corresponding to the integrated circuit is determined based on the feature information, and the adjusted integrated circuit is determined based on the target position parameter, so that the position parameter is automatically adjusted based on the photoelectric characteristic to realize the automatic adjustment of the circuit layout, thereby improving the design efficiency of the circuit layout, and improving the production efficiency of the integrated circuit.

For example, the embodiment of the present application may be applied to a scenario in which a circuit layout of a TFT circuit is designed by a terminal device. In the scene, the terminal equipment can determine a TFT circuit to be designed and acquire a circuit layout corresponding to the TFT circuit; after a circuit layout is obtained, determining a position parameter corresponding to the integrated circuit based on the circuit layout; determining the photoelectric characteristics corresponding to the integrated circuit based on the trained detection network model and the position parameters to obtain the characteristic information corresponding to the integrated circuit, and determining the adjustment parameters corresponding to the position parameters based on the characteristic information; and determining a target position parameter corresponding to the integrated circuit based on the characteristic information, and determining the adjusted integrated circuit based on the target position parameter.

It is to be understood that, in the application scenario described above, although the actions of the embodiment of the present application are described as being performed entirely by the terminal device, the actions may also be performed partly by the terminal device and partly by a server connected to the terminal device. For example, after acquiring a circuit layout corresponding to the integrated circuit, the terminal device inputs the circuit layout into the server, so that the server acquires the circuit layout. The server can respond to the input circuit layout of the terminal equipment and determine the corresponding position parameters of the integrated circuit based on the circuit layout; and determining the photoelectric characteristics corresponding to the integrated circuit based on the trained detection network model and the position parameters to obtain the characteristic information corresponding to the integrated circuit, determining the target position parameters corresponding to the integrated circuit based on the characteristic information, and determining the adjusted integrated circuit based on the target position parameters. Thus, the present application is not limited in terms of executing a subject as long as the actions disclosed in the embodiments of the present application are executed.

It should be noted that the above application scenarios are only shown for the convenience of understanding the present application, and the embodiments of the present application are not limited in any way in this respect. Rather, embodiments of the present application may be applied to any scenario where applicable.

The following further describes the content of the application by describing the embodiments with reference to the attached drawings.

The present embodiment provides a method for adjusting an integrated circuit, as shown in fig. 2 and 8, the method including:

and S10, acquiring characteristic information corresponding to the integrated circuit.

Specifically, the integrated circuit may be a chip integrated circuit, an integrated circuit of a display panel, or an integrated circuit of a pixel unit. In one implementation manner of this embodiment, the integrated circuit is a TFT circuit, and the TFT circuit is used for manufacturing a TFT backplane. For example, as shown in fig. 3, the TFT circuit may include a Gate Driver on Array (GOA) and a plurality of pixels, each of the plurality of pixels includes three sub-pixel units, namely an R pixel unit, a G pixel unit, and a B pixel unit, wherein, as shown in fig. 4, the sub-pixel units may include a circuit element and a connection line, the circuit element may include a capacitor, a TFT transistor, a light emitting diode, and the like, and the connection line may include a scan line, a data line, and the like.

The characteristic information comprises position parameters corresponding to a circuit layout of the integrated circuit and photoelectric characteristics corresponding to the integrated circuit. The position parameters are parameterized representation of the circuit layout, and the position parameters can determine components included in the circuit layout, relative position relations among the components, position information of the components in the circuit layout and the like. In other words, the position parameter is a parameter vector for representing the circuit layout, and the circuit layout can be drawn based on the position parameter. The photoelectric characteristics are used for reflecting the photoelectric properties of the driving circuit corresponding to the circuit layout, wherein the photoelectric characteristics may include an aperture ratio, a charging rate, a maximum voltage and the like.

The circuit layout is used for mapping the circuit design of the integrated circuit to a physical description layer, so that the integrated circuit can be mapped to a wafer for production, wherein the circuit layout comprises related physical information such as component types, component sizes, relative positions among the components, connection relations among the components and the like in the integrated circuit. The circuit layout of the integrated circuit can be automatically generated in advance, and can also be manually designed by a layout designer. In an implementation manner of this embodiment, the circuit layout is automatically generated, and a generation process of the circuit layout may be: determining an integrated circuit to be designed, acquiring a plurality of components corresponding to the integrated circuit and relative position relations among the components, and generating a circuit layout of the integrated circuit based on the relative position relations.

In an implementation manner of this embodiment, the position parameter may be obtained in advance and stored in a local terminal device, or the position parameter may be sent to the terminal device by an external device, or the position parameter may be obtained by a cloud, or the position parameter may be determined by the terminal device based on a circuit layout corresponding to the integrated circuit. In an implementation manner of this embodiment, the feature information is determined by the terminal device based on a circuit layout corresponding to the integrated circuit, and accordingly, the obtaining of the feature information corresponding to the integrated circuit specifically includes:

and A10, obtaining a circuit layout corresponding to the integrated circuit.

And A20, identifying the area information of the components in the circuit layout.

A30, determining the position parameters of the circuit layout based on the acquired region information;

and A40, determining the corresponding photoelectric characteristics of the integrated circuit based on the position information to obtain the corresponding characteristic information of the integrated circuit.

Specifically, the component is a device for forming the circuit layout, wherein the component may include a metal layer, a TFT transistor, a capacitor, an ITO film, and the like. The region information is used for positioning the component, and the position region of the component in the circuit layout and the component type of the component can be determined through the region information. It can be understood that the region information includes positioning information, size information and category information of the component, the positioning information is used for reflecting the position of the component in the circuit layout, the size information is used for reflecting the size of the component, and the category information is used for reflecting the device category of the component. For example, the size information is the height and width of the recognition area corresponding to the component, and the position information is the distance between the center of the recognition area corresponding to the component and the image center of the panel image. Of course, in practical applications, the position information may also be determined in other manners, for example, a distance from a center point of the identification region corresponding to the component to an upper left corner of the panel image, a distance from the upper left corner of the identification region corresponding to the component to the upper left corner of the panel image, and the like. The size information may be determined in other manners, for example, a perimeter of the identification region corresponding to the component, an area of the identification region corresponding to the component, and the like.

Based on this, in one implementation manner of the present embodiment, the area information may be in the form of a circuit parameter, where the circuit parameter includes three data items, namely, positioning information, size information, and category information. For example, the area information is { (100 ), (20,30), and capacitance }, (100 ) represents coordinate information of an anchor point in a component in a coordinate system corresponding to the circuit layout, 20 in (20,30) may represent a width of a rectangular area corresponding to the component, 30 may represent a width of a rectangular area corresponding to the component, and capacitance represents that a device type of the component is capacitance. In addition, the rectangular region refers to a smallest rectangle containing the component. It should be understood that the rectangular area is only an example, and may also be a circle, an ellipse, a triangle, a regular pentagon, and the like, and when the shapes are different, the representation form of the size information is also different, and it is not limited to this, but only an example is given here, for example, when the component corresponds to a circular area, the area information may be a circular coordinate and a circular radius.

In an implementation manner of this embodiment, the identifying the region information of the component in the circuit layout specifically includes:

inputting the circuit layout into a trained recognition network model;

and determining the regional information of the components in the circuit layout through the identification network model.

Specifically, the recognition network model may be a network model trained in advance and used for recognizing the region information of each component in the circuit layout. It can be understood that the recognition network model is a network model trained in advance, the input item of the recognition network model is a circuit layout, the output item of the recognition network model is regional information, when the circuit layout comprises one component, the regional information is one, when the circuit layout comprises a plurality of components, the regional information is a plurality of, and the plurality of regional information and the one-to-one correspondence of the plurality of components are realized. For example, the circuit layout includes a component a and a component B, and the region information output by the recognition network model includes region information a and region information B, where the region information a corresponds to the component a and is used for positioning the component a, and the region information B corresponds to the component B and is used for positioning the component B.

In an implementation manner of this embodiment, the determining the position parameter of the circuit layout based on the acquired region information specifically includes:

for each component in the circuit layout, acquiring a reference part corresponding to the component;

determining a sub-position parameter corresponding to the component based on the area information of the component by taking the reference component as a reference;

and determining the position parameters of the circuit layout based on all the acquired sub-position parameters.

Specifically, the reference component is a reference of the component and is used for determining a relative positional relationship between the component and the reference component, for example, a distance between the component and the reference component, a distance between an edge of the component and an edge of the reference component, an inclination angle of the component with respect to the reference component, and the like. The reference component may be determined based on the acquired region information corresponding to each component, or may be determined based on a preset component position relationship list, where the component position relationship list may store the position relationships among all components included in the circuit layout, for example, a circuit version includes a component a and a component B, and the component a and the component B in the component position relationship list are adjacent to each other.

In an implementation manner of this embodiment, the reference component is determined based on the acquired region information corresponding to each component, and the acquisition process may specifically be: after the area information corresponding to each component is obtained, candidate components located around the component are selected from all the components based on the area information, and all the obtained candidate components are used as reference components of the component. Therefore, the reference component corresponding to the component can be automatically determined according to the acquired region information, and the parameterization speed of the circuit layout can be improved.

In an implementation manner of this embodiment, the reference component is determined based on a preset component position relationship list, and the determining process may specifically include: and for each component, selecting each candidate component related to the component from the component position relation list, and taking all the selected candidate components as the reference components corresponding to the component. Therefore, the reference component is determined through the preset component position relation list, the problem of reference component error caused by the error of the area information can be avoided, and the accuracy of the reference component can be improved.

The sub-position parameters are used for reflecting the size information of the component and the position information between the component and the reference component, and the size of the component, the distance between the component and the reference component and the like can be determined through the sub-position parameters. Thus, the sub-position parameters are used to reflect a plurality of attributes of the component, including the size of the component, the distance between the component and the reference component, and the like. Correspondingly, the sub-position parameters comprise a plurality of position parameter items, the position parameter items correspond to the attributes one by one, and the value of each position parameter item is the attribute value of the corresponding attribute. The attributes are determined based on design rules of the circuit layout, for example, line width rules: the minimum width of a polygon in the layout; maximum (minimum) size limitation: the width or length of the polygon; the spacing rule is as follows: the minimum distance between polygons; the bounding rule: a minimum dimension of overlap between and surrounding one layer of wire with another layer of wire; the rule of overlap: the minimum size of overlap between the two layers; minimum area rule: on the premise of meeting the basic requirements, the minimum layout area is ensured as much as possible.

Based on the method, after the reference component corresponding to the component is obtained, the position parameter items included in the sub-position parameters corresponding to the component are determined according to the rule of the circuit layout, and the parameter values corresponding to the position parameter items are sequentially calculated according to the region information, so that the sub-position parameters corresponding to the component are obtained. For example, if the integrated circuit is a TFT sub-pixel circuit, the capacitor in the TFT sub-pixel circuit is a rectangle with cut corners, the reference component corresponding to the capacitor is a TFT and the bottom edge of the substrate, and the sub-position parameters corresponding to the capacitor may include a length of the rectangle, a width of the matrix, a distance from the bottom edge of the substrate, a distance from the TFT, a size of the cut corner region, and the like.

For example, the following steps are carried out: as shown in fig. 5, a capacitor in the TFT sub-pixel circuit has 12 sub-position parameters, which are distances a, B, C, D, E, F, G, H, I, J, K and L in the figure, and the sub-position parameter corresponding to the capacitor can be represented as (a, B, C, D, E, F, G, H, I, J, K, L).

In one implementation manner of this embodiment, the sub-position parameter is a sub-position vector; the determining the position parameters of the circuit layout based on the acquired all sub-position parameters specifically includes:

and splicing the sub position parameters to obtain the position parameters of the circuit layout.

Specifically, the position parameters are formed by splicing sub-position parameters, and the dimension of the position parameter is equal to the sum of the dimensions of the sub-position parameters, for example, the sub-position parameters corresponding to the circuit layout include a sub-position parameter a and a sub-position parameter B, where the position parameter a is (a1, a2) and the sub-position parameter B is (B1, B2), and then the position parameters are (a1, a2, B1, B2). In addition, in order to determine the components corresponding to each position parameter item in the spliced position parameters, each position parameter item in the position parameters may be configured with a component type of the corresponding component, where the component type may be used as a corner mark of each position parameter item in the sub-position parameters, a suffix of each position parameter item in the sub-position parameters, a prefix of each position parameter item in the sub-position parameters, or the like.

In one implementation of this embodiment, the optoelectronic characteristic is determined based on a trained inspection network model. Correspondingly, the determining the photoelectric characteristic corresponding to the integrated circuit based on the position information to obtain the characteristic information corresponding to the integrated circuit is specifically;

and inputting the position information into the detection network model, and outputting the photoelectric characteristics corresponding to the integrated circuit through the detection network model.

Specifically, the detection network model is trained in advance and is used for determining the corresponding photoelectric characteristic of the integrated circuit. It is understood that the detection network model is used to convert the position parameters into the photoelectric characteristics, and accordingly, the input items of the detection network model are the position parameters, and the output items of the detection network model are the photoelectric characteristics, wherein the photoelectric characteristics may include an aperture ratio, a charging rate, RC, LCS, a voltage deviation Bestvcom, a feed through, a charging time, and the like.

In an implementation manner of this embodiment, the detecting network model includes a first full-connection module, a transformation module, and a second full-connection module, and the determining, based on the trained detecting network model and the position parameter, the optoelectronic characteristic corresponding to the integrated circuit specifically includes:

inputting the position parameters into a first full-connection module, and outputting a first feature vector through the first full-connection module;

inputting the first feature vector into a transformation module, and outputting a second feature vector through the transformation module, wherein the dimension of the first feature vector is equal to that of the second feature vector;

and inputting the second characteristic vector into a second full-connection module, and outputting the corresponding photoelectric characteristic of the integrated circuit through the second full-connection module.

Specifically, the first full-connection module is configured to perform linear transformation on the position parameter, so as to perform dimension reduction on the position parameter. The first eigenvector is a low-dimensional vector obtained by performing linear transformation on the position parameters through the first full-connection module, and correspondingly, the vector dimension of the first eigenvector is smaller than the vector dimension of the position parameters, wherein the value range of the vector dimension of the position parameters can be 50-500, and the value range of the vector dimension of the first eigenvector can be 5-500. In a specific implementation manner, the range of the vector dimension of the position parameter may be 50 to 100, and the range of the vector dimension of the first feature vector may be 5 to 50, for example, the vector dimension of the position parameter is 100, the vector dimension of the first feature vector is 50, and the like.

The transformation module is configured to transform the first feature vector into a second feature vector, and a vector dimension of the second feature vector is equal to a vector dimension of the first feature vector, for example, the vector dimension of the first feature vector is 50, and then the vector dimension of the second feature vector is 50. In an implementation manner of this embodiment, the transformation module may employ a sigmoid function, a tanh function, and the like. The output item of the second fully-connected layer is an optoelectronic characteristic, and the dimension of the output item of the second fully-connected layer can be determined according to the characteristic item included in the optoelectronic characteristic acquired according to the actual application requirement, for example, the dimension of the output item of the second fully-connected layer is 7 if the optoelectronic characteristic includes an aperture ratio, a charging rate, RC, LCS, a voltage deviation Bestvcom, a feed-through and a charging time.

In an implementation manner of this embodiment, the detection network model may include two cascaded network models, which are a first network model and a second network model, respectively, where the first network model is used to perform dimension reduction on the position parameter, and the second network model is used to determine the photoelectric characteristic corresponding to the position parameter. Correspondingly, the determining the corresponding optoelectronic characteristic of the integrated circuit based on the trained detection network model and the position parameter specifically includes:

inputting the position parameters into a first network model, and outputting candidate position parameters through the first network model;

and inputting the candidate position parameters into the second network model, and outputting the photoelectric characteristics corresponding to the integrated circuit through the second network model.

Specifically, the candidate position parameter is an output item of the first network model, the input item of the second network model is a candidate position parameter, and the output item is a photoelectric characteristic. The first network model is used for reducing the dimension of the position parameter to obtain a candidate position parameter after dimension reduction, and correspondingly, the vector dimension of the candidate position parameter is smaller than that of the position parameter, wherein the value range of the vector dimension of the position parameter can be 50-500, and the value range of the vector dimension of the candidate position parameter can be 5-500. In a specific implementation manner, the range of the vector dimension of the position parameter may be 50 to 100, and the range of the vector dimension of the candidate position parameter may be 5 to 50, for example, the vector dimension of the position parameter is 100, the vector dimension of the candidate position parameter is 50, and the like.

In an implementation manner of this embodiment, the first network model may include a third fully-connected module and a non-linear transformation module, the second network model may include a fourth fully-connected module, the third fully-connected module is configured to perform linear transformation on the position parameters to perform dimensionality reduction on the position parameters, the third fully-connected module is connected to the non-linear transformation module, an output item of the third fully-connected module is an input item of the non-linear transformation module, an output item of the non-linear transformation module is a candidate position parameter, and a vector dimension of the candidate position parameter is equal to a vector dimension of an output item of the third fully-connected module, for example, a vector dimension of an output item of the third fully-connected module is 50, and then a vector dimension of the candidate position parameter is 50. In an implementation manner of this embodiment, the nonlinear transformation module may employ a sigmoid function, a tanh function, and the like.

In an implementation manner of this embodiment, the second network model includes a fourth fully-connected module, and a dimension of an output item of the fourth fully-connected module may be determined according to a characteristic item included in the optoelectronic characteristic acquired according to an actual application requirement, for example, the optoelectronic characteristic includes an aperture ratio, a charging rate, an RC, an LCS, a voltage deviation Bestvcom, a feed through, and a charging time, and then the dimension of the output item of the second fully-connected layer is 7.

In an implementation manner of this embodiment, the training process of detecting the network model specifically includes:

acquiring a training sample set;

inputting the training position parameters in the training sample set into a preset network model, and outputting the predicted photoelectric characteristics corresponding to the training position parameters through the preset network model;

and training the preset network model based on the predicted photoelectric characteristics and the target photoelectric characteristics to obtain the detection network model.

Specifically, the preset network model may be preset and used for generating a detection network model based on a training sample set; the detection network model is obtained by training a preset network model by adopting a training sample set and is used for determining the photoelectric characteristics corresponding to the position parameters. It can be understood that, after the preset network model is trained based on the training sample set, a detection network model can be obtained, wherein the model structure of the detection network model is the same as that of the preset network model, and the detection network model is different from the preset network model in that: the model parameters configured by the network model are detected to be model parameters obtained through training, and the model parameters configured by the network model are preset to be initial model parameters.

In an implementation manner of this embodiment, the training sample set includes a plurality of training position parameters and target photoelectric characteristics corresponding to the training position parameters, where each of the plurality of training position parameters corresponds to a circuit layout, and the target photoelectric characteristics corresponding to the training position parameters are photoelectric characteristics of an integrated circuit corresponding to the circuit layout. And the target photoelectric characteristic is used as a mark value of a training position parameter corresponding to the target photoelectric characteristic, and after a predicted photoelectric characteristic corresponding to the training position parameter is determined through a preset network model, a loss value corresponding to the predicted photoelectric characteristic is determined by taking the target photoelectric characteristic as a standard, so that reverse training is performed on the preset network model based on the loss value to optimize the model parameter of the preset network model.

acquiring a training integrated circuit set;

for each training integrated circuit, determining a training position parameter corresponding to a circuit layout of the training integrated circuit, and determining a target photoelectric characteristic corresponding to the training integrated circuit through a circuit simulator;

and determining a training sample set based on the training position parameters and the target photoelectric characteristics corresponding to the training integrated circuits.

Specifically, the training integrated circuit set may include a plurality of training integrated circuits, each of which is pre-designed and tested. Each of the plurality of training integrated circuits corresponds to a training position parameter, wherein the determination process of the training position parameter may refer to the determination process of the position parameter, and is not described herein again. In addition, the target photoelectric characteristic is determined based on a circuit simulator, and the determination process can be as follows: and for each training integrated circuit, acquiring a circuit layout corresponding to the training integrated circuit, and outputting the target photoelectric characteristic corresponding to the training integrated circuit through the circuit simulator.

Further, after a training position parameter and a target photoelectric characteristic corresponding to the training integrated circuit are obtained, the training position parameter and the target photoelectric characteristic are used as a circuit parameter. The plurality of training integrated circuits can determine a plurality of groups of circuit parameters, and each group of circuit parameters comprises a training position parameter and a target photoelectric characteristic. Therefore, after a plurality of groups of circuit parameters corresponding to a plurality of training integrated circuits are obtained, a set formed by the plurality of groups of circuit parameters corresponding to the plurality of training integrated circuits can be used as a training sample set of the preset network model.

And S20, determining a target position parameter corresponding to the integrated circuit based on the characteristic information, and determining the adjusted integrated circuit based on the target position parameter.

Specifically, the target position parameter is an adjusted position parameter corresponding to the position parameter, and the vector dimension of the target position parameter is the same as the vector dimension of the position parameter, for example, the vector dimension of the position parameter is 100, and then the vector dimension of the target position parameter is 100. In addition, after the target position parameter is determined, a circuit layout can be determined based on the target position parameter, and an integrated circuit can be processed based on the circuit layout.

In an implementation manner of this embodiment, the determining the target position parameter corresponding to the integrated circuit based on the feature information specifically includes:

acquiring a reference position parameter corresponding to the position parameter;

determining an optimized position parameter corresponding to the reference position parameter based on the photoelectric characteristic and the reference position parameter;

Specifically, the vector dimension of the reference position parameter is smaller than the vector dimension of the position parameter, and the reference position parameter is obtained by performing dimension reduction transformation on the position parameter. In this embodiment, the reference position parameter may be determined by the detection network model, and when the detection network model includes the first network model and the second network model, the reference position parameter is an output item of the first network model, and when the detection network model includes the first fully-connected module, the transformation module, and the second fully-connected module, the reference position parameter is an output item of the transformation module.

In an implementation manner of this embodiment, the determining, based on the photoelectric characteristic and the reference position parameter, an optimized position parameter corresponding to the reference position parameter specifically includes:

Specifically, the vector dimension of the optimized position parameter is the same as the vector dimension of the reference position parameter, and the optimized position parameter is a position parameter whose maximum probability makes the objective function be improved. It is understood that optimizing the position parameter may maximize the probability that the error becomes smaller based on the objective function. The objective function is determined based on the photoelectric characteristic limit condition corresponding to the integrated circuit, and the determination process of the objective function and the expression form of the objective function are the same as those of the objective function described below, and specifically, the following description of the objective function may be used as parameters. Further, the target value is determined by inputting the photoelectric characteristic to an objective function, wherein the objective function is an objective function having the photoelectric characteristic as an argument. After the target value is obtained, the Bayesian optimizer calculates the optimal position parameter with the maximum probability to improve the target function value according to the target value, the reference position parameter and the target value. In this embodiment, a bayesian optimizer is used to perform gaussian regression for optimization, and other optimizers, such as a genetic algorithm and an annealing algorithm, may also be used in other implementation manners.

In an implementation manner of this embodiment, the determining, based on the optimized location parameter, a target location parameter corresponding to the location parameter specifically includes:

Specifically, the third network model is pre-trained and is configured to perform dimension raising on the optimized position parameter to obtain a target position parameter, where a vector dimension of the target position parameter is greater than a vector dimension of the optimized position parameter, and the vector dimension of the target position parameter is equal to the vector dimension of the position parameter. It is to be understood that the dimensions of the output items of the third network model are the same as the dimensions of the input items of the detection model, and when the detection network model includes the first fully-connected module, the transformation module, and the second fully-connected module, the dimensions of the input items of the third network model are the same as the dimensions of the output items of the transformation module; when the detection network model comprises the first network model and the second network model, the dimension of the input item of the third network model is the same as the dimension of the output item of the first network model.

For example, the following steps are carried out: the detection network model comprises a first network model and a second network model which are cascaded; the input item of the first network model is a first high-dimensional position parameter, and the output item of the first network model is a first low-dimensional position parameter; and the input item of the third network model is a second low-dimensional position parameter, the output item is a second high-dimensional position parameter, the dimensionality of the first high-dimensional position parameter is equal to the dimensionality of the second high-dimensional position parameter, and the dimensionality of the first low-dimensional position parameter is equal to the dimensionality of the second low-dimensional position parameter.

In an implementation manner of this embodiment, the training process of the third network model specifically includes:

Specifically, the first network model is included in the detection network model, and when the detection network model includes a first network model and a second network model, the first network model is the first network model in the detection network model, and when the detection network model includes a first full-connection module, a transformation module, and a second full-connection module, the detection network model may be divided into the first network model and the second network model, where the first network model includes the first full-connection module and the transformation module, and the second network model includes the second full-connection module.

Further, the input item of the third network model is determined based on the first network model, and the input item of the third network model is the output item of the first network model, so that when the third network model is trained, a training sample corresponding to the third network model is determined based on the trained first network model, the third network model is trained by combining the first network model and the third network model, and the model coefficient of the first network model remains unchanged in the process of training the third network model.

In an implementation manner of this embodiment, the third network model is obtained by training after combining the first network model and the third network model. In the training process, the first position parameter is an input item of the first network model, the second position parameter is an output item of the first network model, and is an input item of the third network model, and the third position parameter is an output item of the third network model, wherein the first position parameter is a target value corresponding to the third position parameter, so that a loss item can be determined based on the first position parameter and the third position parameter, and the third network model can be trained based on the loss item. In addition, the first network model is trained, and the first network model is trained based on a second network model in the detection network model, in other words, the first network model is obtained by training the detection network model.

In an embodiment, as shown in fig. 7, after the position parameter is adjusted to obtain a target position parameter, a target photoelectric characteristic corresponding to the target position parameter may be obtained, a target photoelectric characteristic corresponding to the target position parameter is obtained, and a circuit parameter formed by the target position parameter and the target photoelectric characteristic is saved. In addition, the above adjustment process may be continuously performed after the target photoelectric characteristic is acquired until the target photoelectric characteristic reaches a preset condition, or the number of times of the cyclic execution reaches a preset requirement. Therefore, a plurality of circuit parameters can be obtained, wherein each circuit parameter in the plurality of circuit parameters comprises a position parameter and a photoelectric characteristic, the position parameter corresponds to a circuit layout, and the photoelectric characteristic is the photoelectric characteristic corresponding to the circuit layout.

In summary, this embodiment provides a method for adjusting an integrated circuit, where the method includes obtaining feature information corresponding to the integrated circuit, and determining an adjustment parameter corresponding to the position parameter based on the feature information; and determining a target position parameter corresponding to the integrated circuit based on the characteristic information, and determining the adjusted integrated circuit based on the target position parameter, so that the position parameter is automatically adjusted based on the photoelectric characteristic to realize the automatic adjustment of the circuit layout, thereby improving the design efficiency of the circuit layout and improving the production efficiency of the integrated circuit.

In one embodiment, as shown in fig. 6, the method for adjusting an integrated circuit specifically includes:

acquiring characteristic information corresponding to an integrated circuit, wherein the characteristic information comprises position parameters corresponding to a circuit layout of the integrated circuit and photoelectric characteristics corresponding to the integrated circuit;

determining an adjustment parameter corresponding to the position parameter based on the characteristic information;

and adjusting the position parameters based on the adjustment parameters to obtain target position parameters, and determining the adjusted integrated circuit based on the target position parameters. .

Specifically, the process of acquiring the characteristic information may refer to the description of the above embodiment, which is not repeated herein, and the process of determining the target position parameter corresponding to the position parameter based on the photoelectric characteristic and the position parameter and determining the adjusted integrated circuit based on the target position parameter is mainly described herein.

The adjustment parameter is used for adjusting the position parameter, and the position parameter can be adjusted through the adjustment parameter to obtain a target position parameter corresponding to the position parameter, wherein the target position parameter is used for determining a circuit layout of the integrated circuit. The vector dimension of the adjustment parameter is the same as the vector dimension of the position parameter, for each position parameter item in the position parameters, an adjustment parameter item corresponding to the position parameter item exists in the adjustment parameter, and the adjustment parameter item is used for adjusting the corresponding position parameter item, wherein the correspondence between the adjustment parameter item and the position parameter item means that the position serial number of the adjustment parameter item in the adjustment parameter is the same as the position serial number of the position parameter item in the position parameters. For example, the position parameter is a 50-dimensional vector, the adjustment parameter term is a 50-dimensional vector, and the 25 th adjustment parameter term in the adjustment parameter terms corresponds to the 25 th position parameter term in the position parameter. In addition, the vector dimension of the target position parameter is the same as the vector dimension of the position parameter, each target position parameter item in the target position parameter corresponds to each position parameter item in the position parameter one by one, and each target position parameter item is obtained by calculating the corresponding position parameter item and the adjustment parameter item corresponding to the position parameter item.

In an implementation manner of this embodiment, the determining, based on the photoelectric characteristic and the position parameter, an adjustment parameter corresponding to the position parameter specifically includes:

obtaining an error value corresponding to the photoelectric characteristic;

determining an adjustment parameter corresponding to the position parameter based on the error value and the position parameter

Specifically, the error value is used to reflect an error between the optoelectronic characteristic and an optoelectronic characteristic limiting condition, where the optoelectronic characteristic limiting condition is corresponding to the integrated circuit and is used to limit a minimum optoelectronic characteristic requirement of the integrated circuit. The photoelectric characteristics comprise a plurality of photoelectric parameters, and the photoelectric characteristic limiting conditions comprise lower threshold values corresponding to part of the photoelectric parameters in the plurality of photoelectric parameters. For example, the photoelectric characteristic includes an aperture ratio, a charging rate, and a peak voltage, and the photoelectric characteristic limitation condition may include a lower threshold of the aperture ratio, a lower threshold of the charging rate, and a lower threshold of the peak voltage; alternatively, the optical-electrical characteristic limitation condition may include a lower threshold of the charging rate and a lower threshold of the peak voltage, or the optical-electrical characteristic limitation condition may include a lower threshold of the peak voltage. Of course, the limitation condition of the photoelectric characteristic may not include the lower threshold of any photoelectric parameter, and the limitation condition of the photoelectric characteristic is that the larger each photoelectric parameter is, the better the reference position parameter corresponding to the reference photoelectric characteristic is, and conversely, the smaller each photoelectric parameter is, the worse the reference position parameter corresponding to the reference photoelectric characteristic is.

In an implementation manner of this embodiment, the obtaining the error value corresponding to the photoelectric characteristic specifically includes:

acquiring photoelectric characteristic limiting conditions corresponding to the integrated circuit, and determining a target function corresponding to the integrated circuit based on the photoelectric characteristic limiting conditions;

and determining the photoelectric characteristic corresponding error value based on the objective function.

Specifically, the objective function may be preset, and the objective function corresponds to the optical-electrical characteristic limiting condition, and after the optical-electrical characteristic limiting condition corresponding to the integrated circuit is determined, the corresponding objective function may be selected according to the optical-electrical characteristic limiting condition. It can be understood that, an objective function set is preset, the objective function set includes a plurality of objective functions, each objective function in the plurality of objective functions corresponds to one photoelectric characteristic limiting condition, after the photoelectric characteristic limiting condition corresponding to the integrated circuit is determined, one objective function may be selected from the objective function set based on the photoelectric characteristic limiting condition, and the objective function is used as an objective function for determining an error value corresponding to the photoelectric characteristic.

The objective function in the objective function set may be established according to actual applications, and an application scenario is described herein. In this application scenario, the photoelectric characteristic includes three photoelectric parameters, i.e., an aperture ratio a, a charging rate b, and a peak voltage c, and the corresponding relationship between the objective function and the photoelectric characteristic limiting condition may be:

when the photoelectric characteristic limitation conditions are an aperture ratio a > a0, a charging ratio b > b0, and a peak voltage c > c0, where a0 is a lower threshold of the aperture ratio, b0 is a lower threshold of the charging ratio, and c0 is a lower threshold of the peak voltage, the objective function f (a, b, c) may be:

f(a,b,c)＝sigmoid(a-a0)*sigmoid(b-b0)*sigmoid(c-c0)

wherein a represents an aperture ratio, b represents a charging rate, c represents a peak voltage, and sigmoid represents a sigmoid function;

when the optoelectronic characteristic constraints are a charging rate b > b0 and a peak voltage c > c0, where b0 is the lower threshold of the charging rate and c0 is the lower threshold of the peak voltage, the objective function f (a, b, c) may be:

f(a,b,c)＝(a-a0)*sigmoid(b-b0)*sigmoid(c-c0)

wherein a represents an opening rate, b represents a charging rate, c represents a peak voltage, and sigmoid represents a sigmoid function;

when the aperture ratio a, the charging ratio b and the peak voltage c in the limitation condition of the optoelectronic characteristic have no lower threshold, the objective function f (a, b, c) may be:

f(a,b,c)＝ka*(a-a0)+kb*(b-b0)+kc*(c-c0)；

wherein ka, kb, kc are weight coefficients, a0 is a lower threshold of an opening rate, b0 is a lower threshold of a charging rate, and a lower threshold of a peak voltage of c0, and ka, kb, kc, a0, b0, and c0 can be set according to actual requirements.

Further, after the target function is acquired, since the target function is a function having the photoelectric characteristic as an argument, the target function can be converted into a function having the position parameter as an argument. Therefore, the photoelectric characteristics are determined based on the position parameters, a candidate function is arranged between the position parameters and the photoelectric characteristics, each photoelectric parameter in the photoelectric characteristics can be represented by the position parameters based on the candidate function, then each photoelectric characteristic represented by the position parameters is substituted into the target function to obtain a converted target function, and the converted target function is used as the target function corresponding to the photoelectric characteristics. After an objective function with the position parameters as arguments is obtained, the position parameters are input into the objective function, and the error value can be obtained. Of course, in practical applications, the error value may also be obtained by directly inputting the photoelectric characteristic into an objective function with the photoelectric characteristic as an argument.

In an implementation manner of this embodiment, the determining, based on the error value and the position parameter, an adjustment parameter corresponding to the position parameter specifically includes:

for each position parameter item in the position parameters, determining a gradient value corresponding to the position parameter item based on the error value and the objective function, and determining an adjustment parameter item corresponding to the position parameter item based on the gradient value;

and all the obtained adjustment parameter items form adjustment parameters corresponding to the position parameters.

Specifically, the gradient value is used to determine an adjustment parameter item corresponding to the position parameter item. In an implementation manner of this embodiment, the gradient value may be calculated by: dY/dXi ═ f (X1, X2, X3, … Xi +. DELTA.xi, … Xn) -Y0, i ═ 1,2,3 … n, wherein dY/dXi represents the gradient value corresponding to the position parameter item Xi, and Y ═ f (X1, X2, X3, … Xi, … Xn) is the objective function with the position parameter item as an argument; xi is the ith position parameter item in the position parameters, Δ Xi is the variation corresponding to the position parameter item Xi, n represents the number of the position parameter items, and Y0 represents the error value. The variation corresponding to each position parameter item can be the same, or the variation corresponding to part of the position parameter items can be the same, and the variation corresponding to part of the position parameters is different; the variation corresponding to each position parameter item may be different, where the variation may be preset according to an actual application situation.

The calculation formula of the adjustment parameter term can be as follows:

Xi＝Xi+gamma_i*(dY/dXi)*△Xi,i＝1,2,3…n

wherein, Δ Xi is the variation corresponding to the position parameter term Xi, and gamma _ i is the weighting coefficient corresponding to the position parameter term Xi.

In one implementation, the adjusting the position parameter based on the adjustment parameter to obtain the target position parameter specifically includes:

for each position parameter item in the position parameters, determining an adjustment parameter item corresponding to the position parameter item in the adjustment parameters;

determining the element sum of the position parameter item and the adjustment parameter item, and taking the element sum as a target position parameter item corresponding to the position parameter item;

and taking the position parameters formed by all the target position parameter items as target position parameters.

Specifically, the vector dimension of the adjustment parameter is the same as the vector dimension of the position parameter, and adjustment parameter items in the adjustment parameter correspond to position parameter items in the position parameter one to one, so that for each position parameter item, the corresponding adjustment parameter item can be determined, and after the adjustment parameter item is determined, the element sum of the position parameter item and the adjustment parameter item is calculated to obtain an adjusted position parameter item, that is, a target position parameter item corresponding to the position parameter item. Based on this, after the target position parameter items corresponding to all the position parameter items are obtained, the position parameters formed by all the target position parameter items can be used as the target position parameters.

In one embodiment, after several circuit parameters are retrieved, the circuit parameters may be saved to form a circuit parameter set. After the expected photoelectric characteristic is obtained, a target circuit parameter can be selected in the circuit parameter set based on the expected photoelectric characteristic, and a circuit layout corresponding to the position parameter in the target circuit parameter is used as the circuit layout corresponding to the expected photoelectric characteristic, so that the obtaining speed of the circuit layout can be improved.

Based on this, after the circuit parameter set is acquired, as shown in fig. 9 and 10, the method may further include:

Specifically, each of the plurality of circuit parameters includes a position parameter and a photoelectric characteristic, where the position parameter corresponds to a circuit layout, and the photoelectric characteristic is a photoelectric characteristic corresponding to the circuit layout. It will be appreciated that the position parameter and the optoelectronic property correspond to the same circuit layout, the position parameter being parameterized for the circuit layout, and the optoelectronic property being determined by a circuit simulator or being determined based on the position parameter.

The target circuit parameter is included in a plurality of circuit parameters, and the target photoelectric characteristic of the plurality of circuit parameters has the highest matching degree with the expected photoelectric characteristic, wherein the matching degree is used for reflecting the similarity degree of the target photoelectric characteristic and the expected photoelectric characteristic, when the matching degree is higher, the similarity degree of the target photoelectric characteristic and the expected photoelectric characteristic is higher, and conversely, when the matching degree is lower, the similarity degree of the target photoelectric characteristic and the expected photoelectric characteristic is lower.

The matching degree may be a euclidean distance between the photoelectric characteristic and the desired photoelectric characteristic, or a weight coefficient may be configured for each photoelectric parameter in the photoelectric characteristic, and when determining the matching degree, the photoelectric parameter may be updated based on the weight coefficient of each photoelectric parameter (for example, a product of the photoelectric parameter and the weight coefficient is used as the photoelectric parameter, or the like), and the matching degree between the photoelectric characteristic and the desired photoelectric characteristic may be obtained based on the euclidean distance between the updated photoelectric characteristic and the desired photoelectric characteristic.

In an implementation manner of this embodiment, the selecting, based on a preset expected photoelectric characteristic, a target circuit parameter corresponding to the expected photoelectric characteristic from a plurality of pre-stored circuit parameters specifically includes:

a target circuit parameter is selected among the number of circuit parameters based on the desired optoelectronic characteristic and the set of weight coefficients.

Specifically, the weight coefficient set includes a plurality of weight coefficients, the plurality of weight coefficients correspond to a plurality of photoelectric parameters included in the photoelectric characteristics one to one, each weight coefficient is used for reflecting the importance degree of the corresponding photoelectric parameter, the higher the weight coefficient is, the higher the importance degree of the photoelectric parameter is, and conversely, the lower the weight coefficient is, the lower the importance degree of the photoelectric parameter is. The set of weighting factors may be preset and the sets of weighting factors for different desired optoelectronic characteristics may be different.

In an implementation manner of this embodiment, after the weight coefficient set is obtained, when the target photoelectric characteristic corresponding to the desired photoelectric characteristic is determined based on the weight coefficient set, a matching degree between the photoelectric characteristic in each of the plurality of circuit parameters and the desired photoelectric characteristic may be respectively calculated, and a circuit parameter corresponding to the photoelectric characteristic with the highest matching degree may be selected as the target circuit parameter.

In one implementation manner of this embodiment, the plurality of circuit parameters are stored in a KD tree form, and after the weight coefficient set is obtained, when the target photoelectric characteristic corresponding to the desired photoelectric characteristic is determined based on the weight coefficient set, the target circuit parameter may be determined by using KD tree search, so that the obtaining speed of the target circuit parameter may be increased. Correspondingly, the selecting a target circuit parameter from the plurality of circuit parameters based on the desired optoelectronic characteristic and the set of weight coefficients specifically includes:

and performing KD tree search on the circuit parameters based on the expected photoelectric characteristics to obtain target circuit parameters corresponding to the expected photoelectric characteristics, wherein the searching range of the KD tree search on the photoelectric characteristics of the nodes in the backtracking process is determined based on the photoelectric characteristics of the nodes, the expected photoelectric characteristics and the weight coefficient set.

Specifically, after the desired optoelectronic characteristics are obtained, several circuit parameters are searched in the form of KD tree search to obtain candidate circuit parameters. The KD tree searching process can compare the expected photoelectric characteristic with the splitting dimension value of the reference photoelectric characteristic in the circuit parameters of the splitting node, and the expected photoelectric characteristic is smaller than the reference photoelectric characteristic and enters the left sub-tree branch; and if the expected photoelectric characteristic is equal to or greater than the reference photoelectric characteristic, entering a right subtree branch, repeating the steps until reaching a leaf node, and taking the circuit parameter corresponding to the leaf node as a candidate circuit parameter. And after determining the candidate circuit parameters, searching leaf nodes in the same subspace as the candidate circuit parameters, wherein when searching leaf nodes in the same subspace as the candidate circuit parameters, the candidate circuit parameters are used as query circuit parameters, the photoelectric characteristics in the candidate circuit parameters are node photoelectric characteristics, and the search radius is determined based on the node photoelectric characteristics, the expected photoelectric characteristics and the weight coefficient set. For example, the process of searching for a radius may be: the method comprises the steps of firstly multiplying photoelectric parameters in expected photoelectric characteristics by corresponding weight coefficients to update each photoelectric parameter, then calculating Euclidean distances between the expected photoelectric characteristics and the photoelectric characteristics of nodes, and finally taking the calculated Euclidean distances as search radiuses.

Further, after leaf nodes which are located in the same subspace with the point to be queried are searched, the search path is traced back, whether data points with the distance from the expected photoelectric characteristic smaller than the search radius exist in other sub-node spaces of the nodes on the search path is judged, if the data points exist, the other sub-node spaces are required to be skipped to search, other sub-nodes are added into the search path, and whether data points with the distance from the expected photoelectric characteristic smaller than the search radius exist in other sub-node spaces of the nodes on the search path is continuously judged until the search path is empty, so that the target circuit parameters corresponding to the expected photoelectric characteristic are obtained.

Based on the foregoing adjusting method of the integrated circuit, the present embodiment provides an adjusting apparatus of the integrated circuit, as shown in fig. 11, including:

a first obtaining module 100, configured to obtain feature information corresponding to an integrated circuit, where the feature information includes a position parameter corresponding to a circuit layout of the integrated circuit and optoelectronic characteristic information corresponding to the integrated circuit;

a first determining module 200, configured to determine a target location parameter corresponding to the integrated circuit based on the feature information, and determine an adjusted integrated circuit based on the target location parameter.

In one implementation, the second determining module specifically includes:

the first acquisition unit is used for acquiring a reference position parameter corresponding to the position parameter, wherein the dimension of the reference position parameter is lower than that of the position parameter;

the first determining unit is used for determining an optimized position parameter corresponding to the reference position parameter based on the photoelectric characteristic and the reference position parameter, wherein the dimension of the optimized position parameter is equal to that of the reference position parameter;

In one implementation, the first determining unit specifically includes:

the first acquisition subunit is used for acquiring an objective function corresponding to the integrated circuit and determining a target value corresponding to the photoelectric characteristic based on the objective function;

and the optimization subunit is used for optimizing the reference position parameter by adopting a Bayesian optimizer based on the target value to obtain an optimized position parameter.

In one implementation, the optimization subunit is specifically configured to: inputting the optimized position parameters into a trained third network model, and outputting target position parameters corresponding to the position parameters through the third network model.

In one implementation, the detection network model includes a first network model and a second network model in cascade; the input item of the first network model is a first high-dimensional position parameter, and the output item of the first network model is a first low-dimensional position parameter; the input item of the third network model is a second low-dimensional position parameter, the output item is a second high-dimensional position parameter, the dimensionality of the first high-dimensional position parameter is equal to the dimensionality of the second high-dimensional position parameter, and the dimensionality of the first low-dimensional position parameter is equal to the dimensionality of the second low-dimensional position parameter.

In one implementation, the training process of the third network model specifically includes:

In one implementation, the adjusting means of the integrated circuit includes:

and the second acquisition module is used for acquiring the target photoelectric characteristic corresponding to the target position parameter and storing the circuit parameter formed by the target position parameter and the target photoelectric characteristic.

In one implementation, the adjusting means of the integrated circuit includes:

the second determining module is used for selecting a target circuit parameter corresponding to the expected photoelectric characteristic from a plurality of prestored circuit parameters based on the preset expected photoelectric characteristic;

and the third determining module is used for determining the integrated circuit corresponding to the expected photoelectric characteristic based on the target position parameter in the target circuit parameter.

In one implementation, the second determining module specifically includes:

a second obtaining unit, configured to obtain a weight coefficient set corresponding to the desired photoelectric characteristic, where the weight coefficient set includes weight coefficients corresponding to respective photoelectric parameters in the desired photoelectric characteristic;

and the selecting unit is used for selecting a target circuit parameter from the plurality of circuit parameters based on the expected photoelectric characteristic and the weight coefficient set.

In one implementation, the pre-stored circuit parameters are stored in a KD tree.

In one implementation, the selecting unit is specifically configured to: and performing KD tree search on the circuit parameters based on the expected photoelectric characteristics to obtain target circuit parameters corresponding to the expected photoelectric characteristics, wherein the searching range of the KD tree search on the photoelectric characteristics of the nodes in the backtracking process is determined based on the photoelectric characteristics of the nodes, the expected photoelectric characteristics and the weight coefficient set.

In one implementation, the integrated circuit is a TFT circuit.

Based on the adjustment method of the integrated circuit described above, the present embodiment provides a computer-readable storage medium storing one or more programs, which are executable by one or more processors to implement the steps in the adjustment method of the integrated circuit described above.

Based on the above adjustment method of the integrated circuit, the present application further provides a terminal device, as shown in fig. 12, which includes at least one processor (processor) 20; a display screen 21; and a memory (memory)22, and may further include a communication Interface (Communications Interface)23 and a bus 24. The processor 20, the display 21, the memory 22 and the communication interface 23 can communicate with each other through the bus 24. The display screen 21 is configured to display a user guidance interface preset in the initial setting mode. The communication interface 23 may transmit information. The processor 20 may call logic instructions in the memory 22 to perform the methods in the embodiments described above.

Furthermore, the logic instructions in the memory 22 may be implemented in software functional units and stored in a computer readable storage medium when sold or used as a stand-alone product.

The memory 22, which is a computer-readable storage medium, may be configured to store a software program, a computer-executable program, such as program instructions or modules corresponding to the methods in the embodiments of the present disclosure. The processor 20 executes the functional application and data processing, i.e. implements the method in the above-described embodiments, by executing the software program, instructions or modules stored in the memory 22.

The memory 22 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the terminal device, and the like. Further, the memory 22 may include a high speed random access memory and may also include a non-volatile memory. For example, a variety of media that can store program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk, may also be transient storage media.

In addition, the specific processes loaded and executed by the storage medium and the instruction processors in the terminal device are described in detail in the method, and are not stated herein.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.

Claims

1. A method of tuning an integrated circuit, the method comprising:

2. The method for obtaining optoelectronic characteristics according to claim 1, wherein the determining a target position parameter corresponding to the integrated circuit based on the characteristic information specifically includes:

3. The method for obtaining an optoelectronic characteristic according to claim 2, wherein the determining an optimized position parameter corresponding to the reference position parameter based on the optoelectronic characteristic and the reference position parameter specifically includes:

4. The method for obtaining optoelectronic characteristics according to claim 2, wherein the determining, based on the optimized position parameter, a target position parameter corresponding to the position parameter specifically includes:

5. The method according to claim 1, wherein the detection network model includes a first network model and a second network model which are cascaded; the input item of the first network model is a first high-dimensional position parameter, and the output item of the first network model is a first low-dimensional position parameter; and the input item of the third network model is a second low-dimensional position parameter, the output item is a second high-dimensional position parameter, the dimensionality of the first high-dimensional position parameter is equal to the dimensionality of the second high-dimensional position parameter, and the dimensionality of the first low-dimensional position parameter is equal to the dimensionality of the second low-dimensional position parameter.

6. The method according to claim 5, wherein the training process of the third network model specifically includes:

7. The method for obtaining optoelectronic characteristics according to any one of claims 1 to 6, wherein after determining the target position parameter corresponding to the integrated circuit based on the characteristic information and determining the adjusted integrated circuit based on the target position parameter, the method further comprises:

8. The method for acquiring optoelectronic characteristics according to claim 7, wherein after acquiring the target optoelectronic characteristics corresponding to the target position parameters and saving the circuit parameters formed by the target position parameters and the target optoelectronic characteristics, the method further comprises:

9. The method for obtaining optoelectronic characteristics according to claim 8, wherein selecting the target circuit parameter corresponding to the desired optoelectronic characteristic from a plurality of pre-stored circuit parameters based on a preset desired optoelectronic characteristic specifically comprises:

10. The method of claim 9, wherein the pre-stored circuit parameters are stored in a KD tree.

11. The method of claim 10, wherein the selecting a target circuit parameter from the plurality of circuit parameters based on the desired optoelectronic characteristic and the set of weight coefficients comprises:

12. Method for parameterizing integrated circuits according to claims 1-6, wherein said integrated circuits are TFT circuits.

13. An adjustment device for an integrated circuit, the adjustment device comprising:

14. A computer-readable storage medium storing one or more programs, the one or more programs being executable by one or more processors to perform the steps in the method of tuning an integrated circuit of any one of claims 1-12.

15. A terminal device, comprising: a processor, a memory, and a communication bus; the memory has stored thereon a computer readable program executable by the processor;

the processor, when executing the computer readable program, implements the steps in the tuning method of the integrated circuit of any of claims 1-12.