CN114519023B

CN114519023B - Method for realizing multi-port Ram

Info

Publication number: CN114519023B
Application number: CN202210153560.5A
Authority: CN
Inventors: 郑利
Original assignee: Xinhe Semiconductor Technology Wuxi Co Ltd
Current assignee: Xinhe Semiconductor Technology Wuxi Co Ltd
Priority date: 2022-02-18
Filing date: 2022-02-18
Publication date: 2024-04-19
Anticipated expiration: 2042-02-18
Also published as: CN114519023A

Abstract

The invention relates to the technical field of Ram, in particular to a method for realizing multi-port Ram, which comprises the following steps: the simple port 1w1r Ram or the Ram which is commonly applied by combining with the simple dual port 2w r Ram is used for realizing the multi-port Ram, the mode has no special requirement on frequency, the realization mode is simpler and more efficient, and the demand on Ram chip area is smaller.

Description

Method for realizing multi-port Ram

Technical Field

The invention relates to the technical field of Ram, in particular to a method for realizing multi-port Ram.

Background

QoS is an acronym Quality of Service (quality of service) whose purpose is to provide end-to-end quality of service guarantees for various services for their different needs. QoS technology is increasingly used in today's internet, and its role is becoming more important. Without Qos technology, the quality of service of the service cannot be guaranteed. Ram is an important device used in QoS, and with rapid development of network technology, bandwidth is increased, and the requirement for multiple ports is more and more urgent. The current multi-port implementations are complex or rough, by accumulating capacity or limiting frequency, and with the increasing demand for Ram depth, it is also a not insignificant challenge for chip area and power consumption.

The current way of implementing multiple ports is as follows:

1. the read port is enlarged by a copying mode, but the write port cannot be increased;

2. ports are added by frequency doubling, but the limitation on frequency increases;

3. The method is characterized in that a storage data area bank is segmented, the method is realized by segmenting a Ram into n banks, but each bank is fixedly distributed to a group of fixed wrs (r=read, w=write, read-write) for use, and the different wrs cannot share the Ram with each other, so that the method is not really multi-port;

4. One implementation, called LVT (live value table), is shown in fig. 2, where n 0-n-1 are identical Ram, the number depends on the number of writes, and the function of LVT is to record the latest location where the data of a current address exists. LVT is mwnr (m write ports, n read ports, m and n are numbers which are arbitrarily more than 1), multiple ports Ram are realized by using a frequency multiplication mode, the realization is complex, the Ram resource consumption is large, and the requirement on frequency is also met. There is therefore an urgent need for a simpler, more efficient and smaller area implementation of multiport Ram.

In order to overcome the defects, the invention solves the following problems:

The implementation mode of the multiport Ram is simple and efficient;

the multiport Ram has less resource consumption and smaller area;

The frequency of the multiport Ram is not particularly required when in use.

In order to solve the above problems, the present invention proposes to use a simple port (1 w1 r) or combine with a simple dual port (2 wr) to implement a Ram of 2w1r, which is more common in application, and this way has no special requirement on frequency, and is consistent with the implemented Ram.

Disclosure of Invention

In order to solve the problems in the prior art, the invention provides an implementation mode of multi-port Ram.

In order to achieve the purpose, the invention adopts the following technology to achieve multi-port Ram by using simple ports (1 w1 r) or combining simple dual ports (2 wr) which are commonly applied Ram, and the mode has no special requirement on frequency, is simple and efficient to achieve, has less resource consumption and smaller area.

In the embodiment of the invention, a method for realizing multi-port Ram is provided, which comprises the following steps:

S1, defining a functional block of the multi-port Ram, wherein the functional block comprises a storage data area bank, a buffer storage data area buffer and a flag_ram of a marked data area;

S2, performing logic judgment processing on writing, including independent writing and multiple writing processing, judging whether to write a bank or a buffer according to the flag_ram and the bank to be written, and judging whether to update the flag_ram or to move buffer data;

s3, carrying out logic judgment processing on the read, and simultaneously removing the bank, buffer and flag_ram of the corresponding address according to the operation address of the read bank, so as to judge whether the read data come from the bank or the buffer of the corresponding address;

S4, judging the bank, the buffer and the flag_ram which form the multi-port Ram, and if the bank, the buffer and the flag_ram are formed by the multi-port Ram, further processing the multi-port Ram in a mode of copying or splicing the simple ports, so that the multi-port Ram in a real sense is realized.

Further, the data stored in the flag_ram identifies a bank identifier corresponding to the data stored in the buffer and whether the stored data is valid.

Further, the bank, buffer and flag_ram used by the multi-port Ram are composed of a simple port (1 w1 r) and a dual port (2 wr) Ram.

Further, the bandwidth of the bank and the buffer formed by the multiport Ram is equal to the implemented Ram, and the bandwidth of the flag_ram data is equal to the number of banks; the depths of bank, buffer and flag_ram are one-N times the achieved Ram.

Further, the frequencies of the bank, buffer and flag_ram of the port Ram need to be consistent with the multi-port Ram.

Further, a balance is made in capacity and area according to the size of the underlying Ram core and the implementation logic of the spliced Ram.

Further, other multiport rams may be implemented by multiple simple ports and simple dual port combinations.

The invention has the beneficial effects that aiming at the problems existing in the existing communication system, the invention provides the method for realizing the multi-port Ram, which uses the Ram with a common application of a simple port (1 w1 r) or a simple dual port (2 wr) to realize the multi-port Ram, and the method has no special requirement on frequency, is simple and efficient to realize, has less resource consumption and smaller area.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. In the drawings:

FIG. 1 is a schematic diagram of a process flow of an implementation method of the present invention;

FIG. 2 is a schematic diagram of an LVT implementation;

FIG. 3 is a schematic diagram of an implementation of the embodiment of the present invention;

FIG. 4 is a schematic diagram of a first implementation of the embodiment of the present invention;

fig. 5 is a schematic diagram of a second implementation of the embodiment of the present invention.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the embodiments of the present application will be described in further detail with reference to the accompanying drawings. The following examples are only for more clearly illustrating the system method and technical scheme of the present application, and are not intended to limit the scope of the present application.

According to the embodiment of the invention, the implementation method of the multi-port Ram is provided, the multi-port Ram is realized by using a simple port (1 w1 r) or combining a simple dual-port (2 wr) Ram which is commonly applied, the implementation method has no special requirement on frequency, the implementation is simple and efficient, the resource consumption is low, and the area is smaller.

The principles and spirit of the present invention are explained in detail below with reference to several representative embodiments thereof.

Fig. 1 is a schematic process flow diagram of a method for implementing multi-port Ram. As shown in fig. 1, the method comprises the steps of:

Further, the data stored in the flag_ram identifies a bank identifier corresponding to the data stored in the buffer and whether the data is valid or not.

In the preferred embodiment, the number, depth, type and data width of banks and buffers are defined according to the number, depth and data width of the implemented multiport Ram read/write ports.

In a preferred embodiment, the data bit width and depth of the flag_ram are defined according to the bank number and depth.

in a preferred embodiment, it is determined which bank or buffer the data is written in and whether the flag_ram needs to be updated according to the value of the write address while reading the flag_ram.

In the preferred embodiment, when there is only one write, determining whether the address data is stored in the buffer according to the value obtained by the flag_ram, if the address has no data stored in the buffer, the latest data needs to be updated in the bank, and the flag_ram does not need to be updated; if the address has data stored in buffer, the latest data needs to be updated in the bank ram, and the flag valid bit in the flag ram needs to be cleared.

In the preferred embodiment, if two writes belong to different banks and are not stored in the buffer at the same time, two independent write operations are performed, and the operations are the same as independent write operations.

In a preferred embodiment, if two writes belong to different banks and are stored in the buffer at the same time, it is specified to write one write bank, one write buffer, and write the bank while clearing the valid bit of the flag_ram.

In a preferred embodiment, if two writes belong to the same bank, one writes to the bank and one writes to the buffer, and at this time, there may be data of another bank in the buffer, then the moving operation is required and the flag bit of the flag_ram is updated.

In the preferred embodiment, if two writes belong to the same bank, one of the data is stored in the bank and the other is stored in the buffer, the corresponding bank and buffer are directly written respectively, and at this time, the flag_ram does not need to be updated.

In a preferred embodiment, if two writes belong to the same bank and data are stored in the buf fer, one writes the bank and one writes the buffer, and the data written in the bank need to update the valid bit of the address corresponding to the flag_ram to 0 at the same time.

In the implementation, a balance is made in capacity and area according to the size of the bottom Ram core and the realization logic of the spliced Ram.

In a preferred embodiment, other multiport rams may be implemented by multiple simple ports as well as simple dual port combinations.

It should be noted that although the operations of the method of the present invention are described in a particular order in the above embodiments and the accompanying drawings, this does not require or imply that the operations must be performed in the particular order or that all of the illustrated operations be performed in order to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step to perform, and/or one step decomposed into multiple steps to perform.

In order to more clearly explain the implementation of a multiport Ram, a specific embodiment is described below, but it should be noted that this embodiment is only for better illustrating the present invention and is not meant to limit the present invention unduly.

Embodiment one:

in this embodiment, a 2w1r Ram is taken as an example to describe a method for implementing multi-port Ram, and specific implementation steps are as follows:

step 1: defining a 2w1r multiport Ram:

2w1r, as shown in fig. 3, ram of a block 2w1r is composed of three parts: bank, buffer and flag_ram, wherein bank is one-N of depth 2w1r (n=2 is taken as an example in the figure, i.e. N is equal to the number of writes), the data bit width is equal to the ram implemented, and the ram type is 1w1r; the buffer is one-N (in the figure, n=2 is taken as an example) of depth of 2w1r, the data bit width is equal to the implemented Ram, and the Ram type is 1w2r, and the buffer is used for caching data when write collision occurs; the data bit width of the flag_ram is equal to the number of banks, (2 bits in this embodiment), the Ram type is 1w3r, wherein [0] (i.e. bit 0) in the flag_ram is marked by the serial number of the bank and is used for indicating which bank data is stored in the buffer (the value 0 represents bank0 and the value 1 represents bank 1); the flag_ram [1] identifies whether the buffer data is valid, and the depth of the flag_ram is the same as the depths of the bank and the buffer.

Step 2: write logic determination processing

The implementation flow is described: when writing occurs, the flag_ram needs to be read first according to the write address, and the last position is confirmed, so as to confirm whether the flag_ram needs to be updated. The description follows:

(1) Only one write occurs:

Taking the writing of bank0 as an example, if the result of the flag_ram is 2' b11 or 2' b00 (in this example, the flag_ram bit width is 2bit,2' b11, where 2 indicates that bit0 and bit1 are both 1) according to the value obtained by the flag_ram, it is indicated that this address is not stored in the buffer, and only the latest data need to be updated in the bank, and the flag_ram need not to be updated; if the result of the flag_ram is 2' b10, the latest data needs to be updated in the bank ram, and the flag valid bit in the flag_ram needs to be cleared.

(2) When there are two writes to take place,

If two writes belong to bank0 and bank1 respectively, and the respective read flag_ram shows that the two writes are not stored in the buffer at the same time, the two independent write operations are the same as the write operation (1).

If two writes belong to bank0 and bank1 respectively, and the respective read flag_ram is displayed and stored in the buffer at the same time, w0 is written into bank0, w1 is still written into the buffer, and at the moment, the valid bit of w0 updated flag_ram is 0;

If two writes are the same bank at the same time, taking bank0 as an example, three cases are classified according to the result of the flag_ram

A is as stored in bank0: the operation in this case is that W0 is stored in bank0, W1 is written into buffer, at this time, the buffer may have the data of bank1 stored therein, so that the buffer needs to be moved, while the flag is read, the buffer is read by the address of W1, the data of the buffer is moved back to bank1, and the result of updating the flag is 2' b10;

b, one is stored in bank0, one is stored in buffer: the operation in this case is to write the corresponding bank0, buffer, and flag_ram directly without updating

C, storing in buffer: the operation in this case is that w0 needs to be written into bank, w1 is still written into buffer, and at this time, the valid bit of the address corresponding to w0 update flag_ram is 0.

Step 3: read logic operation determination process

When the reading occurs, taking bank0 as an example, at this time, the bank0, buffer and flag_ram need to be read at the same time, and the final result of the reading is obtained according to the result of the flag_ram, if the result of the flag_ram is 2' b11 or 2' b00, the result is the value of bank0, and if the result is 2' b10, the result is the value of buffer.

Fig. 3 shows a scenario where rd is bank0, wr0 and wr1 are both bank0, where r_rd is read triggered by rd, a final result is obtained according to an operation of reading, r_w0 and r_w1 are respectively read triggered by w0 and w1, and two writing according to a writing operation are simultaneously written into a corresponding Ram in a scenario of the same bank.

Step 4: the multi-port Ram of the bank, buffer and flag_ram which form the multi-port Ram is further processed by replication or splicing, so that the real multi-port Ram is realized.

Where a block 1w2r Ram is used in fig. 3 (2 w1 r) Ram, still a multiport Ram, this block 1w2r Ram can be implemented in two ways:

The first is a copy mode, as shown in fig. 4, the principle of implementation is that two 1w1r rams are used, two copies of write data are respectively written into the two rams, and two rds respectively read the respective rams, so that the implementation is simple, but the capacity is doubled.

The second is a splicing manner, as shown in fig. 5, and the specific implementation manner is to split Ram into n identical banks, where the type is 2wr, such as banks 0-3 in fig. 5, and another block of Ram with the same size is needed to store XOR (where XOR represents the meaning of exclusive or, but not two data are exclusive or, and the following example is illustrated in fig. 5, where wr refers to the value written in bank1, exclusive or is the result of other banks and the data written in bank1, and the bit width of XOR is the same as the bit width of the original data, so that the resource needed to implement 1w2r in this manner is 1.25 times, compared with the first resource, but the implementation is complex.

The specific implementation is illustrated as follows:

when writing occurs, it is necessary to determine which bank the writing is based on the splitting principle (in this embodiment, it is assumed that the writing is the writing of bank 1), and meanwhile, according to the writing address, the value of other banks is read, and the read result and the writing data are subjected to exclusive-or operation to write into the XOR bank, as shown in fig. 5, where wr is the writing, r_wr is the writing triggered by wr, the writing is to write the data into bank1, and the reading of other banks is to write the result into the XOR Ram for exclusive-or calculation, with different purposes, but simultaneous operation; the result of the write XOR is

Dout represents the value read from the corresponding bank while wdata is written to the address corresponding to bank 1. When the reading occurs simultaneously and the same block of bank is judged according to the principle of splitting (the reading of the bank2 is assumed), the rd0 reads the bank2, the other rd1 needs to read the values of the banks and the XOR bank except the bank2, the final result can be obtained by exclusive-or the read results, the realized principle is exclusive-or calculation, and the calculation formula is/>The expression is

Wherein A and B respectively represent different values,/>Is the inverse of A and B. The reason why the final result can be obtained by exclusive-or calculation for rd1 is that the last time the result of the write XOR occurred for the rd1 address is according to the formula of the write operation

The result of this rd1 calculation is

Wherein we can put/>As B in the above exclusive or formula, wdata _addr_rd1 is a, and the latest value written to the address corresponding to wdata _addr_rd1, that is, rd1, is obtained according to the formula. It should be noted here that a 2wr type of Ram, as used above for bank_ram (bank 0 and bank1, collectively referred to as bank_ram), is likely to occur in the case of 2r for the same block of Ram

The Ram of 1w3r in fig. 3 may be implemented in a duplication manner if implemented in an easy manner, and may be implemented in an XOR manner as 1w2r to save resources, which is not described herein.

Summarizing, from the above description we can see that a block of 2w1r Ram, we can all use the common 1w1r Ram or use both types of 1w1r and 2wr Ram, implemented by logic concatenation.

In the embodiment of the invention, it is further proposed that the more the bank is, the smaller the buffer_ram (i.e. the Ram constituting the buffer) is, the closer the buffer_ram is to the original Ram capacity, of course, the more the bank is impossible to infinitely increase, and the area during the layout and wiring is increased, so that in actual use, a balance needs to be made between capacity and area, and a proper cutting size is selected according to the size of the underlying Ram core and the implementation logic of the spliced Ram, and can be determined by the back-end comprehensive result. For example, in implementing a block Ram of 16k×10, but the bottom Ram is only 4k×10 at maximum, it is cut into 4k×10, if the bottom Ram is only 2k×10 at maximum, it is cut into 82 k×10, because the two kinds of cutting numbers are different, the selection logic is different, the first is 4-1, the second is 8-1, the more the number of cutting numbers, the more the number of selection logic stages.

In specific implementation, other multiport Ram can be implemented by multiple simple ports and simple dual port combinations.

The invention has the beneficial effects that the invention has the advantages of simpler realization, can be spliced by using a single port or a simple dual-port Ram, and has the same frequency as the module frequency.

The applicant has described in detail the embodiments of the present invention with reference to the accompanying drawings of the specification, the above embodiments are only preferred embodiments of the present invention, and the detailed description is only for helping the reader to better understand the spirit of the present invention, but not limiting the scope of the present invention, but any improvements or modifications based on the spirit of the present invention should fall within the scope of the present invention.

Claims

1. A method for implementing a multiport Ram, the method comprising the steps of:

s4, judging the bank, the buffer and the flag_ram which form the multi-port Ram, and if the bank, the buffer and the flag_ram are formed by the multi-port Ram, further processing the multi-port Ram in a mode of copying or splicing the simple ports so as to realize the multi-port Ram;

The capacity and the area are balanced according to the size of the bottom-layer Ram core and the implementation logic of the spliced Ram, the proper cutting size is selected according to the size of the bottom-layer Ram core and the implementation logic of the spliced Ram, and the cutting size is determined through the rear-end comprehensive result; spliced Ram capacity = cut number x capacity of bottom Ram; the frequencies of the bank, buffer and flag_ram of the port Ram need to be consistent with the multi-port Ram.

2. The method for implementing multiport Ram according to claim 1, wherein: the bank, buffer and flag_ram used by the multi-port Ram are composed of a simple port 1w1r Ram and a simple dual port 2w r Ram.

3. The method for implementing multiport Ram according to claim 1, wherein: and the data stored in the flag_ram identifies the bank identifier corresponding to the data stored in the buffer and whether the stored data is valid or not.

4. The method for implementing multiport Ram according to claim 1, wherein: the bandwidth of the bank and buffer data formed by the multiport Ram is equal to the implemented Ram, and the bandwidth of the flag_ram data is equal to the number of banks; the depths of bank, buffer and flag_ram are one-N times the achieved Ram.

5. The method for implementing multiport Ram according to claim 1, wherein: multiport Ram may be implemented by a plurality of simple ports and a simple dual port combination.