CN114519012A - Artificial intelligence chip compatible with different data access modes and data processing method - Google Patents
Artificial intelligence chip compatible with different data access modes and data processing method Download PDFInfo
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Abstract
The embodiment of the invention discloses an artificial intelligence chip compatible with different data access modes and a data processing method. The artificial intelligence chip compatible with different data access modes comprises: the special address generating module is used for generating a first address according to a preset algorithm; the selection module is used for selecting a second address for receiving the first address and/or external input; the data caching module is used for caching the data to be processed and transmitting the data to be processed according to the first address and/or the second address; and the operation module is used for receiving the data to be processed and finishing the operation of the data to be processed. In the embodiment of the invention, the artificial intelligence chip can use the first address generated by the artificial intelligence chip and can also select the second address input externally, the compatibility is stronger, the algorithm alternation of a special processor can be adapted, the new algorithm requirement can be met through the second address input externally, and the special requirement of the non-common complex algorithm on the address can be considered at the same time.
Description
Technical Field
The invention relates to the technical field of artificial intelligence, in particular to an artificial intelligence chip compatible with different data access modes and a data processing method.
Background
With the development of moore's law, hardware has supported very wide SIMD components, deep memory hierarchies, branch prediction, very deep-hierarchy pipelines, out-of-order execution, multithreading, and the like. However, at present, the processor speech encounters a power consumption bottleneck, the energy efficiency ratio of the processor architecture must be improved, and the energy efficiency ratio of the traditional general architecture design method reaches the limit. To improve the energy efficiency ratio, a domain specific processor architecture (DSA) optimized for the application domain is proposed. DSA can be used for framework optimization of a specific type of application, and therefore better energy efficiency ratio is achieved. Compared with general processors, DSA needs to consider special requirements of a special field when designing, and also needs a designer to have deep understanding of the field. Examples of DSA include neural network processors designed for machine learning, GPUs designed for images and virtual reality.
Conventional domain-specific processors often require a dedicated address generator for generating an access address when performing data access. However, algorithms in some fields have fast iteration speed, and a customized address generator can only provide a fixed data access mode, that is, an address of a specified source is used, and cannot meet the requirements of new algorithms. Some fields have some complex algorithms which are not commonly used, and in order to support the complex algorithms which are not commonly used, the complexity of an address generator is greatly increased, and inconvenience is brought to data access.
Disclosure of Invention
In view of this, the present invention provides an artificial intelligence chip and a data processing method compatible with different data access modes, which can be compatible with a read/write address generated by an external chip and a read/write address generated by the artificial intelligence chip itself, and have strong compatibility with different data access modes.
In a first aspect, the present invention provides an artificial intelligence chip compatible with different data access modes, the chip comprising:
the special address generating module is used for generating a first address according to a preset algorithm;
the selection module is used for selecting and receiving the first address and/or a second address of an external input;
the data caching module is used for caching the data to be processed and transmitting the data to be processed according to the first address and/or the second address;
and the operation module is used for receiving the data to be processed and completing the operation of the data to be processed.
Optionally, in some embodiments, the method further includes:
and the on-chip address caching module is arranged between the selection module and the data caching module and is used for caching the first address and/or the second address.
Optionally, in some embodiments, the method further includes:
and the off-chip address buffer module is connected with the selection module and used for receiving and storing a second address generated by an external chip.
Optionally, in some embodiments:
the operation module is further configured to return an operation result of the to-be-processed data to the data cache module, so that the data cache module completes saving back of the operation result according to the first address and/or the second address.
Optionally, in some embodiments, the on-chip address caching module is further configured to:
and judging whether the residual space of the address cache is less than or equal to a preset space, if so, sending a back pressure signal to the on-chip address cache module or the special address generation module to suspend receiving the first address and/or the second address.
In a second aspect, an embodiment of the present invention further provides a data processing method, which can be implemented based on an artificial intelligence chip compatible with different data access modes provided in any embodiment of the present invention, where the method includes:
determining a data read-write address source according to an operation algorithm to be operated;
acquiring a specified data read-write address based on the data read-write address source;
sending the data to be processed to the operation module according to the data read-write address to complete operation and generate an operation result;
and storing the operation result back according to the data read-write address.
Optionally, in some embodiments, the source of the data read/write address includes the dedicated address generating module and/or the off-chip address caching module, the data read/write address includes the first address and/or the second address, and before obtaining the specified data read/write address based on the source of the data read/write address, the method further includes:
judging whether the source of the data read-write address is a special address generation module;
if so, configuring the special address generation module according to the operation algorithm so that the special address generation module generates the first address;
if not, generating the second address by an external chip according to an address generating program corresponding to the operation algorithm, and storing the second address into the off-chip address cache module.
Optionally, in some embodiments, the determining, according to the operation algorithm to be executed, a source of the data read/write address includes:
and selecting, by the selection module, to acquire the first address from the private address generation module and/or to acquire the second address from the off-chip address cache module.
Optionally, in some embodiments, after obtaining the specified data read-write address based on the data read-write address source, the method further includes:
And judging whether the residual space of the address cache is smaller than a preset space, if so, sending a back pressure signal to the on-chip address cache module or the special address generation module to suspend receiving the first address and/or the second address.
Optionally, in some embodiments, the data read/write address includes a read address and a copy-back address.
The artificial intelligence chip compatible with different data access modes provided by the embodiment of the invention can generate a first address according to a preset algorithm through a self special address generating module, then a selecting module selects to receive the first address generated by the special address generating module or to receive a second address from external input, a data caching module realizes to transmit data to be processed to a designated address according to the first address or the second address selected by the selecting module while caching the data to be processed, and then an operation module receives the data to be processed to complete operation, the chip can use the first address generated by the chip and can also select the second address input from the outside, has stronger compatibility, can adapt to the algorithm alternation of a special processor, the requirement of a new algorithm can be met through the second address input externally, and the special requirement of an unusual complex algorithm on the address can be considered.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only part of the embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a schematic diagram of an artificial intelligence chip compatible with different data access modes according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of another artificial intelligence chip structure compatible with different data access modes according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of another artificial intelligence chip compatible with different data access modes according to an embodiment of the present invention;
fig. 4 is a flowchart of a data processing method according to a second embodiment of the present invention;
fig. 5 is a flowchart of another data processing method according to a second embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Before discussing exemplary embodiments in greater detail, it should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart may describe the steps as a sequential process, many of the steps can be performed in parallel, concurrently, or simultaneously. In addition, the order of the steps may be rearranged. A process may be terminated when its operations are completed, but may have additional steps not included in the figure. A process may correspond to a method, a function, a procedure, a subroutine, a sub computer program, or the like.
Furthermore, the terms "first," "second," and the like may be used herein to describe various orientations, actions, steps, elements, or the like, but the orientations, actions, steps, or elements are not limited by these terms. These terms are only used to distinguish one direction, action, step or element from another direction, action, step or element. For example, a first valid signal may be referred to as a second valid signal, and similarly, a second valid signal may be referred to as a first valid signal, without departing from the scope of the present application. Both the first valid signal and the second valid signal are valid signals, but they are not the same valid signal. The terms "first", "second", etc. are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
Example one
Fig. 1 is a schematic structural diagram of an artificial intelligence chip compatible with different data access modes according to an embodiment of the present invention. As shown in fig. 1, an artificial intelligence chip 10 compatible with different data access modes according to an embodiment of the present invention includes a private address generating module 11, a selecting module 12, a data caching module 13, and an arithmetic module 14. The artificial intelligence chip compatible with different data access modes provided by this embodiment can be applied to various AI systems to complete data processing tasks of complex post-post processing operators in an AI algorithm, for example, performing post-post computation processing on video and image stream-related data, specifically, in this chip:
the special address generating module 11 is configured to generate a first address according to a preset algorithm.
In this embodiment, the artificial intelligence chip compatible with different data access modes is essentially a domain-specific processor, which can perform professional operation processing on data to be processed to obtain expected operation results, and in the process of performing data operation, which requires the reading, operation and storage of specified data by address, and due to the specificity of domain-specific processors, which usually generates fetch addresses by itself to implement the above functions, the special address generation module 11 in this embodiment is a module for generating fetch addresses in the domain-specific processor, the system is provided with a preset algorithm specially set for special processors of different fields, can generate required access addresses for field-specific algorithms, for the convenience of distinguishing from the externally input address hereinafter, the address generated by the private address generating module 11 is referred to as a first address herein.
A selection module 12, configured to select to receive the first address and/or a second address of an external input.
The selection module 12 is connected to the private address generation module 11 and also connected to an external input, and is capable of accepting a first address generated by the private address generation module 11 and a second address from the external input and selecting which address is specifically used as an address for an operation process.
And the data caching module 13 is configured to cache data to be processed and transmit the data to be processed according to the first address and/or the second address.
The data caching module 13 is connected to the selection module 12 and the external input, and is capable of receiving and caching to-be-processed data from the external input and performing data reading and writing according to the first address or the second address received by the selection module 12: and transmitting the data to be processed to a specified address or saving the data to the specified address.
And the operation module 14 is configured to receive the data to be processed and complete operation on the data to be processed.
The operation module 14 is connected to the data caching module 13, and is mainly used for performing a special operation on data to be processed. In this embodiment, in the data operation process, the operation module 14 needs to use the first address or the second address to read the specified data from the data cache module 13 to complete the corresponding operation.
In this embodiment, when the artificial intelligence chip 10 is in normal operation, the operation module 14 stores the data to be processed, which is needed for operation, in the data cache module 13, the data cache module 13 needs to use the first address or the second address to transmit the data to be processed, and the specific use of the first address or the second address is selected by the selection module according to the specific operation algorithm of the operation module 14, when the first address generated by the special address generation module 11 can be used, the first address is adopted, and when the first address generated by the special address generation module 11 is not suitable due to the update of the operation algorithm, the second address of the external input is obtained.
The embodiment provides an artificial intelligence chip compatible with different data access modes, which can generate a first address according to a preset algorithm through a self special address generating module, then a selecting module selects to receive the first address generated by the special address generating module or a second address from external input, a data caching module realizes to transmit data to be processed to a designated address according to the first address or the second address selected by the selecting module while caching the data to be processed, and then an operation module receives the data to be processed to complete operation, the chip can use the first address generated by the chip and select the second address input from the outside, has stronger compatibility, can adapt to the algorithm alternation of a special processor, the new algorithm requirement can be met through the second address input externally, and meanwhile the special requirement of the non-common complex algorithm on the address can be considered.
More specifically, in some embodiments, an artificial intelligence chip compatible with different data access modes is provided as shown in fig. 2, further comprising:
an on-chip address caching module 15, disposed between the selection module 12 and the data caching module 13, and configured to cache the first address and/or the second address.
The on-chip address cache module 15 is configured to store the received first address or second address, so as to avoid a computation resource wasted by waiting for address generation in the data operation process, and the on-chip address cache module 15 can store the generated first address or second address in the on-chip address cache module 15, so that the data cache module 13 can use the first address or second address at any time in the operation process of the operation module 14.
More specifically, in some embodiments, as shown in fig. 3, an off-chip address buffer module 16 is further provided, connected to the selection module 12, for receiving and storing a second address generated by an external chip.
The off-chip address cache module 16 acts similarly to the on-chip address cache module 15, but the off-chip address cache module 16 is only used for caching the second address generated by the external chip, because the external chip can generate the data read address required by any algorithm, but the address generation speed is slow, and the generated address needs to be transmitted to the on-chip, so that the bandwidth requirement of the whole system is increased, and the transmission also needs a certain time, so that the performance of the whole system is reduced. Therefore, the off-chip address cache module 16 can store the second address calculated in advance in some operations and directly take out the second address during the operations, so that the time consumption of address calculation is reduced, and the efficiency is improved. It should be understood that fig. 3 illustrates a case where the off-chip address caching module 16 is disposed on the artificial intelligence chip 10, in which case updating of the compatibility of the artificial intelligence chip 10 is actually achieved, on which addresses have been stored, and that in some alternative embodiments, the off-chip address caching module 16 can also be disposed outside the artificial intelligence chip 10, for example, at an external device connected to the artificial intelligence chip 10 for plug-and-play use of the artificial intelligence chip 10.
Optionally, in some embodiments, the operation module 14 is further configured to return an operation result of the to-be-processed data to the data caching module 13, so that the data caching module 13 completes saving back the operation result according to the first address and/or the second address.
The first address and the second address play a role not only in the transmission of the data to be processed to the operation module 14, but also in the restore of the budget result after the operation is completed: the first address and the second address both include a read address and a restore address, the read address is used in the process of transmitting the data to be processed, and after the operation result is returned to the data cache module 13, the data cache module 13 takes out the restore address and stores the operation result to a specific position according to the restore address.
Optionally, in some embodiments, the on-chip address caching module 15 is further configured to:
and judging whether the address cache residual space is less than or equal to a preset space, if so, sending a back pressure signal to the off-chip address cache module 16 or the special address generation module 11 to suspend receiving the first address and/or the second address.
When the on-chip address cache module 15 does not have enough cache space, the reception of the address needs to be suspended, the on-chip address cache module 16 or the special address generation module 11 is notified by the backpressure signal to stop sending the address, after the address (which can be the first address and can also be the second address) in the on-chip address cache module 15 is taken out and the address cache residual space is larger than the preset space, the off-chip address cache module 16 or the special address generation module 11 sends the backpressure closing signal, and at this time, the off-chip address cache module 16 continues to send the second address to the on-chip address cache module 15 or the special address generation module 11 continues to send the first address to the on-chip address cache module 15.
Example two
Fig. 4 is a data processing method applicable to a scenario where a domain-specific processor is used to perform data processing according to a second embodiment of the present invention, and the method can be implemented based on an artificial intelligence chip compatible with different data access modes according to any embodiment of the present invention. Specifically, as shown in fig. 4, the method includes:
s210, determining a data read-write address source according to an operation algorithm to be operated.
The to-be-operated operation algorithm is an algorithm for processing the to-be-processed data by the operation module, and the data read-write address source is mainly used for determining whether the access address is generated by an artificial intelligent chip compatible with different data access modes or an external chip.
S220, acquiring the appointed data read-write address based on the data read-write address source.
The data read-write address comprises a first address generated by the artificial intelligence chip and/or a second address generated by the external chip.
And S230, sending the data to be processed to the operation module according to the data read-write address to complete operation and generate an operation result.
The data caching module sends the cached data to be processed to the operation module according to the data read-write address, and the operation result is the result of the operation module processing the data to be processed according to the operation algorithm to be operated.
And S240, storing the operation result back according to the data read-write address.
After the operation result is finished, the operation result is sent back to the data cache module, and the data cache module stores the operation result to a specified position according to the data read-write address: the data read-write address comprises a read address and a restore address, the read address is used for realizing the transmission of the data to be processed to the operation module, and the data to be processed is used for realizing the storage of the operation result to the appointed position.
Optionally, in some embodiments, the data read/write address source includes the dedicated address generating module 11 and/or the off-chip address caching module 16, the data read/write address includes the first address and/or the second address, and before the specified data read/write address is obtained based on the data read/write address source, that is, before step S220, as shown in fig. 5, step S250-270 are further included:
and S250, judging whether the data read-write address source is a special address generating module.
And S260, if so, configuring the special address generation module according to the operation algorithm so that the special address generation module generates the first address.
And S270, if the address generation program corresponding to the operation algorithm is not used, generating the second address by an external chip, and storing the second address into the off-chip address cache module.
The address generating program is a specific program written according to the requirement of the operation algorithm, and the external chip can run the address generating program to generate a read-write address required by the operation algorithm and store the address into the off-chip address cache module.
More specifically, in some embodiments, the determining a source of the data read/write address according to the operation algorithm to be executed, that is, step S220, includes:
and selecting, by the selection module, to acquire the first address from the private address generation module and/or to acquire the second address from the off-chip address cache module.
Optionally, in some embodiments, after obtaining the specified data read-write address based on the data read-write address source, the method further includes:
and judging whether the residual space of the address cache is smaller than a preset space, if so, sending a back pressure signal to the on-chip address cache module or the special address generation module to suspend receiving the first address and/or the second address. The address cache residual space refers to a cache space of the on-chip address cache module, after the address in the on-chip address cache module is taken out and is larger than a preset space, the address cache residual space sends a back pressure closing signal to the on-chip address cache module or the special address generation module, and at the moment, the on-chip address cache module continues to send a second address or the special address generation module to the on-chip address cache module to continue to send a first address to the on-chip address cache module.
The embodiment provides a data processing method based on an artificial intelligence chip compatible with different data access modes, a first address can be generated by a special address generating module of the artificial intelligence chip according to a preset algorithm, a selection module selects to receive the first address generated by the special address generating module or to receive a second address from external input, a data caching module realizes to transmit data to be processed to a specified address according to the first address or the second address selected by the selection module while caching the data to be processed, and an operation module receives the data to be processed to complete operation, the chip can use the first address generated by the chip and can also select the second address input from the outside, the compatibility is stronger, the chip can adapt to the algorithm change of a special processor, and the new algorithm requirement can be met by the second address input from the outside, meanwhile, special requirements of non-common complex algorithms on addresses can be considered.
It is to be noted that the foregoing description is only exemplary of the invention and that the principles of the technology may be employed. Those skilled in the art will appreciate that the present invention is not limited to the particular embodiments described herein, and that various obvious changes, rearrangements and substitutions will now be apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in some detail by the above embodiments, the invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the invention, and the scope of the invention is determined by the scope of the appended claims.
Claims (10)
1. An artificial intelligence chip compatible with different data access modes, comprising:
the special address generating module is used for generating a first address according to a preset algorithm;
the selection module is used for selecting and receiving the first address and/or a second address of an external input;
the data caching module is used for caching the data to be processed and transmitting the data to be processed according to the first address and/or the second address;
and the operation module is used for receiving the data to be processed and completing the operation of the data to be processed.
2. The artificial intelligence chip of claim 1, further comprising:
and the on-chip address caching module is arranged between the selection module and the data caching module and is used for caching the first address and/or the second address.
3. The artificial intelligence chip of claim 2, further comprising:
and the off-chip address cache module is connected with the selection module and used for receiving and storing a second address generated by an external chip.
4. The artificial intelligence chip of claim 1, wherein the artificial intelligence chip is compatible with different data access modes:
The operation module is further configured to return an operation result of the to-be-processed data to the data cache module, so that the data cache module completes saving back of the operation result according to the first address and/or the second address.
5. The artificial intelligence chip of claim 3 wherein the on-chip address cache module is further configured to:
and judging whether the residual space of the address cache is less than or equal to a preset space, if so, sending a back pressure signal to the on-chip address cache module or the special address generation module to suspend receiving the first address and/or the second address.
6. A data processing method based on the artificial intelligence chip compatible with different data access modes as claimed in any one of claims 1 to 5, comprising:
determining a data read-write address source according to an operation algorithm to be operated;
acquiring a specified data read-write address based on the data read-write address source;
sending the data to be processed to the operation module according to the data read-write address to complete operation and generate an operation result;
and storing the operation result back according to the data read-write address.
7. The data processing method according to claim 6, wherein the source of the data read/write address includes the dedicated address generating module and/or the off-chip address caching module, the data read/write address includes the first address and/or the second address, and before obtaining the specified data read/write address based on the source of the data read/write address, the method further includes:
judging whether the source of the data read-write address is a special address generation module;
if so, configuring the special address generation module according to the operation algorithm so that the special address generation module generates the first address;
if not, generating the second address by an external chip according to an address generating program corresponding to the operation algorithm, and storing the second address into the off-chip address cache module.
8. The data processing method of claim 7, wherein the determining a source of the data read/write address according to the operation algorithm to be executed comprises:
and selecting, by the selection module, to acquire the first address from the private address generation module and/or to acquire the second address from the off-chip address cache module.
9. The data processing method according to claim 7, wherein after obtaining the specified data read/write address based on the data read/write address source, the method further comprises:
And judging whether the residual space of the address cache is smaller than a preset space, if so, sending a back pressure signal to the off-chip address cache module or the special address generating module to pause receiving the first address and/or the second address.
10. The data processing method of claim 6, wherein the data read and write addresses comprise a read address and a copy-back address.
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