CN114512496A

CN114512496A - Array substrate, preparation method thereof and display device

Info

Publication number: CN114512496A
Application number: CN202011291733.7A
Authority: CN
Inventors: 晏国文
Original assignee: Shenzhen Royole Technologies Co Ltd
Current assignee: Shenzhen Royole Technologies Co Ltd
Priority date: 2020-11-17
Filing date: 2020-11-17
Publication date: 2022-05-17

Abstract

The embodiment of the application provides an array substrate, a preparation method thereof and a display device, wherein the array substrate comprises: a substrate; the driving circuit is arranged on the substrate and comprises at least one first thin film transistor, the first thin film transistor comprises a first active layer and a first gate layer, the first active layer and the first gate layer are arranged oppositely and in an insulating mode, and the distance between the first active layer and the first gate layer is a first distance; the pixel circuit is arranged on the substrate and electrically connected with the driving circuit, the pixel circuit comprises at least one second thin film transistor, the second thin film transistor comprises a second active layer and a second gate layer, the second active layer and the second gate layer are arranged oppositely and in an insulating mode, the distance between the second active layer and the second gate layer is a second distance, and the second distance is larger than the first distance. The application provides an array substrate for promoting a narrow frame and improving a display effect, a preparation method of the array substrate and a display device.

Description

Array substrate, preparation method thereof and display device

Technical Field

The application relates to the technical field of electronics, in particular to an array substrate, a preparation method of the array substrate and a display device.

Background

The array substrate is internally provided with a plurality of thin film transistors, the output current of the thin film transistors required in some scenes is relatively large, and the output current of the thin film transistors required in other scenes is relatively small, so that how to adjust the output current of the thin film transistors is to reach the most suitable output current in different use scenes, promote narrow frames and improve the display effect of the display device, and the technical problem to be solved is solved.

Disclosure of Invention

The application provides an array substrate for promoting a narrow frame and improving a display effect, a preparation method of the array substrate and a display device.

In a first aspect, an embodiment of the present application provides an array substrate, including:

a substrate;

the driving circuit is arranged on the substrate and comprises at least one first thin film transistor, the first thin film transistor comprises a first active layer and a first gate layer, the first active layer and the first gate layer are arranged oppositely and in an insulating mode, and the distance between the first active layer and the first gate layer is a first distance; and

the pixel circuit is arranged on the substrate and electrically connected with the driving circuit, the pixel circuit comprises at least one second thin film transistor, the second thin film transistor comprises a second active layer and a second gate layer, the second active layer and the second gate layer are opposite and insulated, the distance between the second active layer and the second gate layer is a second distance, and the second distance is larger than the first distance.

In a second aspect, an embodiment of the present application provides a display device, where the display device includes the array substrate, the display device has a display area and a non-display area, the driving circuit is disposed in the non-display area, and the pixel circuit is disposed in the display area.

In a third aspect, an embodiment of the present application provides a method for manufacturing an array substrate, including:

forming a substrate;

forming a first active layer of a first thin film transistor and a second active layer of a second thin film transistor on the substrate, the first thin film transistor being for forming a driving circuit, the second thin film transistor being for forming a pixel circuit;

forming a first gate layer and a second gate layer on the substrate, wherein the first gate layer is opposite to and spaced from the first active layer, the second gate layer is opposite to and spaced from the second active layer, and the distance between the first gate layer and the first active layer is smaller than the distance between the second gate layer and the second active layer.

The distance between the first grid layer and the first active layer of the first thin film transistor in the driving circuit is smaller than the distance between the second grid layer and the second active layer of the second thin film transistor in the pixel circuit, so that the output current of the first thin film transistor in the driving circuit is relatively large, the number of the first thin film transistors can be reduced or the area occupied by the first thin film transistor can be reduced, the area occupied by the driving circuit at a frame can be further reduced, and the narrow frame can be favorably realized; and the output current of the second thin film transistor in the pixel circuit is relatively small, the positive bias temperature pressure of the second thin film transistor can be reduced, the afterimage phenomenon caused by overlarge positive bias temperature pressure is further reduced, and the display effect of the display device is improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a display device according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a display screen provided in FIG. 1;

FIG. 3 is a cross-sectional view of the display screen provided in FIG. 2 taken along line A-A;

FIG. 4 is a top view of the array substrate provided in FIG. 3;

fig. 5 is a partial cross-sectional view of an array substrate according to an embodiment of the present application;

FIG. 6 is a top view of the first thin film transistor provided in FIG. 5;

fig. 7 is a partial cross-sectional view of an array substrate according to a second embodiment of the present application;

fig. 8 is a partial cross-sectional view of an array substrate according to a third embodiment of the present application;

fig. 9 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present disclosure;

fig. 10 is a flowchart of a method for manufacturing an array substrate according to a second embodiment of the present application;

fig. 11 is a flowchart of a method for manufacturing an array substrate according to a third embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, and not all embodiments. The embodiments listed in the present application may be appropriately combined with each other.

Referring to fig. 1, the present embodiment provides a display device 100, where the display device 100 includes, but is not limited to, a mobile phone, a desktop computer, a tablet computer, a television, a wearable device, a camera, a vehicle-mounted display device 100, a display screen, a projector, a smart television, an advertisement display screen, a cinema display screen, and other display products.

Referring to fig. 1 and 2, the display device 100 includes a display screen 200. The display screen 200 has a display surface 101. The display surface 101 is a surface on which an image is displayed on the display device 100. The display surface 101 includes a display area 102 and a non-display area 103 surrounding the display area 102. The display area 102 is an area on the display surface 101 where an image is displayed. Optionally, the non-display area 103 is a frame surrounding the display screen 200 of the display device 100; alternatively, the non-display area 103 is a "black border" area of the display screen 200 of the display device 100, wherein the "black border" area is formed by coating dark light-shielding ink on the inner side of the light-transmissive cover plate of the display screen 200.

Referring to fig. 3, the display panel 200 includes an array substrate 10. Specifically, the array substrate 10 is a thin film transistor array substrate. It is understood that the display screen 200 of the display device 100 is divided in principle from light emission, and includes, but is not limited to, an organic light emitting diode display screen, a liquid crystal display screen, and the like. The present embodiment will be described by taking the display panel 200 of the display device 100 as an example of an organic light emitting diode display panel. The display screen 200 of the display device 100 includes, but is not limited to, a flexible display screen or a hard and non-bendable display screen, which is divided from the bending performance of the display screen 200 of the display device 100.

For convenience of description, the thickness direction of the array substrate 10 is defined as a Z-axis direction, the length direction of the array substrate 10 is defined as a Y-axis direction, and the width direction of the array substrate 10 is defined as an X-axis direction.

Referring to fig. 3, in detail, the array substrate 10 includes a substrate 1, and a driving circuit 2 and a pixel circuit 3 disposed on the substrate 1.

Referring to fig. 3, the substrate 1 includes a display pixel region 11 and a peripheral region 12 surrounding the display pixel region 11. The display pixel region 11 constitutes a part of the display region 102, and the peripheral region 12 constitutes a part of the non-display region 103. In other words, the display pixel region 11 faces the display region 102, and the peripheral region 12 faces the non-display region 103. Specifically, the substrate 1 may be a hard substrate or a flexible substrate. The material of the hard substrate includes, but is not limited to, glass, ceramic, hard plastic, etc. The material of the flexible substrate includes, but is not limited to, any one of polyimide, polyethylene terephthalate, polypropylene resin, or acrylic resin, and may also be other bendable materials suitable for preparing the flexible substrate, which is not limited herein.

It is understood that, referring to fig. 4, the display device 100 includes a plurality of sub-pixel units 13 arranged in an array. The sub-pixel unit 13 includes at least three colors of sub-pixel units 13. Specifically, the pixel structure comprises a red sub-pixel unit, a green sub-pixel unit and a blue sub-pixel unit. The three color sub-pixel units 13 are used to form a color. The sub-pixel unit 13 is located in the display pixel region 11. Each sub-pixel unit 13 is provided with a pixel circuit 3. The pixel circuit 3 is disposed in the display area 102 of the display device 100. The pixel circuit 3 is used to drive the sub-pixel unit 13 to be turned on or off, control the brightness of the lighting, and the like. In other words, the number of the pixel circuits 3 is plural, and each pixel circuit 3 is disposed in one sub-pixel unit 13.

Specifically, the pixel circuit 3 includes at least one or more thin film transistors, one or more storage capacitors, and the like. The thin film transistor includes a switching transistor (not shown) and a driving transistor (not shown). The switch transistor is controlled by a scanning signal and is used for controlling the data signal to enter the driving transistor. The driving transistor is used to control a current through the organic light emitting device. The storage capacitor is used for storing the gray scale voltage to determine the driving current of the driving transistor.

Referring to fig. 4, the display pixel region 11 of the array substrate 10 is further provided with a plurality of data lines 14 and a plurality of scan lines 15. The extending direction of the data lines 14, the spacing between the data lines 14, the extending direction of the scan lines 15, and the spacing between the scan lines 15 are not particularly limited in this application. For example, the data lines 14 are disposed in parallel and at equal intervals, and the scan lines 15 are disposed in parallel and at equal intervals. The extending direction of the data lines 14 intersects the extending direction of the scan lines 15. The angle of intersection is not particularly limited in this application. For example, the extending direction of the data line 14 is perpendicular to the extending direction of the scan line 15. However, the data lines 14 are not in contact with the scan lines 15. In other words, the data lines 14 and the scan lines 15 may be disposed on two different layers, respectively, and an insulating layer is disposed between the two different layers for insulation.

Two adjacent data lines 14 and two adjacent scan lines 15 include a region where one sub-pixel unit 13 is located. The pixel circuit 3 is provided in the sub-pixel unit 13. The pixel circuit 3 includes a plurality of input interfaces and output interfaces, wherein one input interface of the pixel circuit 3 is electrically connected to the data line 14, and the other input interface is electrically connected to the scan line 15. In this embodiment, the display panel 200 is a light emitting diode display panel 200, and one output interface of the pixel circuit 3 is electrically connected to the organic light emitting device.

Referring to fig. 4, the driving circuit 2 is disposed in the peripheral region 12. In other words, the driving circuit 2 is disposed in the non-display area 103 of the display device 100. The peripheral region 12 surrounds the periphery of the display pixel region 11, and the driving circuit 2 may be disposed on one side, two sides or the periphery of the display pixel region 11. It is understood that the driving circuit 2 electrically connects the scan lines 15 and the data lines 14. Specifically, the driving circuit 2 includes a plurality of data driving circuits 21 and a plurality of gate driving circuits 22. Each data driving circuit 21 is electrically connected to the data lines 14 to which the sub-pixel units 13 of one row are electrically connected. The gate driving circuit 22 is electrically connected to the scanning lines 15 of at least one row of the sub-pixel units 13.

The source driver chip in the display device 100 receives image data, buffers the image data, converts digital signals into analog signals, and transmits the converted signals to each data driver circuit 21 of the array substrate 10 through an output buffer. The plurality of gate driving circuits 22 load the clock control signal, perform progressive scanning on the sub-pixel units 13 arranged in an array, generate a scanning signal which is turned on in a progressive manner for the clock control signal, load the scanning signal of each row to the corresponding scanning line 15, and then control the switching transistor in the sub-pixel unit 13 to be turned on, so that the image data transmitted by the data driving circuit 21 enters the storage capacitor of the sub-pixel unit 13 in the row through the data line 14, and finally, the normal display of the image is realized.

The drive circuit 2 supplies the pixel circuits 3 with electrical drive signals required for the display. The driving circuit 2 and the pixel circuit 3 are integrated on the substrate 1, so that the integration degree of the array substrate 10 is improved, and the overall volume of the array substrate 10 is reduced. In the present application, the connection mode between the driver circuit 2 and the pixel circuit 3 is not particularly limited. As long as the electric drive signal output from the drive circuit 2 can be transmitted to the pixel electrode. The connection mode may be an electrical connection mode with physical contact or a connection mode with non-physical contact. The driving method of the pixel circuit 3 by the driving circuit 2 includes, but is not limited to, bilateral single-drive, bilateral double-drive, etc.

Alternatively, referring to fig. 4, the plurality of data driving circuits 21 are divided into two parts. The two portions of the data driving circuit 21 are respectively disposed at two opposite sides of the display pixel region 11. The plurality of gate driving circuits 22 are divided into two parts. Two parts of the gate driving circuit 22 are respectively disposed on the other two opposite sides of the display pixel region 11, so that the driving circuit 2 is reasonably disposed in the peripheral region 12, the overall area of the peripheral region 12 is reduced, and the narrow frame design of the display device 100 is realized.

Referring to fig. 5, the driving circuit 2 includes at least one first thin film transistor 23 disposed on the substrate 1. Alternatively, the first thin film transistor 23 may be a transistor of the gate driving circuit 22, and may also be a transistor of the data driving circuit 21. In the Z-axis direction, the first thin film transistor 23 includes a first active layer 231 and a first gate layer 232 which are stacked.

The first active layer 231 is disposed opposite to and insulated from the first gate layer 232. The distance between the first active layer 231 and the first gate layer 232 is the first distance h 1. Specifically, the first distance h1 is a distance between a surface of the first active layer 231 facing the first gate layer 232 and a surface of the first gate layer 232 facing the first active layer 231.

It is understood that the first gate layer 232 may have a single-layer structure or a multi-layer structure, and the material of the first gate layer 232 having a single-layer structure includes, but is not limited to, Mo, MoW, Cr, Al alloy, Mg, Ni, W, Au, and the like. The first gate layer 232 is a multi-layer structure including but not limited to Mo, MoW, Cr, Al alloy, Mg, Ni, W and Au, for example, a stacked structure of two titanium films sandwiching an aluminum film, two molybdenum films sandwiching an aluminum film, two indium tin oxide films sandwiching an aluminum film.

The material of the first active layer 231 includes, but is not limited to, one or more of Indium Gallium Zinc Oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (InZnO), or zinc tin oxide (ZnSnO); or a low temperature polysilicon material or a polysilicon material. In this embodiment, the material of the first active layer 231 is Indium Gallium Zinc Oxide (IGZO).

The pixel circuit 3 includes at least one second thin film transistor 31 provided on the substrate 1. The first thin film transistor 23 is electrically connected to the second thin film transistor 31 to control the operating current of the second thin film transistor 31.

When the first thin film transistor 23 is a transistor of the gate driving circuit 22, a current signal output by the first thin film transistor 23 flows to the gate of the second thin film transistor 31 to control the second thin film transistor 31 to be in an on or off state. Further, when the second thin film transistor 31 is in a conducting state under the control of the output current of the first thin film transistor 23, the source of the second thin film transistor 31 can receive the current supplied by the data driving circuit 21 to control the operating current of the second thin film transistor 31. When the second thin film transistor 31 is in an off state under the control of the output current of the first thin film transistor 23, the source of the second thin film transistor 31 cannot receive the current supplied by the data driving circuit 21, and the operating current of the second thin film transistor 31 is 0.

When the first thin film transistor 23 is a transistor of the data driving circuit 21, a current signal outputted from the first thin film transistor 23 flows to a source of the second thin film transistor 31 to control an operating current of the second thin film transistor 31 when the second thin film transistor 31 is in a conducting state. The working current of the second tft 31 is used to control the brightness of the sub-pixel unit 13, and thus the display brightness of the pixel point on the display device 100 is shown.

Optionally, referring to fig. 5, the second thin film transistor 31 includes a second active layer 311 and a second gate layer 312. The second active layer 311 is disposed opposite to and insulated from the second gate layer 312. It is understood that the second gate layer 312 may have a single-layer structure or a multi-layer structure, and the material of the second gate layer 312 has a single-layer structure including, but not limited to, Mo, MoW, Cr, Al alloy, Mg, Ni, W, Au, and the like. The second gate layer 312 is a multi-layer structure including but not limited to Mo, MoW, Cr, Al alloy, Mg, Ni, W and Au, for example, a stacked structure of two titanium films sandwiching an aluminum film, two molybdenum films sandwiching an aluminum film, two indium tin oxide films sandwiching an aluminum film.

The material of the second active layer 311 includes, but is not limited to, one or more of Indium Gallium Zinc Oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (InZnO), or zinc tin oxide (ZnSnO); or a low temperature polysilicon material or a polysilicon material. In this embodiment, the material of the second active layer 311 is Indium Gallium Zinc Oxide (IGZO).

The spacing between the second active layer 311 and the second gate layer 312 is the second spacing h 2. Specifically, the second distance h2 is a distance between a surface of the second active layer 311 facing the second gate layer 312 and a surface of the second gate layer 312 facing the second active layer 311.

In this embodiment, the second distance h2 is greater than the first distance h 1. In other words, the channel pitch of the first thin film transistor 23 is smaller than the channel pitch of the second thin film transistor 31. Under the condition of the same channel facing area, the channel capacitance of the first thin film transistor 23 is larger than that of the second thin film transistor 31, so that the output current of the first thin film transistor 23 is larger than that of the second thin film transistor 31.

In the conventional art, the first thin film transistor 23 and the second thin film transistor 31 are located in the same layer. The first thin film transistor 23 and the second thin film transistor 31 are manufactured in the same photomask process, so that the production efficiency of the array substrate 10 is higher; moreover, the layer structures of the first thin film transistor 23 and the second thin film transistor 31 are manufactured in the same process, so that the constituent materials of the layer structures are the same, and therefore, the processes and the constituent materials of the first thin film transistor 23 and the second thin film transistor 31 are the same or similar, so that the performance uniformity of the thin film transistors of the driving circuit 2 and the pixel circuit 3 is better. In this way, the distance between the first active layer 231 of the first thin film transistor 23 and the first gate layer 232 is equal to the distance between the second active layer 311 of the second thin film transistor 31 and the second gate layer 312. For example, the channel pitch of the thin film transistors of the drive circuit 2 is about 100nm, and the channel pitch of the thin film transistors of the pixel circuit 3 is about 100 nm.

The skilled person of the application finds that the increase of the output current of the thin film transistor increases the positive bias temperature and pressure of the thin film transistor, thereby causing the display ghost phenomenon; however, for the first thin film transistor 23, since the first thin film transistor 23 is located in the non-display area 103, the output current of the first thin film transistor 23 is increased without causing the image sticking problem, and the increase of the output current of the first thin film transistor 23 is beneficial to reducing the channel facing area of the first thin film transistor 23 or reducing the number of the first thin film transistors 23, thereby reducing the area occupied by the first thin film transistor 23 in the non-display area 103, and being beneficial to realizing the narrow frame effect.

The channel pitch of the first thin film transistor 23 is smaller than the channel pitch of the second thin film transistor 31 including but not limited to the following cases: the first is to reduce the channel pitch of the first thin film transistor 23 while keeping the channel pitch of the second thin film transistor 31 at the pitch in the conventional process; secondly, the channel spacing of the second thin film transistor 31 is increased, and the channel spacing of the first thin film transistor 23 is kept to be the spacing in the conventional process; the third is to decrease the channel pitch of the first thin film transistor 23 and increase the channel pitch of the second thin film transistor 31.

In the embodiment of the present application, the channel pitch of the first thin film transistor 23 is smaller than the channel pitch of the second thin film transistor 31. Specifically, the first distance h1 is 10-100 nm. The second spacing h2 is 100-500 nm or more than 500 nm.

By reducing the channel distance of the first thin film transistor 23, the channel capacitance between the first active layer 231 and the first gate layer 232 can be increased, the electric field intensity generated when the first gate layer 232 is loaded with the same voltage is increased, and thus the number of carriers generated by channel induction is increased, so that the output current of the first thin film transistor 23 is increased, the channel dead-front area of the first thin film transistor 23 can be reduced or the number of the first thin film transistors 23 is reduced, and further the area occupied by the first thin film transistor 23 in the non-display area 103 is reduced, which is beneficial to realizing the narrow-frame effect.

By increasing the channel distance of the second thin film transistor 31, the channel capacitance between the second active layer 311 and the second gate layer 312 is reduced, the electric field strength generated when the same voltage is applied to the second gate layer 312 is reduced, the binding capability of the second gate layer 312 to the carriers of the channel is reduced, the carriers captured by defects in the second thin film transistor 31 are reduced, the second thin film transistor 31 is more stable, the array substrate 10 is more stable, the afterimage of the display device 100 is effectively reduced, and the display effect of the display device 100 is improved.

In the array substrate 10 provided in the embodiment of the present application, by setting the distance between the first gate layer 232 and the first active layer 231 of the first thin film transistor 23 in the driving circuit 2 to be smaller than the distance between the second gate layer 312 and the second active layer 311 of the second thin film transistor 31 in the pixel circuit 3, the output current of the first thin film transistor 23 in the driving circuit 2 is relatively large, the number of the first thin film transistors 23 can be reduced, or the area occupied by the first thin film transistor 23 in the non-display region 103 can be reduced, so that the area occupied by the driving circuit 2 at the frame can be reduced, which is beneficial to realizing a narrow frame; the output current of the second thin film transistor 31 in the pixel circuit 3 is relatively small, which can reduce the forward bias temperature pressure of the second thin film transistor 31, thereby reducing the afterimage phenomenon caused by the excessive forward bias temperature pressure and improving the display effect of the display device 100.

It is understood that the present application is not limited to the number and the position of the first thin film transistors 23 in the driving circuit 2; the present application does not limit the number and the position of the second thin film transistors 31 in the pixel circuit 3. For example, all the tfts in the driving circuit 2 are the first tfts 23, and all the tfts in the pixel circuit 3 are the second tfts 31.

The number and shape of the gate layers of the first thin film transistor 23 and the number and shape of the gate layers of the second thin film transistor 31 are not particularly limited. The gate layer of the first thin film transistor 23 includes, but is not limited to, a double-layer gate structure, a ring-shaped gate structure, and the like disposed above and below. The gate layer of the second thin film transistor 31 includes, but is not limited to, a double-layer gate structure, a ring-shaped gate structure, and the like disposed above and below.

The specific structures of the first thin film transistor 23 and the second thin film transistor 31 provided in the present application are illustrated below with reference to the drawings. For convenience of illustration, the first thin film transistor 23 and the second thin film transistor 31 are put together in the embodiments of the present application, which is convenient for putting the first thin film transistor 23 and the second thin film transistor 31 in the same illustration, and does not represent the actual position between the first thin film transistor 23 and the second thin film transistor 31 in the actual product.

Referring to fig. 5, in a first possible implementation, the first thin film transistor 23 further includes a third gate layer 233. The third gate layer 233 is located on a side of the first active layer 231 facing away from the first gate layer 232. The third gate layer 233 is electrically connected to the first gate layer 232. The third gate layer 233 is disposed opposite to and insulated from the first active layer 231. The first gate layer 232 is distant from the buffer layer 161 with respect to the third gate layer 233.

It is understood that the third gate layer 233 may have a single-layer structure or a multi-layer structure, and the material of the third gate layer 233 has a single-layer structure, including but not limited to Mo, MoW, Cr, Al alloy, Mg, Ni, W, Au, and the like. The third gate layer 233 is a multi-layer structure including but not limited to Mo, MoW, Cr, Al alloy, Mg, Ni, W and Au, for example, a stacked structure of two titanium films sandwiching an aluminum film, two molybdenum films sandwiching an aluminum film, two indium tin oxide films sandwiching an aluminum film.

A third distance h3 is formed between the third gate layer 233 and the first active layer 231. The third distance h3 is a distance between a surface of the third gate layer 233 facing the first active layer 231 and a surface of the first active layer 231 facing the third gate layer 233.

The third spacing h3 is less than the second spacing h 2. Further, the third spacing h3 may be greater than, less than, or equal to the first spacing h 1. In this embodiment, the first spacing h1 and the third spacing h3 are both 10-100 nm. The second spacing h2 is 100-500 nm or more than 500 nm.

In this embodiment, the material of the first active layer 231 is Indium Gallium Zinc Oxide (IGZO). By providing the gate layer of the first thin film transistor 23 as a double-layer gate structure, the stability of the first thin film transistor 23 in which the first active layer 231 is made of the indium gallium zinc oxide material can be increased.

By providing the double-layer gate structure of the first thin film transistor 23, the stability of the first thin film transistor 23 can be improved, so as to further increase the channel capacitance between the gate layer and the active layer of the first thin film transistor 23, further increase the output current of the first thin film transistor 23, further reduce the number of the first thin film transistors 23 or reduce the area occupied by the first thin film transistor 23 in the non-display area 103, further reduce the frame width of the display device 100, and improve the screen area ratio.

Alternatively, the gate layer of the first thin film transistor 23 may be a double-layer gate layer, and the gate layer of the second thin film transistor 31 may be a double-layer gate layer or a single-layer gate layer.

Further, referring to fig. 5, the second thin film transistor 31 further includes a fourth gate layer 313. The fourth gate layer 313 is located on a side of the second active layer 311 facing away from the second gate layer 312. The fourth gate layer 313 is electrically connected to the second gate layer 312. The fourth gate layer 313 is disposed opposite to and insulated from the second active layer 311. The second gate layer 312 is distant from the buffer layer 161 with respect to the fourth gate layer 313.

It is understood that the fourth gate layer 313 may have a single-layer structure or a multi-layer structure, and the material of the fourth gate layer 313 having a single-layer structure includes, but is not limited to, Mo, MoW, Cr, Al alloy, Mg, Ni, W, Au, and the like. The fourth gate layer 313 may be a multilayer structure including, but not limited to, Mo, MoW, Cr, Al alloy, Mg, Ni, W, and Au, for example, a laminated structure of two titanium films sandwiching an aluminum film, two molybdenum films sandwiching an aluminum film, two indium tin oxide films sandwiching an aluminum film.

The fourth gate layer 313 and the second active layer 311 have a fourth gap h4 therebetween. The fourth interval h4 is an interval between a surface of the fourth gate layer 313 facing the second active layer 311 and a surface of the second active layer 311 facing the fourth gate layer 313.

Alternatively, the fourth spacing h4 may be greater than, less than, or equal to the second spacing h 2. The fourth spacing h4 is greater than or equal to the third spacing h 3. In the present embodiment, the fourth distance h4 is equal to the third distance h 3. In this embodiment, the first distance h1, the third distance h3, and the fourth distance h4 are all 10-100 nm. The second spacing h2 is 100-500 nm or more than 500 nm.

The material of the second active layer 311 includes, but is not limited to, one or more of Indium Gallium Zinc Oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (InZnO), or zinc tin oxide (ZnSnO); or a low temperature polysilicon material or a polysilicon material. In this embodiment, the material of the second active layer 311 is Indium Gallium Zinc Oxide (IGZO). By providing the gate layer of the second tft 31 as a double-layer gate structure, the stability of the second tft 31 having the second active layer 311 made of the indium gallium zinc oxide material can be increased.

By arranging the second thin film transistor 31 as a double-layer gate structure, the stability of the second thin film transistor 31 can be ensured, the channel capacitance on the upper side and the lower side of the second active layer 311 can be reduced by increasing the channel distance on one side of the second active layer 311, the electric field intensity generated when the same voltage is loaded on the second gate layer 312 and the fourth gate layer 313 is reduced, the binding capacity of the second gate layer 312 and the fourth gate layer 313 to the carriers of the channel is reduced, the carriers trapped by defects in the second thin film transistor 31 are reduced, the second thin film transistor 31 is more stable, the array substrate 10 is more stable, the afterimage of the display device 100 is effectively reduced, and the display effect of the display device 100 is improved.

Further, referring to fig. 5, the array substrate 10 further includes a buffer layer 161, a blocking layer 162, a first gate insulating layer 165, a second gate insulating layer 166, an interlayer dielectric layer 169, a first electrode 171, a second electrode 172, a third electrode 173, and a fourth electrode 174.

The buffer layer 161 is provided on the substrate 1, and the buffer layer 161 is made of an organic material and is formed on the substrate 1 by a low-temperature film formation technique such as printing or vapor deposition. Because the low-temperature film formation can prolong the path of water vapor penetration, the organic light emitting devices and electrodes in the organic light emitting diode display device 100 can be effectively prevented from being invaded by water oxygen, and the service life of the organic light emitting diode display device 100 is prolonged; the flexibility of the array substrate 10 may also be improved.

The third gate layer 233 and the fourth gate layer 313 are arranged on the buffer layer 161 at intervals; alternatively, the first gate layer 232 and the second gate layer 312 are spaced on the buffer layer 161. In this embodiment, the third gate layer 233 and the fourth gate layer 313 are disposed on the buffer layer 161 at an interval.

Referring to fig. 6, from the perspective of the X-Y plane, the third gate layer 233 includes a body metal layer 2331 and an extension metal layer 2332. The extension direction of the extension metal layer 2332 intersects the extension direction of the body metal layer 2331. Further, the extension direction of the extension metal layer 2332 is perpendicular to the extension direction of the body metal layer 2331.

The blocking layer 162 covers the buffer layer 161, the third gate layer 233, and the fourth gate layer 313. The barrier layer 162 is used for blocking water vapor, and can be formed by a process including, but not limited to, Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), and the like. The material of the barrier layer 162 includes, but is not limited to, a silicon oxide layer, a silicon nitride layer, or a multi-layer stacked structure made of a silicon oxide layer and a silicon nitride layer.

The first active layer 231 and the second active layer 311 are spaced on the barrier layer 162. The first active layer 231 is disposed corresponding to the third gate layer 233, and the second active layer 311 is disposed corresponding to the fourth gate layer 313.

The body metal layer 2331 and the first active layer 231 are both in the shape of a stripe. The body metal layer 2331 extends in the same direction as the first active layer 231, and extends in the Y-axis direction.

The body metal layer 2331 is disposed opposite the first active layer 231. The extension metal layer 2332 has a strip shape, and the extension metal layer 2332 extends in the X-axis direction.

Referring to fig. 6, the first gate layer 232 includes a first gate active portion 2321 and a second gate active portion 2322 integrally connected to each other. The first gate working portion 2321 and the second gate working portion 2322 are connected in the Y-axis direction. The first gate active portion 2321 is disposed opposite to the first active layer 231. The orthographic projection of the second gate active portion 2322 on the plane of the first active layer 231 is located outside the region of the first active layer 231. The second gate active portion 2322 is located on the same side of the first active layer 231 as the extension metal layer 2332.

The first gate insulating layer 165 is disposed on the first active layer 231. The second gate insulating layer 166 is disposed on the second active layer 311.

The first gate insulating layer 165 and the second gate insulating layer 166 are made of the same material, and the first gate insulating layer 165 includes, but is not limited to, a single-layer film formed of an organosilicone compound, silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, aluminum oxide, or hafnium oxide, or a multi-layer film formed of at least one of the above insulating materials.

Optionally, referring to fig. 5, the second gate insulating layer 166 includes a first insulating layer 167 and a second insulating layer 168.

The first insulating layer 167 is provided on the second active layer 311. The second insulating layer 168 is provided on the first insulating layer 167. The second gate layer 312 is disposed on the second insulating layer 168. The thickness of the first insulation layer 167 or the second insulation layer 168 is greater than or equal to the thickness of the first gate insulation layer 165.

Specifically, the first gate insulating layer 165 and the first insulating layer 167 are formed under the same mask process. The thickness of the first gate insulating layer 165 is the same as that of the first insulating layer 167.

The first gate insulating layer 165 is disposed between the first active layer 231 and the first gate layer 232, such that a distance between the first gate layer 232 and the first active layer 231 is equal to a thickness of the first gate insulating layer 165.

A patterned second insulating layer 168 is formed on the first insulating layer 167, and the sum of the thicknesses of the first insulating layer 167 and the second insulating layer 168 is greater than the thickness of the first gate insulating layer 165, so that the spacing between the second gate layer 312 and the second active layer 311 is greater than the spacing between the first gate layer 232 and the first active layer 231, i.e., the second spacing h2 is greater than the first spacing h 1.

Optionally, the first distance h1 may be smaller than the thickness of the gate insulating layer in the conventional design, and the first gate insulating layer 165 with a smaller thickness is disposed to increase the channel capacitance of the first thin film transistor 23, thereby increasing the output current of the first thin film transistor 23 and facilitating the narrow frame of the display device 100.

The first gate layer 232 is disposed on the first gate insulating layer 165. The second gate layer 312 is disposed on the second gate insulating layer 166.

The interlayer dielectric layer 169 covers the blocking layer 162, the first active layer 231, the second active layer 311, the first gate insulating layer 165, the second gate insulating layer 166, the first gate layer 232, and the second gate layer 312. The material of the interlayer dielectric layer 169 may be an organic material such as an organosilicone compound, or a single-layer inorganic material such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, aluminum oxide, hafnium oxide, or a multi-layer structure of a combination thereof, but is not limited thereto.

Referring to fig. 6, the array substrate 10 further includes a conductive connection layer 175 disposed on the interlayer dielectric layer 169. Opposite ends of the conductive connection layer 175 are electrically connected to the extension metal layer 2332 and the second gate active portion 2322 through conductive vias, respectively, so that the third gate layer 233 is electrically connected to the first gate layer 232. Similarly, electrical connection of the second gate layer 312 and the fourth gate layer 313 may be achieved.

The first electrode 171, the second electrode 172, the third electrode 173 and the fourth electrode 174 are all disposed on the interlayer dielectric layer 169. The first electrode 171 and the second electrode 172 are electrically connected to the first active layer 231 from opposite sides of the first gate electrode 232, respectively. The third electrode 173 and the fourth electrode 174 are electrically connected to the second active layer 311 from opposite sides of the second gate electrode 312, respectively.

The first electrode 171 and the second electrode 172 are a source or a drain of the first thin film transistor 23, respectively; alternatively, the first electrode 171 and the second electrode 172 are a drain electrode or a source electrode of the first thin film transistor 23, respectively.

The third electrode 173 and the fourth electrode 174 are a source or a drain of the second thin film transistor 31, respectively; alternatively, the third electrode 173 and the fourth electrode 174 are a drain electrode or a source electrode of the second thin film transistor 31, respectively.

The first electrode 171, the second electrode 172, the third electrode 173 and the fourth electrode 174 may be formed in the same process, that is, a metal material layer is formed on the interlayer dielectric layer 169 and patterned to form the first electrode 171, the second electrode 172, the third electrode 173 and the fourth electrode 174. The metal material layer may be a single-layer or multi-layer structure, and the material of the metal material layer includes, but is not limited to, at least one of Mo, Cr, Al, Mg, Ti, Nd, Cu, Ta, Ni, W, Au, Ag, and alloys thereof, such as a multi-layer structure of Mo/Al/Mo.

Optionally, the data driving circuit 21 and the source and drain electrodes of the thin film transistor are disposed in the same layer. The gate driving circuit 22 may be disposed in the same layer as the source and drain electrodes of the thin film transistor, or in the same layer as the gate electrode layer of the thin film transistor.

Further, the array substrate 10 further includes a passivation layer (not shown) covering the interlayer dielectric layer 169, the first electrode 171, the second electrode 172, the third electrode 173 and the fourth electrode 174. The passivation layer is used for blocking ions from entering the thin film transistor, and the ions are prevented from influencing the electrical performance of the thin film transistor. The passivation layer is made of an inorganic insulating material, and the inorganic insulating material includes, but is not limited to, silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, and the like.

The third gate layer 233, the first active layer 231, the first gate layer 232, the first electrode 171 and the second electrode 172 form the first thin film transistor 23. The fourth gate layer 313, the second active layer 311, the second gate layer 312, the third electrode 173 and the fourth electrode 174 form the second thin film transistor 31.

In this embodiment, by providing the first thin film transistor 23 and the second thin film transistor 31 both with a double-layer gate structure, the stability of the first thin film transistor 23 and the second thin film transistor 31 can be ensured; when the gate insulating layer is formed, a relatively thin insulating layer is disposed on the first active layer 231 of the first thin film transistor 23 to increase the channel capacitance of the first thin film transistor 23, thereby increasing the output current of the first thin film transistor 23 and facilitating a narrow frame of the display device 100; two insulating layers are formed on the second active layer 311 of the second thin film transistor 31, so that the channel distance of the second active layer 311 is relatively large, the channel capacitance of the second thin film transistor 31 is reduced, the output current of the second thin film transistor 31 is increased, and the display afterimage of the display device 100 is reduced. Thus, a narrow bezel of the display device 100 and an improvement in the display effect of the display device 100 can be realized through a simple process.

In a second possible embodiment, referring to fig. 7, the present embodiment is substantially the same as the first embodiment, and the main difference is that: the barrier layer 162 includes a first barrier layer 163 and a second barrier layer 164 that are disposed in a stack. Optionally, the first barrier layer 163 is a patterned layer. The first blocking layer 163 is disposed on the fourth gate layer 313 and covers the fourth gate layer 313. The first blocking layer 163 is spaced apart from the fourth gate layer 313. In other words, the first blocking layer 163 does not cover the third gate layer 233.

The second barrier layer 164 is provided on a side of the first barrier layer 163 facing away from the buffer layer 161. The second blocking layer 164 covers the buffer layer 161, the third gate layer 233, and the first blocking layer 163.

As such, the distance between the third gate layer 233 and the first active layer 231 is the thickness of the second blocking layer 164 in the Z-axis direction. In other words, the third spacing h3 is the thickness of the second barrier layer 164 in the Z-axis direction. The distance between the fourth gate layer 313 and the second active layer 311 is the overlapping thickness of the first blocking layer 163 and the second blocking layer 164 in the Z-axis direction. In other words, the fourth spacing h4 is the sum of the thicknesses of the second barrier layer 164 and the first barrier layer 163 in the Z-axis direction. In this way, it is achieved that the fourth spacing h4 is greater than the third spacing h 3.

Alternatively, the thickness of the second barrier layer 164 may be less than the spacing between the gate layer and the active layer in conventional designs; so that the channel pitch on both sides of the first thin film transistor 23 is small.

In this embodiment, the barrier layer 162 corresponding to the second thin film transistor 31 is a double-layer structure, and the barrier layer 162 corresponding to the first thin film transistor 23 is a single-layer structure, so that the distance between the third gate layer 233 and the second active layer 311 of the second thin film transistor 31 is greater than the distance between the fourth gate layer 313 and the first active layer 231 of the first thin film transistor 23.

By reducing the channel distance on both sides of the first active layer 231, the channel capacitance on the upper side and the lower side of the first active layer 231 can be reduced, and the output current of the first thin film transistor 23 is larger, which is beneficial to the narrow frame design of the display device 100; by increasing the channel distance on both sides of the second active layer 311, the capacitance of the channel on the upper side and the lower side of the second active layer 311 can be reduced, the electric field intensity generated when the same voltage is loaded on the second gate layer 312 and the fourth gate layer 313 is reduced, the binding capability of the second gate layer 312 and the fourth gate layer 313 to the carrier of the channel is reduced, the carrier captured by the defect in the second thin film transistor 31 is reduced, the second thin film transistor 31 is more stable, the array substrate 10 is more stable, the afterimage of the display device 100 is effectively reduced, and the display effect of the display device 100 is improved.

In a third possible embodiment, referring to fig. 8, the present embodiment is different from the first embodiment in that the positions of the third gate layer 233 and the first gate layer 232 are interchanged. The third gate layer 233 is adjacent to the buffer layer 161. The positions of the fourth gate layer 313 and the second gate layer 312 are interchanged. The fourth gate layer 313 is adjacent to the buffer layer 161 with respect to the second gate layer 312. The thickness of the first gate insulating layer 165 is the same as that of the second gate insulating layer 166.

Further, the barrier layer 162 includes a first barrier layer 163 and a second barrier layer 164 which are stacked. The first barrier layer 163 is a patterned layer. The first blocking layer 163 is disposed on the second gate layer 312 and covers the second gate layer 312. The first blocking layer 163 is spaced apart from the first gate layer 232. In other words, the first blocking layer 163 does not cover the first gate layer 232. The second barrier layer 164 is disposed on a side of the first barrier layer 163 facing away from the buffer layer 161. The second blocking layer 164 covers the buffer layer 161, the first gate layer 232, and the first blocking layer 163.

In the present embodiment, when the blocking layer is formed, the relatively thin blocking layer is disposed on the first active layer 231 of the first thin film transistor 23 to increase the channel capacitance of the first thin film transistor 23, so as to increase the output current of the first thin film transistor 23, thereby facilitating the narrow frame of the display device 100; two barrier layers are formed at the second active layer 311 of the second thin film transistor 31, so that the channel distance of the second active layer 311 is relatively large, the channel capacitance of the second thin film transistor 31 is reduced, the output current of the second thin film transistor 31 is increased, and the display afterimage of the display device 100 is reduced. Thus, a narrow bezel of the display device 100 and an improvement in the display effect of the display device 100 can be realized through a simple process.

Referring to fig. 9 and 5, a method for manufacturing an array substrate 10 according to an embodiment of the present disclosure includes the following steps. The method provided by the present embodiment is used for preparing the array substrate provided by the first embodiment.

S110: a substrate 1 is formed.

Specifically, the substrate 1 includes, but is not limited to, a rigid substrate or a flexible substrate. In this embodiment, the substrate 1 is a flexible substrate. The material of the substrate 1 includes, but is not limited to, polyimide, etc.

S120: forming a buffer layer 161 on a substrate 1, and forming a third gate layer 233 and a fourth gate layer 313 on the buffer layer 161; forming a barrier layer 162 on the buffer layer 161, the third gate layer 233, and the fourth gate layer 313; forming a first active layer 231 and a second active layer 311 on the barrier layer 162; a first gate insulating layer 165 and a first insulating layer 167 are formed on the barrier layer 162, the first active layer 231, and the second active layer 311, and a second insulating layer 168 is formed on the first insulating layer 167 such that the thickness of the first insulating layer 167 is greater than or equal to the first gate insulating layer 165.

Specifically, a buffer layer 161 is formed on a substrate 1, a first layer of metal material is formed on the buffer layer 161, and the first layer of metal material is patterned to form a third gate layer 233 and a fourth gate layer 313; forming a barrier layer 162 on the buffer layer 161, the third gate layer 233, and the fourth gate layer 313; forming a semiconductor material layer on the barrier layer 162, and patterning the semiconductor material layer to form a first active layer 231 and a second active layer 311; a first layer of insulating material is formed on the barrier layer 162, the first active layer 231 and the second active layer 311, a second layer of insulating material is formed at a position corresponding to the second active layer 311, and the first layer of insulating material and the second layer of insulating material are patterned, such that the first layer of insulating material forms the first gate insulating layer 165 and the first insulating layer 167, and the second layer of insulating material forms the second insulating layer 168. The thickness of the first insulating layer 167 is made greater than or equal to the first gate insulating layer 165. In this embodiment, the thickness of the first insulation layer 167 is equal to the thickness of the first gate insulation layer 165.

S130: forming a first gate layer 232 on the first gate insulating layer 165 and a second gate layer 312 on the second insulating layer 168 such that a distance between the first gate layer 232 and the first active layer 231 is smaller than a distance between the second gate layer 312 and the second active layer 311; forming an interlayer dielectric layer 169 on the first gate layer 232 and the second gate layer 312, and forming a plurality of via holes on the interlayer dielectric layer 169; forming a first electrode 171, a second electrode 172, a third electrode 173, and a fourth electrode 174 on the interlayer dielectric layer 169, wherein the first electrode 171 is electrically connected to one end of the first active layer 231 through a hole, the second electrode 172 is electrically connected to the other end of the first active layer 231 through a hole, the third electrode 173 is electrically connected to one end of the second active layer 311 through a hole, and the fourth electrode 174 is electrically connected to the other end of the second active layer 311 through a hole; and forming a passivation layer.

Specifically, a second layer of metal material is formed on the first gate insulating layer 165, the second insulating layer 168 and the barrier layer 162, and the second layer of metal material is patterned to form a first gate layer 232 on the first gate insulating layer 165. A second gate layer 312 is formed on the second insulating layer 168, such that the first gate layer 232 is opposite to and spaced apart from the first active layer 231, and the second gate layer 312 is opposite to and spaced apart from the second active layer 311, such that a distance between the first gate layer 232 and the first active layer 231 is smaller than a distance between the second gate layer 312 and the second active layer 311. The first gate layer 232 is electrically connected to the third gate layer 233 through a conductive via, and the second gate layer 312 is electrically connected to the fourth gate layer 313 through a conductive via. Forming an interlayer dielectric layer 169 on the first gate layer 232 and the second gate layer 312, and forming a plurality of via holes on the interlayer dielectric layer 169; forming a third layer of metal material on the interlayer dielectric layer 169, patterning the third layer of metal material to form a first electrode 171, a second electrode 172, a third electrode 173, and a fourth electrode 174, wherein the first electrode 171 is electrically connected to one end of the first active layer 231 through a hole, the second electrode 172 is electrically connected to the other end of the first active layer 231 through a hole, the third electrode 173 is electrically connected to one end of the second active layer 311 through a hole, and the fourth electrode 174 is electrically connected to the other end of the second active layer 311 through a hole; and forming a passivation layer on the third layer of metal material.

The third gate layer 233, the first active layer 231, the first gate layer 232, the first electrode 171 and the second electrode 172 form the first thin film transistor 23. The fourth gate layer 313, the second active layer 311, the second gate layer 312, the third electrode 173 and the fourth electrode 174 form the second thin film transistor 31. The first thin film transistor 23 is used to form the driving circuit 2. The second thin film transistor 31 is used to form the pixel circuit 3.

Referring to fig. 10 and fig. 7, a method for manufacturing an array substrate 10 according to a second embodiment of the present disclosure includes the following steps. The method provided by the present embodiment is used for preparing the array substrate provided by the second embodiment.

S210: a substrate 1 is formed.

S220: forming a buffer layer 161 on a substrate 1, and forming a third gate layer 233 and a fourth gate layer 313 on the buffer layer 161; forming a first blocking layer 163 on the buffer layer 161, the third gate layer 233 and the fourth gate layer 313, such that the first blocking layer 163 covers the fourth gate layer 313, and the first blocking layer 163 and the third gate layer 233 are disposed at an interval; forming the second barrier layer 164 such that the second barrier layer 164 covers the substrate 1, the third gate layer 233 and the first barrier layer 163; forming a first active layer 231, a second active layer 311 on the second barrier layer 164; a first gate insulating layer 165 and a first insulating layer 167 are formed on the second barrier layer 164, the first active layer 231, and the second active layer 311, and a second insulating layer 168 is formed on the first insulating layer 167 such that the thickness of the first insulating layer 167 is greater than or equal to the first gate insulating layer 165.

Specifically, a buffer layer 161 is formed on a substrate 1, a first layer of metal material is formed on the buffer layer 161, and the first layer of metal material is patterned to form a third gate layer 233 and a fourth gate layer 313; forming a first blocking material on the buffer layer 161, the third gate layer 233 and the fourth gate layer 313, patterning the first blocking material to form a first blocking layer 163, so that the first blocking layer 163 covers the fourth gate layer 313, and the first blocking layer 163 and the third gate layer 233 are disposed at an interval; in other words, the first barrier layer 163 does not cover the third gate layer 233; forming the second barrier layer 164 such that the second barrier layer 164 covers the substrate 1, the third gate layer 233 and the first barrier layer 163; forming a semiconductor material layer on the second barrier layer 164, and patterning the semiconductor material layer to form a first active layer 231 and a second active layer 311; a first layer of insulating material is formed on the second barrier layer 164, the first active layer 231 and the second active layer 311, a second layer of insulating material is formed at a position corresponding to the second active layer 311, and the first layer of insulating material and the second layer of insulating material are patterned, such that the first layer of insulating material forms the first gate insulating layer 165 and the first insulating layer 167, and the second layer of insulating material forms the second insulating layer 168.

S230: forming a first gate layer 232 on the first gate insulating layer 165, and a second gate layer 312 on the second insulating layer 168; forming an interlayer dielectric layer 169 on the first gate layer 232 and the second gate layer 312, and forming a plurality of via holes on the interlayer dielectric layer 169; forming a first electrode 171, a second electrode 172, a third electrode 173, and a fourth electrode 174 on the interlayer dielectric layer 169, wherein the first electrode 171 is electrically connected to one end of the first active layer 231 through a hole, the second electrode 172 is electrically connected to the other end of the first active layer 231 through a hole, the third electrode 173 is electrically connected to one end of the second active layer 311 through a hole, and the fourth electrode 174 is electrically connected to the other end of the second active layer 311 through a hole; and forming a passivation layer on the third layer of metal material.

Specifically, a second layer of metal material is formed on the first gate insulating layer 165, the second insulating layer 168 and the second barrier layer 164, and the second layer of metal material is patterned to form a first gate layer 232 on the first gate insulating layer 165. A second gate layer 312 is formed over the second insulating layer 168. The first gate layer 232 is electrically connected to the third gate layer 233 through a conductive via, and the second gate layer 312 is electrically connected to the fourth gate layer 313 through a conductive via. An interlayer dielectric layer 169 is formed on the first gate layer 232 and the second gate layer 312, and a plurality of via holes are formed on the interlayer dielectric layer 169. A third layer of metallic material is formed on the interlevel dielectric layer 169. Patterning the third layer of metal material to form a first electrode 171, a second electrode 172, a third electrode 173, and a fourth electrode 174, wherein the first electrode 171 is electrically connected to one end of the first active layer 231 through a hole, the second electrode 172 is electrically connected to the other end of the first active layer 231 through a hole, the third electrode 173 is electrically connected to one end of the second active layer 311 through a hole, and the fourth electrode 174 is electrically connected to the other end of the second active layer 311 through a hole; and forming a passivation layer on the third layer of metal material.

Referring to fig. 11 and 8, a method for manufacturing an array substrate 10 according to a third embodiment of the present disclosure includes the following steps. The method provided by the present embodiment is used for preparing the array substrate provided by the third embodiment.

S310: a substrate 1 is formed.

S320: forming a buffer layer 161 on a substrate 1, and forming a first gate layer 232 and a second gate layer 312 on the buffer layer 161; forming a first blocking layer 163 on the buffer layer 161, the first gate layer 232, and the second gate layer 312, such that the first blocking layer 163 covers the second gate layer 312, and the first blocking layer 163 and the first gate layer 232 are disposed at an interval; forming the second barrier layer 164 such that the second barrier layer 164 covers the substrate 1, the first gate layer 232 and the first barrier layer 163; forming a first active layer 231, a second active layer 311 on the second barrier layer 164; a first gate insulating layer 165 and a second gate insulating layer 166 are formed on the second blocking layer 164, the first active layer 231, and the second active layer 311.

S330: a third gate layer 233 is formed over the first gate insulating layer 165, and a fourth gate layer 313 is formed over the second insulating layer 168; forming an interlayer dielectric layer 169 on the third gate layer 233 and the fourth gate layer 313, and forming a plurality of via holes on the interlayer dielectric layer 169; forming a first electrode 171, a second electrode 172, a third electrode 173, and a fourth electrode 174 on the interlayer dielectric layer 169, wherein the first electrode 171 is electrically connected to one end of the first active layer 231 through a hole, the second electrode 172 is electrically connected to the other end of the first active layer 231 through a hole, the third electrode 173 is electrically connected to one end of the second active layer 311 through a hole, and the fourth electrode 174 is electrically connected to the other end of the second active layer 311 through a hole; and forming a passivation layer.

Forming a third gate layer on the first gate insulating layer, and a fourth gate layer on the second insulating layer; forming an interlayer dielectric layer on the third gate layer and the fourth gate layer, and forming a plurality of through holes on the interlayer dielectric layer; forming a first electrode, a second electrode, a third electrode and a fourth electrode on the interlayer dielectric layer, wherein the first electrode is electrically connected with one end of the first active layer through a hole, the second electrode is electrically connected with the other end of the first active layer through a hole, the third electrode is electrically connected with one end of the second active layer through a hole, and the fourth electrode is electrically connected with the other end of the second active layer through a hole; and forming a passivation layer.

The above are some embodiments of the present application. It should be noted that. As would be apparent to one of ordinary skill in the art. Without departing from the principles of the present application. Several improvements and refinements can also be made. Such modifications and refinements are also considered to be within the scope of the present application.

Claims

1. An array substrate, comprising:

a substrate;

2. The array substrate of claim 1, wherein the first pitch is 10 to 100nm and the second pitch is 100 to 500 nm.

3. The array substrate of claim 1, wherein the first thin film transistor further comprises a third gate layer on a side of the first active layer facing away from the first gate layer, the third gate layer electrically connected to the first gate layer, the third gate layer disposed opposite to and insulated from the first active layer, and a third gap is formed between the third gate layer and the first active layer.

4. The array substrate of claim 3, wherein the second thin film transistor further comprises a fourth gate layer on a side of the second active layer facing away from the second gate layer, the fourth gate layer electrically connected to the second gate layer, the fourth gate layer disposed opposite to and insulated from the second active layer, and a fourth gap between the fourth gate layer and the second active layer, the fourth gap being greater than or equal to the third gap.

5. The array substrate of claim 4, wherein the third pitch is 10 nm to 100nm and the fourth pitch is 100nm to 500 nm.

6. The array substrate of claim 4, wherein the array substrate further comprises a buffer layer, a blocking layer, a first gate insulating layer, a second gate insulating layer, an interlayer dielectric layer, a first electrode, a second electrode, a third electrode, and a fourth electrode, wherein the buffer layer is disposed on the substrate, the third gate layer and the fourth gate layer are disposed on the buffer layer at intervals, the blocking layer covers the buffer layer, the third gate layer, and the fourth gate layer, the first active layer and the second active layer are disposed on the blocking layer at intervals, the first gate insulating layer is disposed on the first active layer, the second gate insulating layer is disposed on the second active layer, the first gate layer is disposed on the first gate insulating layer, the second gate layer is disposed on the second gate insulating layer, and the interlayer dielectric layer covers the blocking layer, The first active layer, the second active layer, the first gate insulating layer, the second gate insulating layer, the first gate layer, and the second gate layer, the first electrode, the second electrode, the third electrode, and the fourth electrode are all disposed on the interlayer dielectric layer, the first electrode and the second electrode are electrically connected to the first active layer from two opposite sides of the first gate layer, respectively, and the third electrode and the fourth electrode are electrically connected to the second active layer from two opposite sides of the second gate layer, respectively.

7. The array substrate of claim 6, wherein the blocking layer comprises a first blocking layer and a second blocking layer, the first blocking layer is disposed on and covers the fourth gate layer, the first blocking layer and the third gate layer are spaced apart from each other, the second blocking layer is disposed on a side of the first blocking layer facing away from the buffer layer, and the second blocking layer covers the buffer layer, the third gate layer and the first blocking layer.

8. The array substrate of claim 6 or 7, wherein the second gate insulating layer comprises a first insulating layer and a second insulating layer, the first insulating layer is disposed on the second active layer, the second insulating layer is disposed on the first insulating layer, the second gate layer is disposed on the second insulating layer, and a thickness of the first insulating layer or the second insulating layer is greater than or equal to a thickness of the first gate insulating layer.

9. The array substrate of claim 6, wherein the third gate layer comprises a body metal layer and an extension metal layer, the body metal layer and the first active layer are both in a strip shape, the extension direction of the body metal layer is the same as the extension direction of the first active layer, the body metal layer is disposed opposite to the first active layer, the extension metal layer is in a strip shape, and the extension direction of the extension metal layer intersects with the extension direction of the body metal layer;

the first gate layer comprises a first gate action part and a second gate action part which are integrally interconnected, the first gate action part is arranged opposite to the first active layer, the orthographic projection of the second gate action part on the surface of the first active layer is positioned outside the area of the first active layer, and the second gate action part and the extension metal layer are positioned on the same side of the first active layer;

the array substrate further comprises a conductive connecting layer arranged on the interlayer dielectric layer, and the two opposite ends of the conductive connecting layer are respectively and electrically connected with the extension metal layer and the second grid action part through conductive through holes.

10. A display device comprising the array substrate according to any one of claims 1 to 9, wherein the display device has a display region and a non-display region, the driving circuit is disposed in the non-display region, and the pixel circuit is disposed in the display region.

11. A manufacturing method of an array substrate is characterized by comprising the following steps:

forming a substrate;

12. The method of manufacturing of claim 11, wherein between the step of forming a substrate and the step of forming a first active layer of a first thin film transistor and a second active layer of a second thin film transistor on the substrate, the method further comprises:

forming a third gate layer of the first thin film transistor and a fourth gate layer of the second thin film transistor on the substrate;

forming a first barrier layer so that the first barrier layer covers the fourth gate layer and the first barrier layer and the third gate layer are arranged at intervals;

forming a second barrier layer to cover the substrate, the third gate layer and the first barrier layer;

the forming a first gate layer and a second gate layer on the substrate includes:

and forming the first active layer and the second active layer on the second barrier layer, wherein the first active layer is opposite to the third gate layer, and the second active layer is opposite to the fourth gate layer.

13. The fabrication method of claim 11 or 12, wherein between the step of forming the first active layer of the first thin film transistor and the second active layer of the second thin film transistor on the substrate and the step of forming the first gate layer and the second gate layer on the substrate, the method further comprises:

forming a first gate insulating layer on the first active layer and a first insulating layer on the second active layer, the first insulating layer having a thickness greater than or equal to the first gate insulating layer;

forming a second insulation layer on the first insulation layer;

a first gate layer is formed over the first gate insulating layer, and a second gate layer is formed over the second insulating layer.