CN114512485B - Stacked nano-sheet access transistor for 4T-SRAM unit and preparation method thereof - Google Patents

Stacked nano-sheet access transistor for 4T-SRAM unit and preparation method thereof Download PDF

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CN114512485B
CN114512485B CN202210117374.6A CN202210117374A CN114512485B CN 114512485 B CN114512485 B CN 114512485B CN 202210117374 A CN202210117374 A CN 202210117374A CN 114512485 B CN114512485 B CN 114512485B
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silicon
grid
germanium sacrificial
silicon germanium
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CN114512485A (en
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李聪
李高鹏
郭增光
成善霖
游海龙
庄奕琪
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Xidian University
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    • H01L21/8232—Field-effect technology
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
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Abstract

The invention discloses a stacked nano-sheet access transistor and a preparation method thereof, which mainly solve the problem that the threshold voltage and the on-state driving capability of a device cannot be adjusted by the existing stacked nano-sheet structure. The invention can realize the adjustment of the threshold voltage and the on-state driving capability of the stacked nano-sheet structure by the double grid, has simple manufacturing process and can be used for a 4-tube static random access memory.

Description

Stacked nano-sheet access transistor for 4T-SRAM unit and preparation method thereof
Technical Field
The invention belongs to the technical field of microelectronic devices, and particularly relates to a stacked nano-sheet access transistor which can be used for a 4T-SRAM (4T-static random access memory).
Background
As integrated circuits have evolved, the feature sizes of devices have been continually shrinking. In order to alleviate a series of non-ideal effects caused by the downsizing, advanced structures such as double gate field effect transistors, fin field effect transistors, nanowire field effect transistors and the like are proposed. Such a stacked nanoplatelet structure as shown in fig. 1 is considered to be the most promising candidate device for a process node below 5nm due to excellent gate control performance and compatible process flows. However, as the feature size of the device is reduced, the problem of reliability of the device is more and more prominent, and researchers have long found that aging phenomena such as an increase in threshold voltage, a decrease in driving current and the like occur when the device is in a continuously biased state in a high temperature state, so that bias temperature instability is caused, and negative bias temperature instability occurring in PMOS is much more remarkable than positive bias temperature instability occurring in NMOS.
Currently, as shown in fig. 2, a 6-tube sram 6TSRAM cell structure widely used in a memory array is composed of 4 NMOS tubes N3, N4, N5, N6 and 2 PMOS N1, N2 tubes, where the NMOS tubes and PMOS used in the structure may be planar structures based on conventional processes or stacked nano-sheet structures based on advanced processes, but no matter which device structure is used, the circuit is affected by the instability of negative temperature bias voltage. The PMOS transistor is obviously affected by the instability of the negative bias temperature, and the threshold voltage of the PMOS transistor is easily increased under long-time use, so that the mismatch of the PMOS transistor and the NMOS transistor in the SRAM unit is caused, and the read-write stability of the SRAM unit is affected. A 4TSRAM structure based on a dual gate structure has been proposed, in which the read-write performance of an SRAM cell is improved by using feedback of front and rear gates of an access transistor of the dual gate structure, and the SRAM cell is prevented from being affected by negative bias temperature instability due to the use of only NMOS, so that the reliability of a circuit is improved. However, the adjustment of the threshold voltage and the on-state driving capability of the device by the gate cannot be realized by the existing stacked nano-sheet structure, so that the 4T-SRAM unit circuit based on the stacked nano-sheet structure cannot be realized, and the influence of the temperature bias stability on the device below 5nm becomes serious. Thus, there is a need to design a set of SRAM cell structures suitable for stacked nanoflake structures that can mitigate bias temperature instability, and the design of access transistors is a significant issue therein.
Disclosure of Invention
The invention aims at overcoming the defects of the prior art, and provides a stacked nano-sheet access transistor applied to a 4T-SRAM cell and a preparation method thereof, so as to realize adjustment of threshold voltage and on-state driving capability of a grid electrode on the device.
In order to achieve the above object, the present invention is applied to a stacked nano-sheet access transistor of a 4T-SRAM cell, comprising a substrate 1 and source and drain regions 3 located on both sides of the upper portion of the substrate, characterized in that: a conduction control area is arranged between the source region and the drain region, a plurality of stacked P-type silicon layers 2 are arranged in the conduction control area from bottom to top, isolation side walls 4 are arranged on two sides of each stacked P-type silicon layer, a gate dielectric layer 21 is covered on the surface of the P-type silicon layer between the isolation side walls, a lower grid 22 is wrapped on the lower layer of the P-type silicon layer, an upper grid 23 is wrapped on the P-type silicon layer which is not wrapped by the lower grid, and a grid isolation layer 24 is arranged between the upper grid 23 and the lower grid 22.
Further, the number of the P-type silicon layers wrapped by the lower gate is smaller than that of the P-type silicon layers wrapped by the upper gate, the work function of the gate material metal used by the lower gate is higher than that of the gate material used by the upper gate, the work function difference of the gate material used by the lower gate is more than 0.2eV, the work function of the lower gate metal is 4.6 eV-4.7 eV, and the work function of the upper gate is 4.4-4.5 eV.
Further, the substrate 1 is bulk silicon or silicon on insulator.
Further, the isolation side wall 4 is made of silicon nitride or aluminum oxide with high thermal conductivity.
Further, the gate dielectric layer 21 includes a silicon dioxide film and a hafnium dioxide film, the thickness of the silicon dioxide film is 0.6-0.7 nm, and the concentration of the hafnium dioxide film is 1.6-1.8 nm.
Further, each stacked P-type silicon layer 2 has a thickness of 5nm and a length of 10-15 nm, contains arsenic as a doping material, and has a doping concentration of 2×10 17 cm -3 ～1×10 18 cm -3 。
To achieve the above object, the present invention provides a method for preparing a stacked nanoflake access transistor applied to a 4T-SRAM cell, comprising:
1) The P-type superlattice structure 2 is vertically deposited on the substrate 1 by chemical vapor deposition:
1a) Sequentially and circularly depositing a first silicon germanium sacrificial layer 11 and a P-type silicon layer 2 on a substrate, wherein the first layer and the last deposited layer are required to be ensured to be the first silicon germanium sacrificial layer 11;
1b) Depositing a second silicon germanium sacrificial layer 12 on the finally deposited first silicon germanium sacrificial layer 11;
1c) Sequentially and circularly depositing a third silicon germanium sacrificial layer 13, a P-type silicon layer 2 and a third silicon germanium sacrificial layer 13 on the second silicon germanium sacrificial layer 12, wherein the first layer and the last deposited layer are ensured to be the third silicon germanium sacrificial layer 13;
2) Etching the two sides of the first, second and third silicon germanium sacrificial layers respectively to form grooves;
3) Depositing dielectric materials in the grooves by using high conformal deposition or chemical vapor deposition of atomic layer deposition to form isolation side walls 4;
4) Growing N-type epitaxial source-drain regions 3 on two sides of the P-type superlattice structure;
5) Etching the third silicon germanium sacrificial layer 13 to form an upper channel;
6) Silicon dioxide and hafnium oxide materials are grown on the surface of the upper channel to form an upper gate dielectric layer 21;
7) Depositing a gate metal material on the upper gate dielectric layer 21 to form an upper gate 23;
8) Etching the first silicon germanium sacrificial layer 11 to form a lower channel;
9) Silicon dioxide and hafnium oxide materials are grown on the surface of the lower channel to form a lower gate dielectric layer 21;
10 A gate metal material is deposited on the lower gate dielectric layer 21 to form a lower gate 22;
11 The second silicon germanium sacrificial layer 12 is etched away and dielectric material is deposited between them to form a gate spacer 24, completing the device fabrication.
Compared with the prior art, the invention has the following advantages:
compared with the traditional stacked nano-sheet structure, the invention adopts the upper grid electrode and the lower grid electrode to wrap the upper channel and the lower channel respectively to form the surrounding grid structure, and adopts the grid isolation layer to isolate the upper grid electrode from the lower grid electrode, so when the upper grid electrode and the lower grid electrode adopt different voltage biases, the change of the conduction capacity of the upper channel and the lower channel can be caused, and the integral threshold voltage and the on-state driving capacity of the device can be adjusted.
In addition, compared with the traditional double-gate transistor, the invention has the advantages that the structure of stacking the channels and the surrounding gate is adopted, so that higher gate coverage rate is obtained, the gate control performance is improved, and the short channel effect is relieved.
Drawings
FIG. 1 is a block diagram of a prior art conventional stacked nanoflake transistor;
FIG. 2 is a circuit diagram of a conventional 6-pipe SRAM cell;
FIG. 3 is a schematic diagram of a stacked nanoflake access transistor structure of the present invention;
FIG. 4 is a flow chart of the present invention for preparing a stacked nanoflake access transistor;
FIG. 5 is a schematic flow chart of the process for preparing a stacked nano-sheet access transistor according to the present invention
Detailed Description
Embodiments of the present invention will now be described more fully hereinafter with reference to the accompanying drawings.
Referring to fig. 3, the stacked nanoflake access transistor for a 4T-SRAM cell of the present invention comprises a substrate 1 and source and drain regions 3 located on both sides of the upper portion of the substrate, and is characterized in that: a conduction control area is arranged between the source region and the drain region, a plurality of stacked P-type silicon layers 2 are arranged in the conduction control area from bottom to top, isolation side walls 4 are arranged on two sides of each stacked P-type silicon layer, a gate dielectric layer 21 is covered on the surface of the P-type silicon layer between the isolation side walls, a lower grid 22 is wrapped on the lower layer of the P-type silicon layer, an upper grid 23 is wrapped on the P-type silicon layer which is not wrapped by the lower grid, and a grid isolation layer 24 is arranged between the upper grid 23 and the lower grid 22. The number of the P-type silicon layers wrapped by the lower grid is smaller than that wrapped by the upper grid, and the work function of the metal of the grid material used by the lower grid is higher than that of the metal of the grid material used by the upper grid, and the work function difference is more than 0.2 eV. The substrate 1 is made of bulk silicon or on an insulating layerSilicon. The isolation side wall adopts silicon nitride or aluminum oxide with high heat conductivity. The gate dielectric layer 21 comprises a silicon dioxide film and a hafnium dioxide film, wherein the thickness of the silicon dioxide film is 0.6-0.7 nm, and the concentration of the hafnium dioxide film is 1.6-1.8 nm. The thickness of each stacked P-type silicon layer is 5nm, the length is 10-15 nm, the doping material is arsenic, and the doping concentration is 2 multiplied by 10 17 cm -3 ～1×10 18 cm -3 。
Referring to fig. 4 and 5, the method of preparing the stacked nanoflake access transistor of fig. 3 according to the present invention is given in three examples below.
In example 1, the work function of the lower gate metal is 4.6eV, the work function of the upper gate metal is 4.4eV, the substrate is bulk silicon, and the isolation sidewall is silicon nitride. The thickness of the silicon dioxide film is 0.7nm, the thickness of the hafnium dioxide film is 1.6nm, the length of the P-type silicon layer is 10nm, and the doping concentration is 2 multiplied by 10 17 cm -3 Is connected to the transistor.
In step 1, a P-type superlattice structure 2 is vertically deposited on a bulk silicon substrate 1 by chemical vapor deposition, as shown in fig. 5 (a).
1.1 Sequentially and circularly depositing a first silicon germanium sacrificial layer 11 and a P-type silicon layer 2 on the bulk silicon substrate 1, wherein the first layer and the last deposited layer are required to be ensured to be the first silicon germanium sacrificial layer 11;
1.2 A second silicon germanium sacrificial layer 12 is deposited on the last deposited first silicon germanium sacrificial layer 11;
1.3 Sequentially and circularly depositing a third silicon germanium sacrificial layer 13, a P-type silicon layer 2 and a third silicon germanium sacrificial layer 13 on the second silicon germanium sacrificial layer 12, wherein the first layer and the last deposited layer are the third silicon germanium sacrificial layer 13, the final length is 10nm, the thickness is 63nm, and the arsenic impurity concentration is 2 multiplied by 10 17 cm -3 P-type superlattice structure of (c).
And 2, forming a groove.
Etching is sequentially performed on two sides of the first silicon germanium sacrificial layer 11, two sides of the second silicon germanium sacrificial layer 12 and two sides of the third silicon germanium layer 13, and the etching widths of the first silicon germanium sacrificial layer, the second silicon germanium sacrificial layer and the third silicon germanium sacrificial layer are the same, so that two sides of the first silicon germanium sacrificial layer, the second silicon germanium sacrificial layer and the third silicon germanium sacrificial layer are recessed relative to the P-type silicon layer to form grooves.
And 3, forming a silicon nitride isolation side wall 4, as shown in fig. 5 (b).
And uniformly depositing silicon nitride dielectric materials in grooves on two sides of the P-type superlattice structure under the process condition of high conformality by using an atomic layer deposition method to form the silicon nitride isolation side wall 4.
Step 4, an N-type source/drain region 3 is fabricated, as shown in fig. 5 (c).
4.1 Growing epitaxial silicon crystals on two sides of the P-type silicon layer 2 to obtain a plurality of initial silicon extension areas;
4.2 Continuing to grow silicon crystals in the initial silicon expansion areas and communicating the silicon crystals until the silicon crystals are contacted with the bulk silicon substrate to form source and drain expansion areas;
4.3 N-type doping is carried out on the source-drain extension region, chemical mechanical polishing is carried out on the doped source-drain extension region, so that the height of the doped source-drain extension region is flush with the P-type superlattice structure forming the silicon nitride isolation side wall, and an N-type source-drain region 3 is formed.
Step 5, forming an upper channel, as shown in fig. 5 (d).
The third silicon germanium sacrificial layer 13 is selectively etched so that P-type silicon layers above the second silicon germanium sacrificial layer 12 are completely exposed and form a gap therebetween without affecting the first silicon germanium sacrificial layer 11 and the second silicon germanium sacrificial layer 12, thereby forming an upper channel.
And 6, depositing an upper gate dielectric layer 21 a.
6.1 Growing a silicon dioxide dielectric material on the surface of the exposed upper layer channel to form a silicon dioxide film with the thickness of 0.7nm;
6.2 A hafnium oxide dielectric material is deposited on the silicon dioxide film, the deposition thickness is 1.6nm, a hafnium oxide film which completely covers the silicon dioxide film is formed, and the deposition of the upper gate dielectric layer 21a is completed.
In step 7, an upper gate 23 is formed as shown in fig. 5 (e).
7.1 Titanium nitride material is deposited in the gap formed by the surface of the upper gate dielectric layer 21a and the third silicon germanium sacrificial layer 13 after selective etching and is mutually communicated to form a titanium nitride grid wrapping the upper gate dielectric layer 21a and an upper channel;
7.2 Polishing the top of the titanium nitride grid electrode by chemical mechanical polishing to enable the top of the titanium nitride grid electrode to be flush with the top of the N-type source drain region;
7.3 The work function of the titanium nitride gate is adjusted to be 4.4eV, and the upper layer gate 23 is manufactured.
Step 8, forming a lower channel, as shown in fig. 5 (f).
The first silicon germanium sacrificial layer 11 is selectively etched without affecting the second silicon germanium sacrificial layer 12 so that the P-type silicon layers under the second silicon germanium sacrificial layer 12 are completely exposed and form gaps therebetween, thereby forming an underlying channel.
And 9, depositing a lower gate dielectric layer 21 b.
9.1 A silicon dioxide dielectric material grows on the surface of the exposed lower-layer channel to form a silicon dioxide film, and the thickness of the film is 0.7nm;
9.2 A hafnium oxide dielectric material is deposited on the silicon dioxide film, the deposition thickness is 1.6nm, a hafnium oxide film which completely covers the silicon dioxide film is formed, and the deposition of the lower gate dielectric layer 21a is completed.
In step 10, a lower gate 22 is formed as shown in fig. 5 (g).
10.1 Titanium nitride material is deposited on the surface of the lower gate dielectric layer 21b to fill the gap formed by the selective etching of the first silicon germanium sacrificial layer 11 and is communicated with each other to form a titanium nitride gate wrapping the lower gate dielectric layer and the lower channel;
10.2 The titanium nitride gate is doped to adjust its work function to 4.6eV, thereby completing the formation of the lower gate 21.
In step 11, a gate spacer 24 is formed as shown in fig. 5 (h).
11.1 Etching the second silicon germanium sacrificial layer 12 to form a gap between the upper gate electrode 23 and the lower gate electrode 22;
11.2 Silicon nitride dielectric material is deposited in the gap to form the gate spacer 24, completing the device fabrication.
Example 2 preparation of lower Gate Metal work function of 4.7eV, upper GateThe work function of the metal is 4.5eV, the material used for the substrate is silicon on an insulating layer, the isolation side wall is made of aluminum oxide material, the thickness of a silicon dioxide film is 0.7nm, the thickness of a hafnium dioxide film is 1.6nm, the length of a P-type silicon layer is 15nm, and the doping concentration is 1 multiplied by 10 18 cm -3 Is connected to the transistor.
In a first step, a P-type superlattice structure 2 is vertically deposited on a bulk silicon substrate 1 by chemical vapor deposition, as shown in fig. 5 (a).
Firstly, sequentially and circularly depositing a first silicon germanium sacrificial layer 11 and a P-type silicon layer 2 on a silicon substrate 1 on an insulating layer, wherein the first layer and the last deposited layer are required to be ensured to be the first silicon germanium sacrificial layer 11;
next, depositing a second silicon germanium sacrificial layer 12 on the finally deposited first silicon germanium sacrificial layer 11;
finally, a third silicon germanium sacrificial layer 13, a P-type silicon layer 2 and a third silicon germanium sacrificial layer 13 are sequentially and circularly deposited on the second silicon germanium sacrificial layer 12, the first layer and the finally deposited layer level are ensured to be the third silicon germanium sacrificial layer 13, the length is 15nm, the thickness is 63nm, and the arsenic impurity concentration is 1 multiplied by 10 18 cm -3 P-type superlattice structure of (c).
And step two, forming a groove.
The specific implementation of this step is the same as step 2 of example 1.
Step three, forming an alumina isolation sidewall 4, as shown in fig. 5 (b).
And uniformly depositing alumina dielectric materials in grooves on two sides of the P-type superlattice structure by using chemical vapor deposition under the process condition that the deposition rate is more than 2nm/min at 150 ℃ to form the alumina isolation side wall 4.
Step four, an N-type source-drain region 3 is fabricated, as shown in fig. 5 (c).
The specific implementation of this step is the same as step 4 of example 1.
Step five, forming an upper channel as shown in fig. 5 (d).
The specific implementation of this step is the same as step 5 of embodiment 1.
And step six, depositing an upper gate dielectric layer 21 a.
Firstly, growing a silicon dioxide dielectric material on the surface of the exposed upper channel to form a silicon dioxide film with the thickness of 0.7nm; and depositing a hafnium oxide dielectric material with the thickness of 1.6nm on the silicon dioxide film to form a hafnium oxide film which completely covers the silicon dioxide film, thereby completing the deposition of the upper gate dielectric layer 21 a.
Step seven, an upper gate 23 is formed as shown in fig. 5 (e).
Firstly, depositing titanium nitride materials in gaps formed by the surface of the upper gate dielectric layer 21a and the third silicon germanium sacrificial layer 13 after selective etching, and forming titanium nitride grids wrapping the upper gate dielectric layer 21a and an upper channel by mutual communication;
and then polishing the top of the titanium nitride grid electrode by chemical mechanical polishing to enable the top of the titanium nitride grid electrode to be flush with the top of the N-type source drain region, finally doping the titanium nitride grid electrode, adjusting the work function of the titanium nitride grid electrode to be 4.5eV, and completing the manufacture of the upper grid electrode 23.
Step eight, forming a lower channel, as shown in fig. 5 (f).
The specific implementation of this step is the same as step 8 of embodiment 1.
And step nine, depositing a lower gate dielectric layer 21 b.
Firstly, growing a silicon dioxide dielectric material on the surface of the exposed lower-layer channel to form a silicon dioxide film with the thickness of 0.7nm; and depositing a hafnium oxide dielectric material with the thickness of 1.6nm on the silicon dioxide film to form a hafnium oxide film which completely covers the silicon dioxide film, thereby completing the deposition of the lower gate dielectric layer 21 a.
In step ten, the lower gate 22 is formed as shown in fig. 5 (g).
Firstly, depositing a titanium nitride material on the surface of the lower gate dielectric layer 21b to fill gaps formed by the first silicon germanium sacrificial layer 11 after selective etching, and mutually communicating to form a titanium nitride gate wrapping the lower gate dielectric layer and a lower channel; then, the titanium nitride gate was doped to adjust its work function to 4.7eV, thereby completing the formation of the lower gate 21.
In step eleven, a gate spacer 24 is formed as shown in fig. 5 (h).
The specific implementation of this step is the same as step 11 of embodiment 1.
Example 3 preparation of lower layer Gate Metal work function 4.6eV, upper layer Gate Metal work function 4.4eV, substrate material is insulating layer upper silicon, isolation side wall is silicon nitride material, silicon dioxide film thickness is 0.6nm, hafnium dioxide film thickness is 1.8nm, P-type silicon layer length is 15nm, doping concentration is 1×10 18 cm -3 Is connected to the transistor.
Step a, a P-type superlattice structure 2 is vertically deposited on a bulk silicon substrate 1 by chemical vapor deposition, as shown in fig. 5 (a).
A1 Sequentially and circularly depositing a first silicon germanium sacrificial layer 11 and a P-type silicon layer 2 on the silicon substrate 1 on the insulating layer, wherein the first layer and the last deposited layer are required to be ensured to be the first silicon germanium sacrificial layer 11;
a2 A second silicon germanium sacrificial layer 12 is deposited on the last deposited first silicon germanium sacrificial layer 11;
a3 Sequentially and circularly depositing a third silicon germanium sacrificial layer 13, a P-type silicon layer 2 and a third silicon germanium sacrificial layer 13 on the second silicon germanium sacrificial layer 12, wherein the first layer and the last deposited layer are the third silicon germanium sacrificial layer 13, the final length is 15nm, the thickness is 63nm, and the arsenic impurity concentration is 1 multiplied by 10 18 cm -3 P-type superlattice structure of (c).
And B, forming a groove.
The specific implementation of this step is the same as step 2 of example 1.
And C, forming a silicon nitride isolation side wall 4, as shown in fig. 5 (b).
And uniformly depositing silicon nitride dielectric materials in grooves on two sides of the P-type superlattice structure by using chemical vapor deposition under the process condition that the deposition rate is more than 2nm/min at 150 ℃ to form the silicon nitride isolation side wall 4.
Step D, an N-type source/drain region 3 is formed, as shown in FIG. 5 (c).
The specific implementation of this step is the same as step 4 of example 1.
Step E, forming an upper channel as shown in FIG. 5 (d).
The specific implementation of this step is the same as step 5 of embodiment 1.
And F, depositing an upper gate dielectric layer 21 a.
F1 Growing a silicon dioxide dielectric material on the surface of the exposed upper channel to form a silicon dioxide film with the thickness of 0.6 nm;
f2 A hafnium oxide dielectric material with the thickness of 1.8nm is deposited on the silicon dioxide film, the thickness of 1.8nm is deposited, a hafnium oxide film which completely covers the silicon dioxide film is formed, and the deposition of the upper gate dielectric layer 21a is completed.
In step G, an upper gate 23 is formed as shown in fig. 5 (e).
G1 Titanium nitride material is deposited in the gap formed by the surface of the upper gate dielectric layer 21a and the third silicon germanium sacrificial layer 13 after selective etching and is mutually communicated to form a titanium nitride grid wrapping the upper gate dielectric layer 21a and an upper channel;
g2 Polishing the top of the titanium nitride grid electrode by chemical mechanical polishing to enable the top of the titanium nitride grid electrode to be flush with the top of the N-type source drain region;
g3 The work function of the titanium nitride gate is adjusted to be 4.4eV, and the upper layer gate 23 is manufactured.
Step H, forming a lower layer channel, as shown in fig. 5 (f).
The specific implementation of this step is the same as step 8 of embodiment 1.
And step I, depositing a lower gate dielectric layer 21 b.
I1 Growing a silicon dioxide dielectric material on the surface of the exposed lower-layer channel to form a silicon dioxide film with the thickness of 0.6 nm;
i2 A hafnium oxide dielectric material with the thickness of 1.8nm is deposited on the silicon dioxide film to form a hafnium oxide film which completely covers the silicon dioxide film, and the deposition of the lower gate dielectric layer 21a is completed.
In step J, a lower gate 22 is formed as shown in FIG. 5 (g).
J1 Titanium nitride material is deposited on the surface of the lower gate dielectric layer 21b to fill the gap formed by the selective etching of the first silicon germanium sacrificial layer 11 and is communicated with each other to form a titanium nitride gate wrapping the lower gate dielectric layer and the lower channel;
j2 The titanium nitride gate is doped to adjust its work function to 4.6eV, thereby completing the formation of the lower gate 21.
In step K, a gate spacer 24 is formed as shown in fig. 5 (h).
The specific implementation of this step is the same as step 11 of embodiment 1.
The above description is only three specific examples of the invention and does not constitute any limitation of the invention, it will be apparent to those skilled in the art that various modifications and changes in form and details may be made without departing from the principles, construction of the invention, but these modifications and changes based on the idea of the invention are still within the scope of the claims of the invention.

Claims (8)

1. A method of manufacturing a stacked nanoflake access transistor for a 4T-SRAM cell, comprising:
1) And vertically depositing a P-type superlattice structure (2) on the substrate (1) by adopting chemical vapor deposition:
1a) Sequentially and circularly depositing a first silicon germanium sacrificial layer (11) and a P-type silicon layer (2) on a substrate, and ensuring that the first layer and the last deposited layer are the first silicon germanium sacrificial layer (11);
1b) Depositing a second silicon germanium sacrificial layer (12) on the finally deposited first silicon germanium sacrificial layer (11);
1c) Sequentially and circularly depositing a third silicon germanium sacrificial layer (13), a P-type silicon layer (2) and the third silicon germanium sacrificial layer (13) on the second silicon germanium sacrificial layer (12), and ensuring that the first layer and the last deposited layer are the third silicon germanium sacrificial layer (13);
2) Etching the two sides of the first, second and third silicon germanium sacrificial layers respectively to form grooves;
3) Depositing dielectric materials in the grooves by using high-conformal deposition or chemical vapor deposition of atomic layer deposition to form isolation side walls (4);
4) Growing N-type epitaxial source-drain regions (3) on two sides of the P-type superlattice structure;
5) Etching the third silicon germanium sacrificial layer (13) to form an upper layer channel;
6) Silicon dioxide and hafnium dioxide materials are grown on the surface of the upper channel to form an upper gate dielectric layer (21);
7) Depositing a gate metal material on the upper gate dielectric layer (21) to form an upper gate (23);
8) Etching the first silicon germanium sacrificial layer (11) to form a lower layer channel;
9) Silicon dioxide and hafnium oxide materials are grown on the surface of the lower channel to form a lower gate dielectric layer (21);
10 Depositing a gate metal material on the lower gate dielectric layer (21) to form a lower gate (22);
11 Etching away the second silicon germanium sacrificial layer (12) and depositing a dielectric material therebetween to form a gate spacer (24) to complete device fabrication.
2. The method according to claim 1, wherein the silicon dioxide and hafnium oxide materials are grown on the channel surface in 6) or 9), wherein the silicon dioxide material is grown around the P-type silicon layer (2) to form a thin film, and then the hafnium oxide is deposited around the silicon dioxide.
3. The method of manufacturing according to claim 1, characterized in that: the device structurally comprises a substrate (1) and source and drain regions (3) positioned on two sides of the upper part of the substrate; be equipped with between the source drain region and switch on the control region, this switch on the control region from bottom to top and be provided with a plurality of P type silicon layer (2) of piling up, every P type silicon layer both sides of piling up are isolation side wall (4), P type silicon layer surface between the isolation side wall is covered and is had bars dielectric layer (21), the lower floor parcel of P type silicon layer has lower floor grid (22), the parcel has upper grid (23) on the P type silicon layer that is not wrapped up by lower floor grid, upper grid (23) are equipped with bars isolation layer (24) with lower floor grid (22).
4. A method according to claim 3, characterized in that: the number of the P-type silicon layers (2) wrapped by the lower grid is smaller than that of the P-type silicon layers (2) wrapped by the upper grid, the work function of the grid material metal used by the lower grid is higher than that of the grid material used by the upper grid, the work function difference of the grid material used by the lower grid is more than 0.2eV, the work function of the lower grid metal is 4.6 eV-4.7 eV, and the work function of the upper grid is 4.4-4.5 eV.
5. A method according to claim 3, characterized in that: the substrate (1) is made of bulk silicon or silicon on insulator.
6. A method according to claim 3, characterized in that: the isolation side wall (4) is made of silicon nitride or aluminum oxide.
7. A method according to claim 3, characterized in that: the thickness of each stacked P-type silicon layer is 5nm, the length is 10-15 nm, the doping material is arsenic, and the doping concentration is 2 multiplied by 10 17 cm -3 ～1×10 18 cm -3 。
8. A method according to claim 3, characterized in that: the gate dielectric layer comprises a silicon dioxide film and a hafnium dioxide film, wherein the thickness of the silicon dioxide film is 0.6-0.7 nm, and the thickness of the hafnium dioxide film is 1.6-1.8 nm.
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112736141A (en) * 2020-12-17 2021-04-30 西安国微半导体有限公司 Nano-sheet transistor with heterogeneous gate dielectric and preparation method
CN113690238A (en) * 2021-07-27 2021-11-23 西安电子科技大学重庆集成电路创新研究院 Integrated nanosheet structure, SRAM unit and preparation method thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112736141A (en) * 2020-12-17 2021-04-30 西安国微半导体有限公司 Nano-sheet transistor with heterogeneous gate dielectric and preparation method
CN113690238A (en) * 2021-07-27 2021-11-23 西安电子科技大学重庆集成电路创新研究院 Integrated nanosheet structure, SRAM unit and preparation method thereof

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