CN114510450A - Accelerated calculation method and device of encryption algorithm and array unit operator system - Google Patents
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Abstract
The invention provides an accelerated computing method and device of an encryption algorithm and an array unit operator system, which relate to the technical field of encryption and are applied to a reconfigurable computing array; the reconfigurable computing array comprises a plurality of operators; the method comprises the following steps: determining an operator calculation period according to a preset processing time sequence; presetting a processing time sequence for determining the calculation process of an operator; determining an array unit based on the input byte number of the encryption algorithm; in the operator calculation period, operator dynamic calculation is carried out based on the array units so as to carry out accelerated calculation on the encryption algorithm. The invention can improve the calculation speed of the encryption algorithm, balance the calculation power consumption and improve the anti-attack capability during encryption calculation.
Description
Technical Field
The invention relates to the technical field of encryption, in particular to an accelerated calculation method and device of an encryption algorithm and an array unit operator system.
Background
With the development of informatization and networking, the security of information gets more and more attention. A complete, advanced information system does not take into account the application of information security techniques.
The RSA cryptosystem is a public cryptosystem, can be used for encryption/decryption, and can also be used for signature/signature verification, and is widely applied to various social fields, such as smart cards, bank password cards, and the like, and improves security quality for signing public keys of users, issuing public keys, issuing certificates, managing certificates, and the like. The modular multiplication operation is a very important step in the RSA algorithm, and a common modular multiplication implementation method adopts the montgomery algorithm, however, with the development of side channel attack, the algorithm has high power consumption and is easily subjected to simple power consumption attack, differential power consumption attack, fault attack and the like.
But with the development of side channel attacks such as time analysis attacks, power consumption analysis attacks, electromagnetic radiation analysis attacks, fault injection analysis attacks, and the like. The side channel information of the cryptographic algorithm is analyzed, and the side channel information comprises the running time, power consumption, electromagnetic radiation, error results and the like of the cryptographic operation, so that the decryption of the cryptographic algorithm key information is realized. For example, simple power consumption attack, a power consumption trace curve is obtained by sampling the power consumption condition of a component when the cryptographic component runs, and then what operations the cryptographic module performs in a specific time period is guessed through curve analysis, and parameters involved in the operations.
The modular multiplication operation is a very important step in the RSA algorithm, and a common modular multiplication implementation method adopts the montgomery algorithm, has high power consumption, and is easily subjected to simple power consumption attack, differential power consumption attack, fault attack and the like.
Disclosure of Invention
The invention aims to provide an accelerated calculation method and device for an encryption algorithm and an array unit operator system, which can improve the calculation speed of the encryption algorithm, balance the calculation power consumption and improve the anti-attack capability during encryption calculation.
In a first aspect, the invention provides an accelerated computing method of an encryption algorithm, which is applied to a reconfigurable computing array; the reconfigurable computing array comprises a plurality of operators; the method comprises the following steps: determining an operator calculation period according to a preset processing time sequence; presetting a processing time sequence for determining the calculation process of an operator; determining an array unit based on the input byte number of the encryption algorithm; in the operator calculation period, operator dynamic calculation is carried out based on the array units so as to carry out accelerated calculation on the encryption algorithm.
In an optional embodiment, the step of determining the calculation period of the operator according to a preset processing time sequence includes: determining a calculation period according to the number of operators of the reconfigurable calculation array; wherein, the calculation period corresponds to the number of operators; the number of operators performing the calculation in each calculation cycle is different.
In an optional implementation manner, in each calculation period in which calculation is performed in sequence, the number of operators for performing encryption algorithm calculation is increased according to a preset increment; the preset increment is at least one operator increment.
In an alternative embodiment, the method further comprises: the switching timing of the byte processing is determined based on the number of input bytes of the encryption algorithm and the array unit.
In an optional implementation manner, when the number of array units calculated in the operator calculation period is one, the step of performing operator dynamic calculation based on the array units in the operator calculation period includes: in the calculation period, after the current operator receives the enabling signal, an encryption algorithm is executed based on the input encryption initial value, and the operator encryption value is obtained.
In an optional implementation manner, when the number of the array units in the operator calculation period is at least two, the encryption intermediate value calculated by the previous operator is used as the encryption initial value of the current operator; the step of dynamically calculating an operator based on the array unit in the operator calculation cycle includes: determining an input enabling signal of the current operator based on the enabling signal output by the last operator; and calculating the encryption intermediate value of the current operator based on the input enabling signal and the encryption initial value until all operators are completely calculated.
In a second aspect, the invention provides an accelerated computing device of an encryption algorithm, which is applied to a reconfigurable computing array; the reconfigurable computing array comprises a plurality of operators; the device comprises:
the calculation period determining module is used for determining an operator calculation period according to a preset processing time sequence; presetting a processing time sequence for determining the calculation process of an operator; an array unit determination module for determining an array unit based on the number of input bytes of the encryption algorithm; and the accelerated calculation module is used for carrying out operator dynamic calculation based on the array unit in the operator calculation period so as to carry out accelerated calculation on the encryption algorithm.
In a third aspect, the present invention provides an array unit operator system, where the array unit operator system includes a plurality of array unit operator structures connected in sequence; wherein the array unit operator structure is used to perform the accelerated computation method of the encryption algorithm of any of the preceding embodiments.
In a fourth aspect, the present invention provides an electronic device comprising a processor and a memory, the memory storing machine executable instructions capable of being executed by the processor, the processor executing the machine executable instructions to implement the method of accelerated computing of an encryption algorithm of any one of the preceding embodiments.
In a fifth aspect, the present invention provides a machine-readable storage medium having stored thereon machine-executable instructions which, when invoked and executed by a processor, cause the processor to carry out a method of accelerated computing of an encryption algorithm according to any one of the preceding embodiments.
The accelerated calculation method of the encryption algorithm is applied to a reconfigurable calculation array, wherein the reconfigurable calculation array comprises a plurality of operators, the method firstly determines an operator calculation period according to a preset processing time sequence (used for determining the calculation process of the operators), then determines an array unit based on the input byte number of the encryption algorithm, and further performs dynamic calculation of the operators based on the array unit in the operator calculation period so as to perform accelerated calculation on the encryption algorithm. In the method, the operator calculation period is determined through the preset processing time sequence, the array unit is determined through the input byte number of the encryption algorithm, and then the operator dynamic calculation is carried out based on the array unit in the determined operator calculation period, so that the generation of peak power consumption during the multiplication of the large number and the large number can be avoided, and the anti-attack capability is improved. Therefore, the embodiment of the invention can improve the calculation speed of the encryption algorithm, balance the calculation power consumption and improve the anti-attack capability during encryption calculation.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic flowchart of an accelerated computing method for an encryption algorithm according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a computation timing sequence according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a switching sequence according to an embodiment of the present invention;
FIG. 4 is a schematic structural diagram of an accelerated computing device for an encryption algorithm according to an embodiment of the present invention;
FIG. 5 is a diagram illustrating an array unit operator structure according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
Some embodiments of the invention are described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.
For convenience of understanding, a detailed description is first given of an accelerated computing method of an encryption algorithm provided in an embodiment of the present invention, where the method is applied to a reconfigurable computing array, where the reconfigurable computing array includes a plurality of operators, and the plurality of operators are arranged according to a preset arrangement order, where the preset arrangement order may be set according to a design requirement of a circuit board, such as requirements of saving space and wiring; the setting may also be performed according to actual requirements, such as the size of the actual calculation amount, the required calculation efficiency, and the like, and is not limited specifically herein.
Referring to fig. 1, a flow diagram of an accelerated computing method of an encryption algorithm is shown, which mainly includes the following steps S102 to S106:
and S102, determining an operator calculation period according to a preset processing time sequence.
Since the encryption algorithm is calculated by using the plurality of operators in the reconfigurable computing array, the preset processing time sequence is used for determining the computing process of the operators, that is, the processing time sequence of the plurality of operators when the encryption algorithm is executed is determined by the preset processing time sequence. In order to avoid peak power consumption when the encryption algorithm is executed and the encryption algorithm is not easy to break, the operator calculation period is determined, and a plurality of operators are calculated (including effective calculation and ineffective calculation) in each operator calculation period, so that the operator power consumption is stable and is not easy to break during calculation.
In step S104, an array unit is determined based on the number of input bytes of the encryption algorithm.
In one embodiment, the encryption algorithm may be a Montgomery modulo reduction algorithm. This embodiment is adopted based on the mode 28The input of the Montgomery modular reduction algorithm is X and Y respectively, wherein,
X、Y<n, N is an odd number; the output of the algorithm is X Y rho-1mod N. Each operator completesThe minimum time required for calculation of Y, N corresponding to X bytes is Y _ LEN/32 cycles, and in order to guarantee the utilization rate of operators, the number of array elements adopted in the embodiment is less than Y _ LEN/32.
And step S106, in the operator calculation period, carrying out operator dynamic calculation based on the array unit so as to carry out accelerated calculation on the encryption algorithm.
In one embodiment, the operator calculation period may be generally plural, and the number of array elements of different operator calculation periods may be different. For ease of understanding, for example, the number of array elements is 8: the first operator calculation period can adopt a first operator to carry out calculation, the second period adopts the first operator and the second operator to carry out calculation in sequence (wherein, the calculation result output of the first operator is the calculation input of the second operator), and the third period adopts the first operator, the second operator and the third operator to carry out calculation in sequence (the calculation mode is the same as the second period) … … until the eighth period adopts eight operators to carry out calculation in sequence. After the 8 operator calculation cycles are executed, all 8 unit arrays (namely operators) are calculated, namely, operator dynamic calculation is carried out.
According to the accelerated calculation method of the encryption algorithm, provided by the embodiment of the invention, the operator calculation period is determined through the preset processing time sequence, the array unit is determined through the input byte number of the encryption algorithm, and then the operator dynamic calculation is carried out based on the array unit in the determined operator calculation period, so that the generation of the large digital-analog multiplication time peak power consumption can be avoided, and the anti-attack capability is improved. Therefore, the embodiment of the invention can improve the calculation speed of the encryption algorithm, balance the calculation power consumption and improve the anti-attack capability during encryption calculation.
The encryption algorithm adopted in this embodiment is Montgomery (Montgomery) algorithm, and in specific implementation, the encryption algorithm may be selected based on modulo 28Compared with the Montgomery modular reduction algorithm based on the mode 2, the Montgomery modular reduction algorithm has the performance improved by 8 times. For ease of understanding, the algorithm will first be described, with the algorithm improvement expression as follows:
inputting:
X,Y<n, N is an odd number
And (3) outputting: x Y rho-1mod N
X can be split into k first and is performed by:
1.r[0]＝0；n＝N[7:0]；
2. calculating n _ inv ═ - (n)-1％28)
3.for i＝0to k-1do
a)t＝r[i]％28
b)u＝(t*n_inv+xi*Y0*n_inv)％28
c)r[i+1]＝(r[i]+xi*Y+u*N)/28
4.if r[k]>N,r[k]-N,else return r[k]
Further, we divide Y and N into units of 32 bits for calculation, in this embodiment, it is preferable to use 32 bits as a basic unit, so that better area efficiency and good timing can be obtained, that is, u and r are calculated within 1 cycle at a higher frequency, where u and r are intermediate variables of encryption calculation.
Y can be split into s yj unit splices, that is:
Y＝y0+y1*232+y2*232*232+…
＝y0+y1*232*1+y2*232*2+…ys*232*s
N＝n0+n1*232+n2*232*232+…
＝n0+n1*232*1+n2*232*2+…ns*232*s
thus, the above calculation can be expanded as follows:
1.r[0][0]＝0；n＝N[7:0]；
2. calculating n _ inv ═ - (n)-1％28)
3.for i＝0to m-1do
a)for j＝0to s-1do
i.t＝r[i][0]％28
ii.u＝(t*n_inv+xi*Y0*n_inv)％28
iii.v[i+1][j+1]＝(r[i][j]+u*nj+1+xi*yj+1+w[i][j])
iv.w[i+1][j+1]＝v[i+1][j+1]/232
v.r[i+1][j+1]＝(v[i+1][j+1]+c[i][j+1])/28
vi.c[i+1][j+1]＝v[i+1][j+1]/28
4.if r[m]>N,r[m]-N,else return r[m]
In order to accelerate the computation in the expression, the embodiment implements the expression by adopting an operator array (that is, a reconfigurable computation array), wherein the reconfigurable computation array comprises a plurality of operators, different operators spatially expand i rows, and different clock cycles temporally expand j columns, so that a plurality of operators simultaneously perform parallel computation to achieve the purpose of acceleration. The timing design is as shown in fig. 2, in an embodiment, a calculation period may be determined according to the number of operators of the reconfigurable calculation array, where the calculation period corresponds to the number of operators, and the number of operators performing calculation in each calculation period is different. For example, in each calculation cycle in which calculation is performed sequentially, the number of operators performing calculation of the encryption algorithm may be increased by a preset increment, where the preset increment is at least one operator increment. For ease of understanding, an example is provided in connection with the timing diagram shown in FIG. 2:
cycle 0: all operators are idle;
cycle 1: the 1 st operator PE1 receives the enable signal and receives the x input data (the 1 st byte of x), starts the calculation work, and calculates the u value;
cycle 2: the 1 st operator PE1 receives input data (1 st word) of y and n, calculates to obtain a result r [1] [1], registers a calculation carry w [1] [1] by using a register (as an input carry calculated by the 2 nd word of y and n), sends byte0 and the calculation carry of r [1] [1] and r [1] [1] to the next operator PE2, and outputs an enable signal PE1_ EN _ O; the 2 nd operator receives the enabling signal output by the 1 st operator, starts working, receives x input data (the 2 nd byte of x), and calculates a u value;
cycle 3: the 1 st operator PE1 receives input data (2 nd word) of y and n, calculates to obtain a result r [1] [2], registers a calculation carry w [1] [2] by using a register (as an input carry calculated by the 3 rd word of y and n), sends byte0 of r [1] [2] and the calculation carry to the next operator PE2, and outputs an enable signal PE1_ EN _ O; the 2 nd operator PE2 receives the input data (1 st word) of y and n, calculates to obtain a result r 2 < 1 >, registers the calculation carry w 2 < 1 > by using a register (as the input carry calculated by the 2 nd word of y and n), sends byte0 of r 2 < 1 > and the calculation carry to the next operator PE3, and outputs an enable signal PE2_ EN _ O; the 3 rd operator receives the enabling signal output by the 2 nd operator, starts working, receives x input data (the 3 rd byte of x), and calculates a u value;
and repeating the steps until all the operators are calculated, and finishing the dynamic calculation of the operators.
In the above calculation, the switching timing of byte processing may be determined based on the input byte number and the number of array units of the encryption algorithm, such as that in fig. 2, after the XIN _ B1 (the first byte of X) of the first operator PE1_ XIN _ I is processed in the first cycle1, and so on, the XIN _ B2 (the second byte of X) of the second operator PE2_ XIN _ I is processed in the second cycle, and so on, the switching timing of byte processing by multiple operators may be obtained.
In order to reduce the number of computing units and the logic area of a chip, each item of i in the expression does not need to be expanded and is computed by different operators, and the number of array unit operators can be smaller than the maximum length of X bytes/8. The minimum time required by a single operator to complete the calculation of Y, N corresponding to each X byte is Y _ LEN/32 cycles, and in order to guarantee the utilization rate of the operator, the number of array elements adopted in the embodiment is smaller than Y _ LEN/32.
For ease of understanding, taking the number of array cells as k as an example, the byte switching timing of X is shown in FIG. 3:
cycle 0: all operators are idle;
cycle 1: operator 1 receives operator enable signal and x input byte 1, and starts working;
cycle 2: operator 2 receives operator enable signal and x input 2 nd byte, starts working;
……
s +1 th cycle: the operator 1 completes all word calculations of Y and N;
s +2 th cycle: operator 1 is idle; the operator 2 completes all word calculations of Y and N;
s +3 th cycle: operator 1 receives operator enable signal and x input k +1 byte, starts working; operator 2 is idle;
s +4 th cycle: and the operator 2 receives the operator enabling signal and the (k + 2) th byte of the x input, starts working until all operators are switched in a time sequence.
Further, PE1_ YIN/NIN _ I is processed in subsequent cycles cycle2, cycle3, and cycle4 … …, and the output enable signal PE1_ EN _ O of the first operator PE1_ XIN _ I is the same as the input enable signal PE2_ EN _ I of the second operator PE2_ XIN _ I, that is, the output enable signal PE1_ EN _ O of the first operator PE1_ XIN _ I is the input enable signal of the second operator PE2_ XIN _ I, and so on until all operators.
In specific implementation, when the number of array units calculated in an operator calculation cycle is one, that is, when the array units are in the first cycle, after a current operator (that is, a first operator) receives an enable signal, an encryption algorithm is executed based on an input encryption initial value to obtain an operator encryption value, wherein the operator encryption value is calculated from the u value obtained by the calculation.
When the number of array units in calculation in an operator calculation period is at least two, namely the second period and the subsequent operator calculation periods, an encrypted intermediate value obtained by calculation of the previous operator is used as an encrypted initial value of the current operator, in each operator calculation period, an input enabling signal of the current operator is determined based on an enabling signal output by the previous operator, and the encrypted intermediate value of the current operator is calculated based on the input enabling signal and the encrypted initial value until all the operators are completely calculated.
For the above accelerated computing method of the encryption algorithm, the present invention also provides an accelerated computing apparatus of the encryption algorithm, as shown in fig. 4, the apparatus is applied to a reconfigurable computing array, the reconfigurable computing array includes a plurality of operators, and the apparatus mainly includes the following parts:
a calculation period determining module 402, configured to determine an operator calculation period according to a preset processing time sequence; presetting a processing time sequence for determining the calculation process of an operator;
an array unit determining module 404 for determining an array unit based on the input byte number of the encryption algorithm;
and the accelerated calculation module 406 is configured to perform operator dynamic calculation based on the array units in the operator calculation period so as to perform accelerated calculation on the encryption algorithm.
The accelerated computing device for the encryption algorithm determines an operator computing period through the preset processing time sequence, determines the array unit through the input byte number of the encryption algorithm, and further performs operator dynamic computing based on the array unit in the determined operator computing period, so that the generation of large digital-analog multiplication time peak power consumption can be avoided, and the anti-attack capability is improved. Therefore, the embodiment of the invention can improve the calculation speed of the encryption algorithm, balance the calculation power consumption and improve the anti-attack capability during encryption calculation.
In an embodiment, the computation cycle determining module 402 is further configured to determine a computation cycle according to the number of operators of the reconfigurable computation array; wherein, the calculation period corresponds to the number of operators; the number of operators performing the calculation in each calculation period is different.
In one embodiment, in each calculation period of calculation in sequence, the number of operators for executing the calculation of the encryption algorithm is increased according to a preset increment; the preset increment is at least one operator increment.
In one embodiment, the above apparatus further comprises: and the time sequence switching module is used for determining the switching time sequence of the byte processing based on the input byte number of the encryption algorithm and the array unit.
In an embodiment, when the number of array units calculated in the operator calculation cycle is one, the acceleration module 406 is further configured to execute an encryption algorithm based on an input encryption initial value after the current operator receives the enable signal in the calculation cycle, so as to obtain an operator encryption value.
In one embodiment, when the number of the array units in an operator calculation period is at least two, the encryption intermediate value calculated by the last operator is used as the encryption initial value of the current operator; the acceleration module 406 is further configured to determine an input enable signal of the current operator based on the enable signal output by the previous operator; and calculating the encryption intermediate value of the current operator based on the input enabling signal and the encryption initial value until all operators are completely calculated.
The device provided by the embodiment of the present invention has the same implementation principle and technical effect as the method embodiments, and for the sake of brief description, reference may be made to the corresponding contents in the method embodiments without reference to the device embodiments.
Further, the present invention provides an array unit operator system, wherein the array unit operator system includes a plurality of array unit operator structures connected in sequence, and the array unit operator structure is shown in fig. 5, where the array unit operator structure is used for executing the accelerated computation method of the encryption algorithm in any one of the foregoing embodiments.
The embodiment of the invention provides electronic equipment, which particularly comprises a processor and a storage device; the storage means has stored thereon a computer program which, when executed by the processor, performs the method of any of the above described embodiments.
Fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present invention, where the electronic device 100 includes: a processor 60, a memory 61, a bus 62 and a communication interface 63, wherein the processor 60, the communication interface 63 and the memory 61 are connected through the bus 62; the processor 60 is arranged to execute executable modules, such as computer programs, stored in the memory 61.
The memory 61 may include a high-speed Random Access Memory (RAM) and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory. The communication connection between the network element of the system and at least one other network element is realized through at least one communication interface 63 (which may be wired or wireless), and the internet, a wide area network, a local network, a metropolitan area network, and the like can be used.
The bus 62 may be an ISA bus, PCI bus, EISA bus, or the like. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one double-headed arrow is shown in FIG. 6, but that does not indicate only one bus or one type of bus.
The memory 61 is used for storing a program, the processor 60 executes the program after receiving an execution instruction, and the method executed by the apparatus defined by the flow process disclosed in any of the foregoing embodiments of the present invention may be applied to the processor 60, or implemented by the processor 60.
The processor 60 may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware or instructions in the form of software in the processor 60. The Processor 60 may be a general-purpose Processor, and includes a Central Processing Unit (CPU), a Network Processor (NP), and the like; the device can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components. The various methods, steps and logic blocks disclosed in the embodiments of the present invention may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present invention may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software modules may be located in ram, flash, rom, prom, or eprom, registers, etc. as is well known in the art. The storage medium is located in a memory 61, and the processor 60 reads the information in the memory 61 and completes the steps of the method in combination with the hardware.
The method and the apparatus for accelerated computation of an encryption algorithm and the computer program product of an array unit operator system provided in the embodiments of the present invention include a computer-readable storage medium storing a nonvolatile program code executable by a processor, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by the processor, the method described in the foregoing method embodiments is executed.
It can be clearly understood by those skilled in the art that, for convenience and simplicity of description, the specific working process of the system described above may refer to the corresponding process in the foregoing embodiment, and details are not described herein again.
The computer program product of the readable storage medium provided in the embodiment of the present invention includes a computer readable storage medium storing a program code, where instructions included in the program code may be used to execute the method described in the foregoing method embodiment, and specific implementation may refer to the method embodiment, which is not described herein again.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. An accelerated computing method of an encryption algorithm is characterized in that the method is applied to a reconfigurable computing array; the reconfigurable computational array comprises a plurality of operators; the method comprises the following steps:
determining an operator calculation period according to a preset processing time sequence; the preset processing time sequence is used for determining the calculation process of an operator;
determining an array unit based on the input byte number of the encryption algorithm;
in the operator calculation period, carrying out operator dynamic calculation based on the array unit so as to carry out accelerated calculation on the encryption algorithm.
2. The method for accelerating calculation of an encryption algorithm according to claim 1, wherein the step of determining the calculation period of the operator in accordance with a predetermined processing timing includes:
determining a calculation period according to the number of operators of the reconfigurable calculation array; wherein the calculation period corresponds to the number of operators; the number of operators for executing calculation in each calculation period is different.
3. The accelerated computing method of encryption algorithms of claim 2, characterized in that in each computation cycle of the computation in sequence, the number of operators performing the computation of the encryption algorithms is increased according to a preset increment; the preset increment is at least one operator increment.
4. A method for accelerated computation of a cryptographic algorithm according to claim 1, characterized in that said method further comprises:
the switching timing of the byte processing is determined based on the number of input bytes of the encryption algorithm and the array unit.
5. The accelerated computing method of encryption algorithm according to claim 1, wherein when the number of array elements computed in the operator computation cycle is one, the step of performing dynamic computation of an operator based on the array elements in the operator computation cycle comprises:
in the calculation period, after the current operator receives the enabling signal, an encryption algorithm is executed based on the input encryption initial value, and the operator encryption value is obtained.
6. The accelerated computing method of encryption algorithm according to claim 5, wherein when the number of array elements in the computing period of the operator is at least two, the encryption intermediate value computed by the previous operator is used as the encryption initial value of the current operator; the step of dynamically calculating an operator based on the array unit in the operator calculation cycle includes:
determining an input enabling signal of the current operator based on the enabling signal output by the last operator;
and calculating the encryption intermediate value of the current operator based on the input enabling signal and the encryption initial value until all operators are completely calculated.
7. An accelerated computing device for cryptographic algorithms, said device being applied to a reconfigurable computing array; the reconfigurable computational array comprises a plurality of operators; the device comprises:
the calculation period determining module is used for determining an operator calculation period according to a preset processing time sequence; the preset processing time sequence is used for determining the calculation process of an operator;
an array unit determination module for determining an array unit based on the number of input bytes of the encryption algorithm;
and the accelerated calculation module is used for carrying out operator dynamic calculation based on the array unit in the operator calculation period so as to carry out accelerated calculation on the encryption algorithm.
8. An array unit operator system is characterized in that the array unit operator system comprises a plurality of array unit operator structures which are connected in sequence; wherein the array unit operator structure is adapted to perform the accelerated computation method of the cryptographic algorithm of any one of claims 1 to 6.
9. An electronic device comprising a processor and a memory, the memory storing machine executable instructions executable by the processor, the processor executing the machine executable instructions to implement the accelerated computing method of the cryptographic algorithm of any of claims 1 to 6.
10. A machine-readable storage medium having stored thereon machine-executable instructions which, when invoked and executed by a processor, cause the processor to implement a method of accelerated computing of a cryptographic algorithm as claimed in any of claims 1 to 6.
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