CN114499536A - Overload processing method and system for Sigma-Delta ADC - Google Patents

Overload processing method and system for Sigma-Delta ADC Download PDF

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Publication number
CN114499536A
CN114499536A CN202210332975.9A CN202210332975A CN114499536A CN 114499536 A CN114499536 A CN 114499536A CN 202210332975 A CN202210332975 A CN 202210332975A CN 114499536 A CN114499536 A CN 114499536A
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sigma
adc
input signal
integrator
delta adc
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张际宝
李炜
廖火荣
李建峰
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Shenzhen Apt Microelectronics Co ltd
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Shenzhen Apt Microelectronics Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters

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  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

The invention relates to an overload processing method for a Sigma-Delta ADC (analog to digital converter), which comprises the following steps of: detecting the amplitude of an input signal; generating a control signal according to the comparison result of the amplitude of the input signal and the input signal range of the ADC; and dynamically adjusting a feedforward coefficient or a feedback coefficient of the Sigma-Delta ADC according to the control signal. The invention generates a control signal to dynamically adjust the feedforward coefficient or the feedback coefficient of the Sigma-Delta ADC by comparing the amplitude of the input signal with the input signal range of the ADC, so that the overload of the ADC can be avoided by dynamically adjusting the internal coefficient of the ADC under the condition of not influencing the signal establishment of an internal integrator, and the invention has the advantages of high signal recovery speed and low system algorithm complexity.

Description

Overload processing method and system for Sigma-Delta ADC
Technical Field
The present invention relates to the field of signal processing technologies, and in particular, to an overload processing method and system for a Sigma-Delta ADC.
Background
With the rapid development of the ultra-large scale integrated circuit technology, the system has higher reliability and lower cost by adopting one-piece sensor signal acquisition and intelligent calculation. How to realize the functions required by the system by using a simple and proper structure and low power consumption as far as possible becomes a hot spot of scientific research and product development. Sigma-Delta ADCs (analog to digital converters) have wide application in the field of high-precision AD conversion, and can be well integrated in a chip system under the current small-size CMOS (Complementary Metal Oxide Semiconductor) process.
There is often an overload phenomenon in Sigma Delta ADCs where the theoretical output of the integrator exceeds the range that the actual circuit can handle. In prior methods of dealing with Sigma Delta ADC overload, reset integrators were typically used or the ADC was powered down and then powered up. However, the former will affect the signal establishment, the latter will require the system to be re-established, and the ADC will resume normal operation for a longer time. There is also a technology that detects adc input signals, outputs signals of each internal integrator, and then resets the integrator a if the integrator a is overloaded, and although a certain integrator is reset in a targeted manner, a certain time is required for establishing a system signal.
Disclosure of Invention
The invention aims to provide an overload processing method and system for a Sigma-Delta ADC (analog to digital converter), so as to avoid an unstable condition caused by overload of the ADC by dynamically adjusting internal coefficients of the ADC under the condition of not influencing the establishment of signals of an internal integrator.
According to an aspect of the present invention, there is provided an overload processing method for a Sigma-Delta ADC, including the steps of:
detecting the amplitude of an input signal;
generating a control signal according to the comparison result of the amplitude of the input signal and the input signal range of the ADC; and
and dynamically adjusting a feedforward coefficient or a feedback coefficient of the Sigma-Delta ADC according to the control signal.
In the overload processing method for the Sigma-Delta ADC, provided by the invention, in the step of generating the control signal according to the comparison result of the amplitude of the input signal and the input signal range of the ADC, if the amplitude of the input signal is greater than the input signal range of the ADC, the control signal is at a low level; and if the amplitude of the input signal is smaller than the input signal range of the ADC, the control signal is at a high level.
In the overload processing method for the Sigma-Delta ADC provided by the invention, the step of dynamically adjusting the feedforward coefficient or the feedback coefficient of the Sigma-Delta ADC according to the control signal comprises the following steps:
generating a control code according to the control signal;
and controlling the connection of a plurality of sampling capacitors of an integrator in the Sigma-Delta ADC to adjust the feedforward coefficient or the feedback coefficient of the Sigma-Delta ADC according to the control code.
In the overload processing method for the Sigma-Delta ADC, if the control signal is at a high level, all sampling capacitors in each integrator are controlled to be enabled; and if the control signal is at a low level, controlling one sampling capacitor in each integrator to be enabled.
According to another aspect of the present invention, there is also provided an overload processing system for a Sigma-Delta ADC, connected to the Sigma-Delta ADC, comprising:
the overload detection module is used for detecting the amplitude of the input signal and generating a control signal according to the comparison result of the amplitude of the input signal and the input signal range of the ADC; and
and the overload processing module is used for dynamically adjusting a feedforward coefficient or a feedback coefficient of the Sigma-Delta ADC according to the control signal.
In the overload processing system for the Sigma-Delta ADC, provided by the invention, if the amplitude of an input signal is greater than the input signal range of the ADC, the control signal is at a low level; and if the amplitude of the input signal is smaller than the input signal range of the ADC, the control signal is at a high level.
In the overload processing system for the Sigma-Delta ADC, provided by the invention, the overload processing module generates a control code according to the control signal; and the Sigma-Delta ADC controls the connection of a plurality of sampling capacitors of the integrator to adjust the feedforward coefficient or the feedback coefficient of the Sigma-Delta ADC according to the control code.
In the overload processing system for the Sigma-Delta ADC, if the control signal is at a high level, all sampling capacitors in each integrator are controlled to be enabled; and if the control signal is at a low level, controlling one sampling capacitor in each integrator to be enabled.
The overload processing method for the Sigma-Delta ADC has the following beneficial effects: the overload processing method for the Sigma-Delta ADC provided by the invention generates a control signal to dynamically adjust the feedforward coefficient or the feedback coefficient of the Sigma-Delta ADC by comparing the amplitude of the input signal with the input signal range of the ADC, so that the overload of the ADC can be avoided by dynamically adjusting the internal coefficient of the ADC under the condition of not influencing the signal establishment of an internal integrator, and the overload processing method has the advantages of high recovery speed and low algorithm complexity.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts:
FIG. 1 is a schematic diagram of an overload handling system for a Sigma-Delta ADC according to an embodiment of the present invention;
FIG. 2 is a diagram showing the architecture of a feedforward Sigma Delta ADC in which an overload processing system according to the present invention is applied;
FIG. 3 is a diagram showing the architecture of an overload processing system for a Sigma Delta ADC according to the present invention applied to a feedback Sigma Delta ADC;
FIG. 4 shows the integrator output signal VoutA schematic of the change over time;
fig. 5 shows a specific implementation of the gain circuit inside the integrator of fig. 2 and 3.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In a feed forward Sigma Delta ADC (as shown in fig. 3), the transfer function of the first stage integrator is as follows as the input signal increases
Vout= - Cs*Vin/Cf (1)
Wherein, CsTo sample the capacitance, CfIs the integrating capacitance. When V isinWhen increasing, VoutIt increases in the opposite direction. In the actual circuit, VoutFrom 0 to the power supply level. When V isoutWhen the power supply level or 0 is reached, the ADC system may be overloaded, i.e., the ADC output outputs a high level or a low level for a long time.
The general idea of the invention is therefore: aiming at the defect that the method for processing the overload of the Sigma-Delta ADC in the prior art has long time for establishing the output signal of the integrator, the overload processing method for the Sigma-Delta ADC is provided, a control signal is generated to dynamically adjust the feedforward coefficient or the feedback coefficient of the Sigma-Delta ADC by comparing the amplitude of an input signal with the input signal range of the ADC, so that the overload of the ADC is avoided by dynamically adjusting the internal coefficient of the ADC under the condition of not influencing the signal establishment of an internal integrator, and the overload processing method has the advantages of high recovery speed and low algorithm complexity.
Fig. 1 is a schematic diagram of an overload handling system for a Sigma-Delta ADC according to an embodiment of the present invention. As shown in FIG. 1, the overload handling system for Sigma-Delta ADC provided by the present invention is connected to Sigma-Delta ADC 110, and it will be understood by those skilled in the art that Sigma-Delta ADC 110 may be a feed-forward Sigma-Delta ADC (shown in FIG. 2) or a feedback Sigma-Delta ADC (shown in FIG. 3), and the present invention is not limited thereto. The overload processing system for the Sigma-Delta ADC comprises an overload detection module 120 and an overload processing module 130, wherein the overload detection module 120 is connected to the overload processing module 130, and the overload processing module 130 is connected to the Sigma-Delta ADC 110. The input end of the overload detection module 120 is connected to the input voltage signal, and is configured to detect an amplitude of the input signal, and then generate a control signal according to a comparison result between the amplitude of the input signal and a range of the input signal of the ADC, and transmit the control signal to the overload processing module 130; the overload processing module 130 dynamically adjusts an internal parameter of the Sigma-Delta ADC according to the control signal, wherein the internal parameter is a feed-forward coefficient or a feedback coefficient.
Example one
FIG. 2 is a diagram showing the architecture of a feedforward Sigma Delta ADC in which an overload processing system for the Sigma Delta ADC according to the present invention is applied. As shown in fig. 2, the feedforward Sigma Delta ADC includes n integrators (integrator 1 and integrator 2....... integrator n) connected in series in sequence, an input end of each integrator is connected with an integrator coefficient (integrator coefficient c1 and integrator coefficient c2..... integrator coefficient cn), an output end of each integrator is connected with a feedforward coefficient (feedforward coefficient a1 and feedforward coefficient a2...... feedforward coefficient an) and an integrator coefficient of the next integrator, and all feedforward coefficients are connected to an input end of the comparator a. For example, the input end of the integrator 1 is connected with an integrator coefficient c1, and the output end of the integrator 1 is connected with a feedforward coefficient a1 and an integrator coefficient c2 of the integrator 2. In the prior art, when an overload occurs in a Sigma Delta ADC, the overload is avoided by resetting the integrator or adjusting the integrator coefficients. From equation 1, as shown in fig. 4, V is obtained if the overload is adjusted by resetting the integrator at the next signal transitionoutThe time required to rise from the 0 level or the common mode level to the theoretical value is t1. If the method of this embodiment is used, i.e. the overload is adjusted by adjusting the feedforward coefficient of the integrator, the V of the integratoroutDoes not need to be reset to 0, but from VoutSo that V startsoutThe time required for rising to the theoretical value is t2. As shown in fig. 4, t2Less than t1. Furthermore, if overload is avoided by adjusting the integrator coefficients, the time required for the signal to build up to completion is short, but it still affects the building up of the integrator output signal. The invention is adjusted byThe feedforward coefficient of the integrator only affects the feedforward addition of the signal and has no influence on the establishment of the output signal of the integrator, so the overload phenomenon of the ADC can be adjusted in a short time by dynamically adjusting and adjusting the internal coefficient of the ADC under the condition of not affecting the establishment of the signal of the internal integrator.
Specifically, in an embodiment of the present invention, as shown in fig. 2, the overload detection module 120 of the overload processing system provided in this embodiment employs a voltage comparator. The full-scale threshold voltage of the feedforward Sigma Delta ADC is input to the positive input end of the voltage comparator, and the input voltage signal V of the feedforward Sigma Delta ADC is connected to the negative input endin. When inputting a voltage signal VinWhen the voltage is less than the full-scale threshold voltage, the voltage comparator outputs a high level to the overload processing module 130; when inputting a voltage signal VinAbove the full scale threshold voltage, the voltage comparator outputs a low level to the overload processing module 130.
Specifically, in an embodiment of the present invention, as shown in fig. 2, after receiving the control signal from the overload detection module 120, the overload processing module 130 needs to output a corresponding control code according to the control signal; after the feedforward type Sigma-Delta ADC receives the control code, the feedforward coefficient of the corresponding integrator is controlled according to the control code. Fig. 5 shows a gain circuit inside one of the integrators in fig. 2, and as shown in fig. 5, each integrator includes a comparator op, two input terminals of the comparator are respectively connected to n sampling capacitor branches connected in parallel, and each sampling capacitor branch includes a sampling capacitor Cs and a sampling capacitor switch (k1... k n). The control code from the overload processing signal 130 controls the sampling capacitor to operate by controlling the connection or disconnection of the sampling capacitor switch, and the feedforward coefficient of the integrator can be adjusted by controlling the connection of the sampling capacitor branch, that is, the adjustment of the multiple of the feedforward coefficient is realized by adjusting the number of the sampling capacitors connected to the circuit.
In an embodiment of the present invention, when the overload detection module 120 detects that the amplitude of the input signal is smaller than the range of the input signal of the ADC, it indicates that the overload does not occur, and at this time, the overload detection module 120 outputs a high-level control signal;the overload processing module 130 generates a high-level control code according to the high-level control signal, for example, if the control code is 3 bits, the control code of 3' b111 is output; after the integrator of the Sigma-Delta ADC receives the control code of 3' b111, all sampling capacitance modules are enabled, namely sampling capacitance switches k 1-kn and k1 b-knb are all closed, and at the moment, VoutAnd a large signal is output, and the gain of the integrator is large. It will be appreciated by those skilled in the art that the number of bits of the control code may also be other numbers, for example, if the control code is 4 bits, when the overload processing module 130 receives a high-level control signal, it generates a control code of 4' b1111 to send to the integrator; when the overload processing module 130 receives the low-level control signal, it generates a control code of 4' b00000 and sends the control code to the integrator, which is not limited in the present invention.
In another embodiment of the present invention, when the overload detection module 120 detects that the amplitude of the input signal is greater than the range of the input signal of the ADC, it indicates that an overload occurs, and at this time, the overload detection module 120 outputs a low-level control signal; the overload processing module 130 generates a low-level control code according to the low-level control signal, for example, if the control code is 3 bits, it outputs a 3' b000 control code; after the integrator of the Sigma-Delta ADC receives the 3' b000 control code, only one sampling capacitor module of the integrator is enabled, namely sampling capacitor switches k1 and k1b are closed, and sampling capacitor switches k 2-kn and k2 b-knb are kept in an open state, and at the moment, V is in a state of being openedoutAnd a small signal is output, and the gain of the integrator is small so as to ensure that the output signal can be stable after a plurality of cycles.
Example two
Fig. 3 is a diagram showing an architecture of an overload processing system for a Sigma Delta ADC according to the present invention applied to a feedback Sigma Delta ADC. As shown in fig. 3, the feedback Sigma Delta ADC includes n integrators (integrator 1 and integrator 2...... integrator n) connected in series in sequence, an input end of each integrator is connected with an integrator coefficient (integrator coefficient c1 and integrator coefficient c2..... integrator coefficient cn) and a feedback coefficient (feedback coefficient a1 and feedback coefficient a2.... feedback coefficient an), and an output end of each integrator is connected with a next integrator coefficient anIntegrator coefficients and feedback coefficients of the divider, all of which are connected to the output of the comparator. For example, the input end of the integrator 1 is connected with an integrator coefficient c1 and a feedback coefficient a1, and the output end of the integrator 1 is connected with an integrator coefficient c2 and a feedback coefficient a2 of the integrator 2. In the prior art, when an overload occurs in a Sigma Delta ADC, the overload is avoided by resetting the integrator or adjusting the integrator coefficients. From equation 1, as shown in fig. 4, V is obtained if the overload is adjusted by resetting the integrator at the next signal transitionoutThe time required to rise from the 0 level or the common mode level to the theoretical value is t1. If the method of this embodiment is used, i.e. the overload is adjusted by adjusting the feedforward coefficient of the integrator, the V of the integratoroutDoes not need to be reset to 0, but from VoutSo that V startsoutThe time required for rising to the theoretical value is t2. As shown in fig. 4, t2Less than t1. Furthermore, if overload is avoided by adjusting the integrator coefficients, the time required for the signal to build up to completion is short, but it still affects the building up of the integrator output signal. The feedback coefficient of the integrator is adjusted, only the feedback summation of signals is influenced, and the establishment of the output signals of the integrator is not influenced.
Specifically, in an embodiment of the present invention, as shown in fig. 3, the overload detection module 120 of the overload processing system provided in this embodiment employs a voltage comparator. The full-scale threshold voltage of the feedback type Sigma Delta ADC is input to the positive input end of the voltage comparator, and the input voltage signal V of the feedback type Sigma Delta ADC is connected to the negative input endin. When inputting a voltage signal VinWhen the voltage is less than the full-scale threshold voltage, the voltage comparator outputs a high level to the overload processing module 130; when inputting a voltage signal VinAbove the full scale threshold voltage, the voltage comparator outputs a low level to the overload processing module 130.
Specifically, in an embodiment of the present invention, as shown in fig. 3, after receiving the control signal from the overload detection module 120, the overload processing module 130 needs to output a corresponding control code according to the control signal; and after receiving the control code, the feedback type Sigma-Delta ADC controls the feedback coefficient of the corresponding integrator according to the control code. Fig. 5 shows a gain circuit inside one of the integrators in fig. 3, and as shown in fig. 5, each integrator includes a comparator op, two input terminals of the comparator are respectively connected to n sampling capacitor branches connected in parallel, and each sampling capacitor branch includes a sampling capacitor Cs and a sampling capacitor switch (k1... k n). The control code from the overload processing signal 130 controls the sampling capacitor to operate by controlling the connection or disconnection of the sampling capacitor switch, and the feedback coefficient of the integrator can be adjusted by controlling the connection of the sampling capacitor branches, that is, the adjustment of the multiple of the feedback coefficient is realized by adjusting the number of the sampling capacitors connected to the circuit.
In an embodiment of the present invention, when the overload detection module 120 detects that the amplitude of the input signal is smaller than the range of the input signal of the ADC, it indicates that the overload does not occur, and at this time, the overload detection module 120 outputs a high-level control signal; the overload processing module 130 generates a high-level control code according to the high-level control signal, for example, if the control code is 3 bits, the control code of 3' b111 is output; after the integrator of the Sigma-Delta ADC receives the control code of 3' b111, all sampling capacitance modules are enabled, namely sampling capacitance switches k 1-kn and k1 b-knb are all closed, and at the moment, VoutAnd a large signal is output, and the gain of the integrator is large. It will be appreciated by those skilled in the art that the number of bits of the control code may also be other numbers, for example, if the control code is 4 bits, when the overload processing module 130 receives a high-level control signal, it generates a control code of 4' b1111 to send to the integrator; when the overload processing module 130 receives the low-level control signal, it generates a control code of 4' b00000 and sends the control code to the integrator, which is not limited in the present invention.
In another embodiment of the present invention, when the overload detection module 120 detects that the amplitude of the input signal is larger than the range of the input signal of the ADC, it indicates that the overload occurs, and the overload detection module 120 outputs the overloadOutputting a low-level control signal; the overload processing module 130 generates a low-level control code according to the low-level control signal, for example, if the control code is 3 bits, it outputs a 3' b000 control code; after the integrator of the Sigma-Delta ADC receives the 3' b000 control code, only one sampling capacitor module of the integrator is enabled, namely sampling capacitor switches k1 and k1b are closed, and sampling capacitor switches k 2-kn and k2 b-knb are kept in an open state, and at the moment, V is in a state of being openedoutAnd a small signal is output, and the gain of the integrator is small so as to ensure that the output signal can be stable after a plurality of cycles.
EXAMPLE III
The invention also provides an overload processing method for the Sigma-Delta ADC, which comprises the following steps:
step S1, detecting the amplitude of the input signal;
specifically, in one embodiment of the invention, the amplitude of the input voltage of the Sigma-Delta ADC is detected by the overload detection module.
Step S2, generating a control signal according to the comparison result of the amplitude of the input signal and the input signal range of the ADC;
specifically, in one embodiment of the present invention, the amplitude of the input signal is compared with the input signal range of the ADC, and if the amplitude of the input signal is greater than the input signal range of the ADC, a low-level control signal is generated; if the amplitude of the input signal is less than the input signal range of the ADC, a high level control signal is generated.
And step S3, dynamically adjusting a feedforward coefficient or a feedback coefficient of the Sigma-Delta ADC according to the control signal.
Specifically, in an embodiment of the present invention, a control code is generated according to the control signal; and then controlling the connection of a plurality of sampling capacitors of an integrator in the Sigma-Delta ADC according to the control code to adjust the feedforward coefficient or the feedback coefficient of the Sigma-Delta ADC. Further, if the control signal is at a high level, all sampling capacitors in each integrator are controlled to be enabled; and if the control signal is at a low level, controlling one sampling capacitor in each integrator to be enabled. Therefore, the overload phenomenon of the ADC can be adjusted in a short time by dynamically adjusting the feedback coefficient of the ADC without influencing the signal establishment of the internal integrator.
The overload processing method for the Sigma-Delta ADC solves the problem of overload of the Sigma-Delta ADC by adjusting internal coefficients a 1-an of the Sigma-Delta ADC, and is suitable for a feedforward Sigma Delta ADC and a feedback Sigma Delta ADC. By comparing the magnitude of the input signal to the input signal span of the ADC to control the internal coefficients of the Sigma Delta ADC, the integrator output signal settling takes less time than conventionally resetting the ADC.
Certain specific embodiments of the present invention have been described above. Note that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. For example, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Although several embodiments of the present invention have been described above with reference to the accompanying drawings, it is to be understood that the invention is not limited to the specific embodiments disclosed. The invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.

Claims (8)

1. An overload processing method for a Sigma-Delta ADC (analog to digital converter) is characterized by comprising the following steps of:
detecting the amplitude of an input signal;
generating a control signal according to the comparison result of the amplitude of the input signal and the input signal range of the ADC; and
and dynamically adjusting a feedforward coefficient or a feedback coefficient of the Sigma-Delta ADC according to the control signal.
2. The overload processing method for the Sigma-Delta ADC of claim 1, wherein in the step of generating the control signal according to the comparison result between the amplitude of the input signal and the input signal range of the ADC, if the amplitude of the input signal is greater than the input signal range of the ADC, the control signal is at a low level; and if the amplitude of the input signal is smaller than the input signal range of the ADC, the control signal is at a high level.
3. The overload processing method for the Sigma-Delta ADC of claim 2, wherein the step of dynamically adjusting the feed-forward coefficients or the feedback coefficients of the Sigma-Delta ADC according to the control signal comprises:
generating a control code according to the control signal;
and controlling the connection of a plurality of sampling capacitors of an integrator in the Sigma-Delta ADC to adjust the feedforward coefficient or the feedback coefficient of the Sigma-Delta ADC according to the control code.
4. The overload processing method for the Sigma-Delta ADC of claim 3, wherein if the control signal is high, all sampling capacitors in each integrator are controlled to be enabled; and if the control signal is at a low level, controlling one sampling capacitor in each integrator to be enabled.
5. An overload handling system for a Sigma-Delta ADC connected to the Sigma-Delta ADC, comprising:
the overload detection module is used for detecting the amplitude of the input signal and generating a control signal according to the comparison result of the amplitude of the input signal and the input signal range of the ADC; and
and the overload processing module is used for dynamically adjusting a feedforward coefficient or a feedback coefficient of the Sigma-Delta ADC according to the control signal.
6. The overload processing system for the Sigma-Delta ADC of claim 5, wherein the control signal is low if the magnitude of the input signal is greater than an input signal range of the ADC; and if the amplitude of the input signal is smaller than the input signal range of the ADC, the control signal is at a high level.
7. The overload processing system for the Sigma-Delta ADC of claim 6, wherein the overload processing module generates a control code according to the control signal; and the Sigma-Delta ADC controls the connection of a plurality of sampling capacitors of the integrator to adjust the feedforward coefficient or the feedback coefficient of the Sigma-Delta ADC according to the control code.
8. The overload processing system for the Sigma-Delta ADC of claim 7, wherein if the control signal is high, all sampling capacitors in each integrator are controlled to be enabled; and if the control signal is at a low level, controlling one sampling capacitor in each integrator to be enabled.
CN202210332975.9A 2022-03-31 2022-03-31 Overload processing method and system for Sigma-Delta ADC Pending CN114499536A (en)

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Citations (6)

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Publication number Priority date Publication date Assignee Title
US6064326A (en) * 1998-03-30 2000-05-16 Silicon Laboratories, Inc. Analog-to-digital conversion overload detection and suppression
CN1893281A (en) * 2005-03-03 2007-01-10 阿纳洛格装置公司 Apparatus and method for controlling the state variable of an integrator stage in a modulator
CN102291150A (en) * 2011-04-15 2011-12-21 深圳大学 Sigma-delta modulator
CN102739254A (en) * 2011-04-02 2012-10-17 苏州启芯信息技术有限公司 Sigma-delta type analog-to-digital converter (ADC)
US20140240153A1 (en) * 2013-02-28 2014-08-28 Texas Instruments Incorporated Advanced overload protection in sigma delta modulators
CN105406871A (en) * 2014-09-04 2016-03-16 亚德诺半导体集团 Embedded Overload Protection In Delta-sigma Analog-to-digital Converters

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6064326A (en) * 1998-03-30 2000-05-16 Silicon Laboratories, Inc. Analog-to-digital conversion overload detection and suppression
CN1893281A (en) * 2005-03-03 2007-01-10 阿纳洛格装置公司 Apparatus and method for controlling the state variable of an integrator stage in a modulator
CN102739254A (en) * 2011-04-02 2012-10-17 苏州启芯信息技术有限公司 Sigma-delta type analog-to-digital converter (ADC)
CN102291150A (en) * 2011-04-15 2011-12-21 深圳大学 Sigma-delta modulator
US20140240153A1 (en) * 2013-02-28 2014-08-28 Texas Instruments Incorporated Advanced overload protection in sigma delta modulators
CN105406871A (en) * 2014-09-04 2016-03-16 亚德诺半导体集团 Embedded Overload Protection In Delta-sigma Analog-to-digital Converters

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