CN114499514B - Phase jitter sampling method - Google Patents
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- CN114499514B CN114499514B CN202210404866.3A CN202210404866A CN114499514B CN 114499514 B CN114499514 B CN 114499514B CN 202210404866 A CN202210404866 A CN 202210404866A CN 114499514 B CN114499514 B CN 114499514B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
- H03M1/0634—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale
- H03M1/0656—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
Abstract
The invention discloses a phase jitter sampling method, which is characterized in that a timing trigger module is designed based on a programmable logic internal clock period, a trigger pulse signal with a preset time interval is generated, the trigger signal is sent to a phase adjustment module, the phase adjustment module takes an output signal of the timing trigger module as an input, a sampling adjustment period is set, the phase of the first sampling period in each adjustment period is adjusted once, the other sampling periods are kept unchanged, the phase offset of one clock period is increased every time, when the total delay of the increased phase reaches the set clock period, the phase offset which is reduced by one clock period is started to be generated until the phase offset is zero, and then the process is repeated to realize phase jitter sampling. According to the invention, through setting and adjusting the sampling period and the phase, the sampling points of the jitter phase slide between the sampling points at fixed time in sequence, and the problem of information loss of signals caused by abnormal signals between the two sampling points is avoided.
Description
Technical Field
The invention relates to the technical field of digital information transmission protection, in particular to a phase jitter sampling method.
Background
Digital control's equipment all need be with analog quantity signal conversion digital signal, what generally adopted is analog-to-digital conversion module (ADC), according to the nyquist sampling theorem, generally selects 2 times of sampling frequency more than or equal to analog signal frequency, just can resume analog signal through digital signal, and generally ADC sampling all adopts fixed frequency cycle sampling, and the system sends sampling signal regularly and gives the ADC, controls ADC sampling analog quantity.
If the abnormal part in the signal is just between two sampling points, the recovered signal can lose the signal information of the part, so the invention provides a sampling method of a jitter phase sampling signal, which is equivalent to that the sampling points of the jitter phase slide between the sampling points at fixed time in sequence.
Disclosure of Invention
The purpose of the invention is as follows: the invention aims to provide a phase jitter sampling method aiming at the defects of the prior art, and compared with the prior art, the phase jitter sampling method realizes that sampling points of a jitter phase slide between sampling points at fixed time in sequence by setting and adjusting a sampling period and the phase, thereby avoiding the problem of signal loss caused by abnormal signals between two sampling points.
The invention discloses a phase jitter sampling method, which adopts programmable logic and controls an ADC (analog-to-digital converter) module to trigger sampling through a timing trigger module, a phase adjustment module and a fixed phase trigger module, and comprises the following steps:
step 1: setting a programmable logic internal clock period T, a preset adjusting period Tp and a preset adjusting phase number;
step 2: designing a timing trigger module based on the internal clock period T of the programmable logic, wherein the timing trigger module generates a trigger pulse signal with a sampling period of Ts;
and step 3: transmitting a trigger pulse signal with a sampling period of Ts to a phase adjustment module, wherein the phase adjustment module takes a pulse signal output by a timing trigger module as input, performs phase adjustment on the trigger pulse signal, generates a trigger sampling signal after phase adjustment, and controls an ADC module to trigger sampling by taking the trigger sampling signal as a first sampling signal in a preset adjustment period Tp;
and 4, step 4: the fixed phase module takes the sampling signal after the first phase adjustment in a preset adjustment period Tp as an input signal, generates a sampling signal of a fixed phase with the sampling period of Ts as a reference, and takes the sampling signal as the rest sampling signals in the preset adjustment period Tp to control the ADC module to trigger sampling;
In the phase adjustment process, the phase adjustment module increases the phase offset of one clock cycle T for the first sampling signal each time, when the total delay of the increased phases reaches a preset adjustment phase number, the phase is reduced, in the phase reduction process, the phase adjustment module reduces the phase offset of one clock cycle T each time until the phase offset is zero, and then the phase adjustment process is repeated to realize phase jitter.
The sampling period Ts of the trigger pulse signal generated by the timing trigger module comprises Ts/T clock periods.
The phase adjusting module performs phase adjustment on the phase offset of increasing or decreasing the trigger pulse signal by one clock cycle T each time.
The timing trigger module counts by the internal clock period T of the programmable logic and generates a trigger pulse signal with the sampling period of Ts.
The period of the sampling signal generated by the fixed phase module is equal to the sampling period Ts of the trigger pulse signal generated by the timing trigger module.
The sampling signal in the adjustment period Tp includes one sampling signal whose phase is adjusted and the remaining sampling signals whose phases are kept unchanged.
The phase is adjusted only once in the adjusting period Tp, namely the first sampling period of the adjusting period Tp, the phases of the other sampling periods are kept unchanged, and the preset adjusting phase number is that the total delay of the increased phases reaches the preset clock period number
When the phase adjustment module adjusts the phase, a phase shift trigger time is generated, which includes a positive offset time T1 and a negative offset time T2, and the specific calculation formula is as follows:
wherein n represents a bit of the number of adjustment times; n represents the number of adjustments, i.e. the Nth adjustment phase, N ranges from
In the middle of; ts represents the sampling period; t denotes a clock cycle.
The phase shift comprises a positive offset and a negative offset, and the positive offset leads the phase to generate a trigger signal by the timing trigger module; the negative shift is based on the leading phase of the positive shift and then the negative shift, so that the phase returns to the trigger signal which is consistent with the trigger signal generated by the timing trigger module.
The technical scheme of the invention has the following beneficial effects:
1. according to the phase jitter sampling method, the information between two fixed sampling points can be acquired by a system through a sampling method of a jitter phase, and if sampling with fixed frequency is adopted in a period of time, the sampling position of each point can be calculated according to the position of the first point. Based on the phase jitter sampling method, if the sampling point is positively shifted by one phase, the sampling point is equivalent to sampling once between fixed sampling points, and then the phase is shifted continuously, so that all positions between two fixed phase points are sampled on the whole.
2. According to the phase jitter sampling method, the sampling period and the phase are set and adjusted, so that the sampling points of the jitter phase sequentially slide between the sampling points at fixed moments, and the problem that information is lost due to abnormal signals between the two sampling points is solved.
Drawings
Fig. 1 is a schematic flow chart of ADC sampling by phase dithering according to the present invention.
FIG. 2 is a timing diagram of logic signals for timing generation of 2us trigger pulse signals according to the present invention.
FIG. 3 is a timing diagram of logic signals for generating 8 sampling periods with fixed phases according to the present invention.
FIG. 4 is a phase diagram of the present invention with 1 clock cycle added every 8 sampling cycles of fixed phase.
FIG. 5 is a phase diagram of the present invention showing the reduction of 1 clock cycle per 8 fixed phase sampling periods.
FIG. 6 is a schematic diagram of the invention with a phase increased by 1 clock cycle, and a clock cycle increased for each adjustment cycle.
FIG. 7 is a schematic diagram showing that each adjustment cycle is reduced by one clock cycle when the phase is reduced by 1 clock cycle according to the present invention.
Fig. 8 is a schematic diagram of the present invention comparing the timing of generating 2us triggers with the sampling of the actual jittered phase.
FIG. 9 is a timing diagram of the positive and negative phase offsets of the present invention.
Detailed Description
The technical solution of the present invention is described in detail below, but the scope of the present invention is not limited to the embodiments.
As shown in fig. 1, the present invention discloses a phase jitter sampling method, which uses programmable logic to control an ADC module to trigger sampling through a timing trigger module, a phase adjustment module and a fixed phase module, and comprises the following steps:
step 1: setting the internal clock period T of the programmable logic to 10ns, and presetting an adjustment period Tp for every 8 sampling periods Ts and presetting an adjustment phase number of 128 clock periods T.
And 2, step: designing a timing trigger module based on the internal clock period T of the programmable logic, wherein the timing trigger module generates a trigger pulse signal with the sampling period Ts of 2us, and each sampling period Ts comprises 200 clock periods T at intervals.
Specifically, as shown in FIG. 2, clk is the programmable logic internal clock, and the rad _ trig is the trigger signal that generates a pulse with a sampling period of 2 us.
And 3, step 3: the trigger pulse signal with the sampling period of Ts is transmitted to a phase adjustment module, the phase adjustment module takes the pulse signal output by the timing trigger module as input, the trigger pulse signal is adjusted, a trigger sampling signal with the adjusted phase is generated, the trigger sampling signal is used as a first sampling signal in a preset adjustment period Tp, and the ADC module is controlled to trigger sampling.
Specifically, the phase adjustment module receives a pulse signal with a sampling period Ts of 2us input by the timing trigger module, and adjusts a phase once in a first sampling period of each preset 8 sampling periods Ts, and after the phase is adjusted, a trigger sampling signal with the adjusted phase is generated as the first sampling signal with 8 sampling periods Ts to control the ADC module to trigger sampling.
And 4, step 4: the fixed phase module takes a first sampling signal in a preset adjusting period Tp as an input signal, generates other sampling signals in the adjusting period Tp with the input signal as a reference and the period of Ts, and controls the ADC module to trigger sampling; the first sampling signal in each preset adjusting period Tp is adjusted once in phase, the other sampling signals in the preset adjusting period Tp keep the phase unchanged, in the process of phase increase, the phase adjusting module increases the phase offset of one clock period T each time, when the total delay of the increased phases reaches the preset adjusting phase number, the phase reducing module starts to generate the reduced phase, in the process of phase reduction, the phase adjusting module reduces the phase offset of one clock period T each time until the phase offset is zero, and then the process of phase adjustment is repeated, so that the phase dithering is realized.
Specifically, a preset sampling period Ts every 8 us intervals is an adjustment period Tp, a phase of a first sampling period Ts in each adjustment period Tp (i.e., every 8 sampling periods Ts) is adjusted once, and the remaining 7 sampling periods are kept unchanged, the phase adjustment module adjusts the phase of the first sampling period, each time the phase offset of one clock period T is increased, and when the total increased phase delay reaches 128 clock periods T, the phase offset of one clock period starts to be decreased until the phase offset is zero.
The phase adjustment module adjusts the phase of an input trigger pulse signal with a sampling period of Ts, the phase offset of one clock period T is increased or decreased on the basis of the previous phase adjustment, the minimum phase inside the programmable logic device is adjusted to (T/Ts) × 2 × pi, the programmable logic device with the frequency of F =100MHZ and the clock period of T =10ns is adopted in the scheme, and other frequencies, pi =3.1415926, the angle calculated according to radian can be selected. The sampling signal with fixed phase generated by the fixed phase module is connected with the trigger sampling signal with adjusted phase, that is, other sampling signals except the first sampling signal in the adjustment period Tp keep the fixed phase to continue sampling for a period of time based on the phase of the first sampling signal. Each adjustment period Tp includes the first sampling signal with the adjusted phase and the other sampling signals with the fixed phase generated by the fixed phase module and continuing to the first sampling signal, and the first sampling signal with the adjusted phase and the other sampling signals with the fixed phase continuing to the first sampling signal serve as all sampling signals in one adjustment period to control the ADC module to trigger sampling.
As shown in fig. 4, a clock cycle is added every 8 sampling cycles, which is equivalent to that the phase is added by a certain phase amount, wdelta represents the phase amount of one clock cycle added every 8 sampling cycles, wfirst represents that the trigger signals output by 8 trigger modules are used as one adjustment cycle, and the phase is adjusted once by using the first trigger signal of one adjustment cycle. Fig. 4 shows a positive shift of the phase, and fig. 5 shows a negative shift. As shown in fig. 5, the phase is decreased by 1 clock cycle every 8 sampling cycles, which is equivalent to the phase being decreased by a certain phase amount, wdelta represents the phase amount of one clock cycle decreased every 8 sampling cycles, wdirst represents that the trigger signals output by 8 trigger modules are used as one adjustment cycle, and the phase is adjusted once by the first trigger signal of one adjustment cycle. As also shown in FIG. 3, adc _ firtttrig _ i is an input trigger signal and adc _ trig _ o outputs 7 trigger signals, where the 7 trigger signals and the input trigger signal constitute 8 trigger signals. Due to the phase adjustment, the first sampling period is changed to 201 clock cycles when the phase is increased, and to 199 clock cycles when the phase is decreased, but the total number of sampling cycles is not changed throughout the process. As shown in fig. 6, when the phase increases, the first sampling period changes to 201 clock cycles, the other 7 sampling periods are 200 clock cycles, radc _ actcnt2 represents the number of sampling cycles, wfirst represents the first trigger signal with one cycle of trigger signals output by 8 trigger modules, and adc _ trig _ o represents the trigger sampling signal actually output. As shown in fig. 7, when the phase decreases, the first sampling period becomes 199 clock periods, the other 7 sampling periods are 200 clock periods, radc _ actcnt2 represents the number of sampling periods, wfirst represents the first trigger signal with one period being the trigger signal output by 8 trigger modules, and adc _ trig _ o represents the trigger sampling signal actually output. Phase adjusted triggers, as shown in fig. 8, rdc _ trig represents a fixed phase timing 2us trigger and adc _ trig _ o is a sampled trigger after phase dithering is achieved.
When the phase adjusting module adjusts the phase, phase shift is generated, the phase shift comprises positive offset and negative offset, and the positive offset leads the phase to be ahead of the trigger signal generated by the timing trigger module; the negative shift is based on the leading phase of the positive shift and then the negative shift, so that the phase returns to the trigger signal consistent with the generation of the timing trigger module, and then the phase shift trigger time is generated, wherein the trigger time comprises a positive shift time T1 and a negative shift time T2, and the specific calculation formula is as follows:
wherein n represents a bit of the number of adjustment times; n denotes the number of adjustments, i.e. the Nth adjustment phase, N ranges
To (c) to (d); ts represents the sampling period; t denotes a clock cycle. N is an unsigned number, for example: n =256, then N =8 bits, less than 128 positive adjustments and greater than 128 negative adjustments. A specific calculation diagram is shown in fig. 9.
The invention discloses a phase jitter sampling method, which adopts programmable logic, controls an ADC (analog-to-digital converter) module to trigger sampling through a timing trigger module, a phase adjustment module and a fixed phase trigger module, sets an internal clock period of the programmable logic, designs the timing trigger module based on the internal clock period of the programmable logic, generates a trigger pulse signal with a sampling period of Ts, sends the trigger pulse signal to the phase adjustment module, adjusts the phase of the first sampling period in each adjustment period according to a preset adjustment period by taking an output signal of the timing trigger module as an input of the phase adjustment module, keeps the rest sampling periods unchanged, adjusts the phase by the phase adjustment module, increases the phase offset of one clock period each time, and starts to reduce the phase offset of one clock period when the total delay of the increased phase reaches the set clock period, until the phase offset is zero, and then the process is repeated to realize phase jitter sampling. According to the invention, through setting and adjusting the sampling period and the phase, the sampling points of the jitter phase slide between the sampling points at the fixed moment in sequence, and the problem of signal loss caused by abnormal signals between the two sampling points is avoided.
As noted above, while the present invention has been shown and described with reference to certain preferred embodiments, it is not to be construed as limited to the invention itself. Various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (9)
1. A phase jitter sampling method adopts programmable logic, controls an ADC module to trigger sampling through a timing trigger module, a phase adjustment module and a fixed phase module, and is characterized by comprising the following steps:
step 1: setting a programmable logic internal clock period T, a preset adjusting period Tp and a preset adjusting phase number;
step 2: designing a timing trigger module based on the internal clock period T of the programmable logic, wherein the timing trigger module generates a trigger pulse signal with a sampling period of Ts;
and step 3: transmitting a trigger pulse signal with a sampling period of Ts to a phase adjustment module, wherein the phase adjustment module takes a pulse signal output by a timing trigger module as input, performs phase adjustment on the trigger pulse signal, generates a trigger sampling signal after phase adjustment, and controls an ADC module to trigger sampling by taking the trigger sampling signal as a first sampling signal in a preset adjustment period Tp;
And 4, step 4: the fixed phase module takes a sampling signal after the first phase adjustment in a preset adjustment period Tp as an input signal, generates a sampling signal of a fixed phase with the sampling period of Ts as a reference, and controls the ADC module to trigger sampling as the rest sampling signals in the preset adjustment period Tp;
in the phase adjustment process, the phase adjustment module increases the phase offset of one clock cycle T for the first sampling signal every time, when the total delay of the increased phase reaches the preset adjustment phase number, the phase is reduced, in the phase reduction process, the phase adjustment module reduces the phase offset of one clock cycle T every time until the phase offset is zero, and then the phase adjustment process is repeated to realize the phase jitter.
2. A phase jittered sampling method according to claim 1, wherein a sampling period Ts of the trigger pulse signal generated by said timing trigger module comprises Ts/T clock cycles.
3. A phase jittered sampling method according to claim 1, wherein the phase adjustment module phase adjusts the phase offset of the trigger pulse signal by one clock period T at a time.
4. A phase jittered sampling method according to claim 1, wherein said timing trigger module counts by a programmable logic internal clock period T, generating a trigger pulse signal with a sampling period Ts.
5. A phase jittered sampling method according to claim 1, wherein the period of the sampling signal generated by said fixed phase module is equal to the sampling period Ts of the trigger pulse signal generated by the clocked trigger module.
6. A phase jittering sampling method according to claim 1, wherein, each of said sampling signals in adjusting period Tp includes a phase adjusted sampling signal and the rest of sampling signals with unchanged phase.
7. A phase jitter sampling method as claimed in claim 1, wherein the phase is adjusted only once in an adjustment period Tp, i.e. the first sampling period of the adjustment period Tp, and the remaining sampling periods are kept unchanged in phase, and the predetermined number of adjusted phases is such that the total delay of the increased phases reaches the predetermined number of clock cycles.
8. The method of claim 1, wherein the phase adjustment module generates the phase shift trigger time including a positive shift time T1 and a negative shift time T2 when adjusting the phase, and the specific calculation formula is as follows:
Wherein n represents a bit of the number of adjustment times; n represents the number of adjustments, i.e. the Nth adjustment phase, N ranges from
In the middle of; ts represents the sampling period; t denotes a clock cycle.
9. A phase jittered sampling method according to claim 8, wherein the phase shift comprises a positive shift and a negative shift, the positive shift advancing the phase with respect to the timing trigger block generating the trigger signal; the negative shift is based on the leading phase of the positive shift and then the negative shift, so that the phase returns to the trigger signal which is consistent with the trigger signal generated by the timing trigger module.
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