CN114499468A - Memristor feedback type self-conditioning hyperchaotic waveform generator - Google Patents
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Abstract
The invention discloses a memristor feedback type self-conditioning hyperchaotic waveform generator, which relates to the technical field of electronics, communication and information engineering, and outputs a hyperchaotic signal with adjustable amplitude by adopting a three-way integral summation operation circuit, 2 multiplier circuits and two inverting operation units; the adjusting circuit outputs the value of the amplitude change of the hyperchaotic signal through the resistor of a certain branch circuit to realize amplitude regulation, amplitude control has two control inlets different from other circuits, the flexibility of a hardware circuit is increased, the difficulty of circuit realization and debugging is reduced, and convenience is provided for the application of the hyperchaotic signal to electronics and information engineering.
Description
Technical Field
The invention relates to the technical field of electronics, communication and information engineering, in particular to a memristive feedback type self-conditioning hyperchaotic waveform generator.
Background
The hyperchaotic signal is used as a broadband random signal and has wide application in the fields of fluid stirring, searching and predicting, instruments and meters, communication, radar and the like. Amplification or attenuation of signal amplitude and control of bias applied in engineering are both requirements for signal conditioning and an important aspect for characterizing circuit characteristics. The amplitude and bias change of the hyperchaotic signals are basic tasks of signal preprocessing or conditioning circuits, redundant circuit elements or additional systems can be reduced by constructing the self-conditioning circuit based on system parameters, the purpose of simplifying the circuits is achieved, and the method has important engineering value.
Regarding the generation of self-conditioning chaotic signals, related patents provide corresponding design circuits at present, for example, a patent [ grant No. CN107317668B ] provides a self-conditioning chaotic signal source, amplitude regulation of chaotic signals output by the system is realized through rheostat regulation of a second branch, and polarity control of chaotic signals is realized through regulation of a direct current power supply, but the system does not realize the conditioning of hyperchaos. In addition, a patent No. CN105846991A proposes a simple three-dimensional amplitude-modulated chaotic signal generator, the invention adopts two groups of analog gating gate circuits, outputs a LORENZ-like chaotic attractor with adjustable size through a three-way integral summation operation circuit, and the system can only condition chaotic signals and cannot output hyperchaotic signals.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide a memristor feedback type self-conditioning hyperchaotic waveform generator.
The invention adopts the following technical scheme for solving the technical problems:
the memristor feedback type self-conditioning hyperchaotic waveform generator comprises a memristor, a product operation unit, first to tenth resistors, first to third capacitors, a first integral operation unit, an inverse proportion operation unit, a second integral operation unit, a third integral operation unit and a first direct-current voltage source; wherein,
the output end of the memristor is connected with the input end of the product operation unit, the output end of the product operation unit is connected with one end of the third resistor, the other end of the third resistor is respectively connected with one end of the first resistor, one end of the second resistor, one end of the fourth resistor, one end of the eighth resistor, one end of the first capacitor and the inverting input end of the first integral operation unit, the other end of the eighth resistor is connected with the first direct-current voltage power supply, the other end of the first capacitor is respectively connected with the output end of the first integral operation unit and one end of the ninth resistor, the other end of the ninth resistor is respectively connected with one end of the tenth resistor and the inverting input end of the inverting proportional operation unit, the other end of the tenth resistor is respectively connected with the output end of the inverting proportional operation unit, one end of the seventh resistor and one end of the fifth resistor, and the other end of the seventh resistor is respectively connected with one end of the third capacitor, The inverting input ends of the third integral operation units are respectively connected, the other end of the third capacitor is connected with the output end of the third integral operation unit, the other end of the fifth resistor is respectively connected with one end of the sixth resistor, one end of the second capacitor and the inverting input end of the second integral operation unit, and the other end of the second capacitor is connected with the output end of the second integral operation unit.
As a further optimization scheme of the memristor feedback type self-conditioning hyperchaotic waveform generator, the memristor comprises a first product operation unit, tenth to seventeenth resistors, a fourth capacitor, a second direct-current voltage source, a first operational amplifier, a second operational amplifier, a third operational amplifier and an absolute value circuit; wherein,
one end of a thirteenth resistor is connected with one end of a fourteenth resistor, one end of a fourth capacitor and the inverting input end of the first operational amplifier respectively, the other end of the fourteenth resistor is connected with the output end of the first product operation unit, the output end of the first operational amplifier is connected with one end of a seventeenth resistor, the other end of the seventeenth resistor is connected with one end of an absolute value circuit, the other end of the absolute value circuit is connected with one end of a sixteenth resistor, the other end of the sixteenth resistor is connected with one end of a fifteenth resistor and the inverting input end of the second operational amplifier respectively, the output end of the second operational amplifier is connected with the other end of the fifteenth resistor and one end of an eleventh resistor respectively, the other end of the eleventh resistor is connected with one end of a tenth resistor, one end of a twelfth resistor and the inverting input end of the third operational amplifier respectively, and the other end of the twelfth resistor is connected with a second direct current voltage source, the other end of the tenth resistor is connected with the output end of the third operational amplifier.
As a further optimization scheme of the memristive feedback type self-conditioning hyperchaotic waveform generator, a fourteenth resistor is a variable resistor.
Compared with the prior art, the technical scheme adopted by the invention has the following technical effects:
the invention outputs amplitude-adjustable hyperchaotic signals by a three-way integral summation operation circuit, 2 multiplier circuits and two inverting operation units; the adjusting circuit outputs the value of the amplitude change of the hyperchaotic signal through the resistor of a certain branch circuit, so that amplitude regulation and control are realized, amplitude control has two control inlets different from other circuits, the flexibility of a hardware circuit is improved, the difficulty in circuit realization and debugging is reduced, and convenience is provided for the application of the hyperchaotic signal to electronics and information engineering.
Drawings
FIG. 1 is a signal waveform diagram of a memristive feedback type self-conditioning hyperchaotic waveform generator x (t);
FIG. 2 is a signal waveform diagram of a memristive feedback type self-conditioning hyperchaotic waveform generator y (t);
fig. 3a is a z-x phase rail under the condition of amplitude modulation of a memristive feedback type self-conditioning hyperchaotic waveform generator, and fig. 3b is a signal waveform diagram of z (t) under the condition of amplitude modulation of the memristive feedback type self-conditioning hyperchaotic waveform generator;
FIG. 4 shows phase track and waveform variation under bias of a memristive feedback type self-conditioning hyperchaotic waveform generator; wherein (a) is the change in rail position when n-8, 0, 8; (b) is the change in the track waveform when n-8, 0, 8;
FIG. 5a is a circuit diagram of a memristive feedback type self-conditioning hyper-chaotic waveform generator, and FIG. 5b is a circuit diagram of a memristor;
FIG. 6 is a memristive feedback type self-conditioning hyperchaotic waveform generator experimental simulation oscilloscope phaseA track map; wherein (a) is when the resistance R is regulated9The waveform of the x (t) signal at 10K Ω, and (b) the waveform of the signal when the resistance R is adjusted9A waveform diagram of the x (t) signal at 1K Ω;
FIG. 7 is a circuit simulation diagram of a memristive feedback type self-conditioning hyperchaotic waveform generator; wherein (a) is when the resistance R is regulated9The waveform of the y (t) signal at 10K omega, and (b) when the resistance R is adjusted9Waveform diagram of the signal y (t) at 1K Ω.
FIG. 8 is a circuit simulation diagram of phase rail and waveform variation of amplitude modulation characteristics of a memristive feedback type self-conditioning hyperchaotic waveform generator; wherein (a) is when the resistance R is regulated9A z-x phase rail at 10K Ω, and (b) is when the resistance R is adjusted9A z-x phase rail at 1K Ω, and (c) is when the resistance R is adjusted9The waveform of z (t) signal at 10K Ω, and (d) when the resistance R is adjusted9Waveform diagram of z (t) signal at 1K Ω.
Fig. 9 is a simulation diagram of a phase-rail and waveform change circuit of the memristive feedback type self-conditioning hyperchaotic waveform generator bias characteristic: wherein (a), (b) and (c) are each when V2Change in rail position at 1.5, 0, -1.5; (d) when each of (e) and (f) is V21.5, 0, -1.5 phase track waveform change.
Detailed Description
The technical scheme of the invention is further explained in detail by combining the attached drawings:
a memristor feedback type self-conditioning hyperchaotic waveform generator comprises a memristor W (u) and a product operation unit M3First to tenth resistors R1-R7、R0、R13、R14First to third capacitors C1-C3A first integral operation unit U1Inverse proportion operation unit U2A second integral operation unit U3A third integral operation unit U5A first DC voltage source V2(ii) a Wherein,
the output end of the memristor is connected with the input end of the product operation unit, the output end of the product operation unit is connected with one end of the third resistor, the other end of the third resistor is respectively connected with one end of the first resistor, one end of the second resistor, one end of the fourth resistor, one end of the eighth resistor, one end of the first capacitor and the inverting input end of the first integral operation unit, the other end of the eighth resistor is connected with the first direct-current voltage power supply, the other end of the first capacitor is respectively connected with the output end of the first integral operation unit and one end of the ninth resistor, the other end of the ninth resistor is respectively connected with one end of the tenth resistor and the inverting input end of the inverting proportional operation unit, the other end of the tenth resistor is respectively connected with the output end of the inverting proportional operation unit, one end of the seventh resistor and one end of the fifth resistor, and the other end of the seventh resistor is respectively connected with one end of the third capacitor, The inverting input ends of the third integral operation units are respectively connected, the other end of the third capacitor is connected with the output end of the third integral operation unit, the other end of the fifth resistor is respectively connected with one end of the sixth resistor, one end of the second capacitor and the inverting input end of the second integral operation unit, and the other end of the second capacitor is connected with the output end of the second integral operation unit.
The memristor comprises a first product operation unit, tenth to seventeenth resistors R10、R11、R12、R8、R9、R15、R16、R17A fourth capacitor C4A second DC voltage source V1A first operational amplifier U6A second operational amplifier U4A third operational amplifier U9And an absolute value circuit; wherein,
one end of a thirteenth resistor is connected with one end of a fourteenth resistor, one end of a fourth capacitor and the inverting input end of the first operational amplifier respectively, the other end of the fourteenth resistor is connected with the output end of the first product operation unit, the output end of the first operational amplifier is connected with one end of a seventeenth resistor, the other end of the seventeenth resistor is connected with one end of an absolute value circuit, the other end of the absolute value circuit is connected with one end of a sixteenth resistor, the other end of the sixteenth resistor is connected with one end of a fifteenth resistor and the inverting input end of the second operational amplifier respectively, the output end of the second operational amplifier is connected with the other end of the fifteenth resistor and one end of an eleventh resistor respectively, the other end of the eleventh resistor is connected with one end of a tenth resistor, one end of a twelfth resistor and the inverting input end of the third operational amplifier respectively, and the other end of the twelfth resistor is connected with a second direct current voltage source, the other end of the tenth resistor is connected with the output end of the third operational amplifier.
The fourteenth resistor is a variable resistor.
The oscillation behavior of the system can be adjusted by the connection resistance of the corresponding branch. The memristive hyper-chaotic circuit designed by the invention has a more complex structure and dynamic behavior, can better meet the requirements of safe communication and information encryption, and is beneficial to developing pseudo-random number generators and secret communication systems based on chaotic engineering application.
The memristor is a novel nonlinear element, and has become a novel circuit element commonly used for constructing a chaotic system due to introduction of nonlinear feedback. Many circuits introduce memristors to obtain hyperchaos and study the multistable behavior caused by memristors. In recent years, with the development of memristor concepts and devices, some classical systems and other dynamical systems have successfully converted into memristive systems. The generation of the memristor hyperchaotic signal has important theoretical, physical significance and engineering value. The invention provides a hyperchaotic memristor circuit, which outputs hyperchaotic by introducing memristor feedback and combining a plurality of resistors and four capacitors by means of two multipliers and nine operational amplifiers. The amplitude of the hyperchaotic signal is controlled by the resistance of a certain branch circuit, and the bias control of the chaotic signal is realized by the adjustment of a direct current power supply.
The memristor feedback type self-conditioning hyperchaotic waveform generator takes an integrating circuit with four branches as a frame, and outputs four paths of hyperchaotic signals by combining a plurality of resistors and four capacitors through two multipliers and nine operational amplifiers. The amplitude of the hyperchaotic signal is adjusted by the resistance on the memristive nonlinear feedback branch circuit.
In the memristive feedback type self-conditioning hyperchaotic waveform generator, a first branch comprises five input ends and a direct-current voltage source V2D.C. voltage source V2One end of the first connecting rod is grounded, and the other end is connected with R0And U1Are connected to each other. Wherein the input signals-x, y and z respectively passResistance R1Resistance R2Resistance R4Connecting integral arithmetic unit U1An input terminal of (1); an input signal x is connected with a memristor W (u), x W (u) items are output, and the input signals-x and x W (u) pass through a product operation unit M3Connection R3And integral operation unit U1Is connected to an integral arithmetic unit U1The output end output signal x is connected with an inverse proportion operation unit U2Inverse proportional arithmetic unit U2The output terminal outputs a signal-x. The second branch comprises two input terminals, two input signals-x and y of which are respectively passed through a resistor R5And a resistance R6Is connected with an integral operation unit U3Integral arithmetic unit U3The output terminal outputs a signal y, and the input signal-x of the second branch is the output signal of the first branch. The third branch has only one input end, that is, the output signal-x of the first branch is used as the input signal of the third branch and is connected with the integrating operation circuit U5 through the resistor R7, and the output end of the integrating operation circuit U5 outputs the signal z.
The input signal x in the first branch is connected to a memristor W (u), and W (u) comprises a resistor R8Resistance R9Resistance R10Resistance R11Resistance R12Resistance R15Resistance R16Resistance R17Resistance R18Resistance R19Resistance R20Resistance R21Capacitor C4Operational amplifier U2Operational amplifier U6Operational amplifier U4Operational amplifier U8Operational amplifier U9Product operation unit, diode D1Diode D2D.C. voltage source V1。
The first branch comprises an integral operation unit U1Inverse proportion operation unit U2DC voltage source V2Resistance R0Resistance R1Resistance R2Resistance R3And a resistor R4Resistance R13Resistance R14And a capacitor C1Product unit M3Wherein the output terminal of the second branch passes through a resistor R2Is connected with an integral operation unit U1The inverting input terminal of (1), an integral operation unit U1In phase with the inputEnd-grounded integral operation unit U1And the inverting input terminal and the capacitor C of1Is connected to one terminal of a capacitor C1And the other end of (1) and an integral operation unit U1Is connected to the output terminal via a resistor R13Connected with an inverse phase proportion operation unit U2The inverse proportion operation unit U2The non-inverting input end of the operational amplifier is grounded, and the inverse proportion operation unit U2And the resistor R13Is connected to one end of the first branch and a resistor R in the second branch5And an inverse proportion operation unit U2I.e. to the output of the first branch.
The second branch comprises an integral operation unit U3Resistance R5Resistance R6And a capacitor C2Wherein, an integral operation unit U2The non-inverting input end of the operational amplifier is grounded, and an integral operation unit U2And the inverting input terminal and the capacitor C of2Is connected to one terminal of a capacitor C2Is passed through a resistor R6Receiving an input signal y while passing through a resistor R5And receiving an input signal-x, wherein the input signal-x is an output signal of the first branch.
The third branch comprises an integral operation unit U5Resistance R7And a capacitor C3Wherein the resistance R7Is connected with an integral operation unit U3The inverting input terminal of (1), an integral operation unit U3And the inverting input terminal and the capacitor C of3Is connected to one terminal of a capacitor C3And the other end of (1) and an integral operation unit U3And the output end of the third branch circuit is connected with the output end of the third branch circuit.
The amplitude of the output hyperchaotic signal of the memristive feedback type self-conditioning hyperchaotic waveform generator can be changed by adjusting the resistance R of the first branch3Is achieved by the value of (c).
Fig. 3a is a z-x phase orbit under the condition of amplitude modulation of a memristive feedback type self-conditioning hyperchaotic waveform generator, and fig. 3b is a signal waveform diagram of z (t) under the condition of amplitude modulation of the memristive feedback type self-conditioning hyperchaotic waveform generator; FIG. 4 shows phase track and waveform variation under bias of a memristive feedback type self-conditioning hyperchaotic waveform generator; wherein (a) in fig. 4 is a case where n is-8, 0,8-time rail position change; fig. 4 (b) is a change of the track waveform when n is-8, 0, 8; FIG. 5a is a circuit diagram of a memristive feedback type self-conditioning hyper-chaotic waveform generator, and FIG. 5b is a circuit diagram of a memristor; wherein, C1＝C2＝C3＝10nF,R1＝R2＝22.22kΩ,R3＝10kΩ,R4＝100kΩ,R5＝R6＝18.18kΩ,R7＝500kΩ,R13＝R14The equivalent circuit parameter of the corresponding memristive element is C4＝10nF,R8＝250kΩ,R9＝R10＝R12＝R15＝R16＝10kΩ,R11＝2.5kΩ。
FIG. 6 is a phase rail diagram of a memristive feedback type self-conditioning hyperchaotic waveform generator experimental simulation oscilloscope; wherein (a) in FIG. 6 is when the resistance R is adjusted9The waveform of the x (t) signal at 10K Ω, and (b) in FIG. 6 is the waveform when the resistance R is adjusted9A waveform diagram of the x (t) signal at 1K Ω;
FIG. 7 is a circuit simulation diagram of a memristive feedback type self-conditioning hyperchaotic waveform generator; wherein (a) in FIG. 7 is when the resistance R is adjusted9A waveform diagram of the y (t) signal at 10 K.OMEGA., (b) in FIG. 7 is a waveform diagram when the resistance R is adjusted9Waveform diagram of the signal y (t) at 1K Ω.
FIG. 8 is a circuit simulation diagram of phase rail and waveform variation of amplitude modulation characteristics of a memristive feedback type self-conditioning hyperchaotic waveform generator; wherein (a) in FIG. 8 is when the resistance R is adjusted9A z-x phase rail at 10 K.OMEGA. (b) in FIG. 8 is when the resistance R is adjusted9Z-x phase rail at 1 K.OMEGA., (c) in FIG. 8 is when the resistance R is adjusted9The waveform of the z (t) signal at 10 K.OMEGA. (d) in FIG. 8 is the waveform when the resistance R is adjusted9Waveform diagram of z (t) signal at 1K Ω.
Fig. 9 is a simulation diagram of a phase-rail and waveform change circuit of the memristive feedback type self-conditioning hyperchaotic waveform generator bias characteristic: wherein (a), (b) and (c) in FIG. 9 are each when V2Change in rail position at 1.5, 0, -1.5; in FIG. 9, (d), (e), (f) are each when V21.5, 0, -1.5 phase track waveform change.
(1) Dynamic equation and circuit structure of memristive feedback type self-conditioning hyperchaotic waveform generator
The hyper-chaotic memristive circuit of the present invention may be described by the following dynamical system equations,
the memristor equation is as follows:
the equation formally comprises eight primary linear feedbacks, one secondary nonlinear feedback and one internal nonlinear feedback, and one constant term for bias regulation. When a is 11, b is 154, c is 14, D is 1.25, e is 1, m is 1, and IC is (1,0,0,1), the hyper-chaotic attractor output by the system has the lyapunov exponent of (0.5997,0.0529,0, -5.3768), and D is DKY＝3.1214。
The system can be realized by a closed feedback system consisting of three branches, when a three-way integral summation operation loop is adopted for realizing, a circuit diagram is shown in fig. 2, fig. 1 is a signal waveform diagram of a memristive feedback type self-conditioning hyperchaotic waveform generator x (t), wherein a is 11, b is 154, c is 14, d is 1.25, e is 1, and IC is 1001; fig. 2 is a signal waveform diagram of a memristive feedback type self-conditioning hyperchaotic waveform generator y (t), wherein a is 11, b is 154, c is 14, d is 1.25, e is 1, and IC is 1001. The above mathematical equations are converted into more specific circuit equations,
circuit equations and system dynamicsThe equations are consistent. Here, the coefficients of the various feedback terms in the system are implemented by resistor settings, while the coefficient m of the linear term enables amplitude control of the signal, which can be achieved by resistor R3To be implemented.
The first branch comprises an integral operation unit U1Inverse proportion operation unit U2DC voltage source V2Resistance R0Resistance R1Resistance R2Resistance R3Resistance R4Resistance R13Resistance R14And a capacitor C1Product unit M3Wherein the output terminal of the second branch passes through a resistor R2Connect and add integral arithmetic unit U1The inverting input terminal of (1), an integral operation unit U1The non-inverting input end of the operational amplifier is grounded, and a summation integral operation unit U1And the inverting input terminal and the capacitor C of1Is connected to one terminal of a capacitor C1And a summation-integration operation unit U1Is connected to the output terminal via a resistor R13Connected with an inverse phase proportion operation unit U2The inverse proportion operation unit U2The same-phase input end of the operational unit U is grounded and the inverse proportion of the operational unit U is calculated2And the resistor R13Is connected to one end of the first branch and a resistor R in the second branch5And an inverse proportion operation unit U2I.e. to the output of the first branch. The first branch comprises five inputs, wherein the input signals-x, y and z are respectively passed through a resistor R1Resistance R2Resistance R4Connecting integral arithmetic unit U1An input terminal of (1); an input signal x is connected with a memristor W (u), x W (u) items are output, and the input signals-x and x W (u) pass through a product operation unit M3Connection R3And integral operation unit U1Is connected to an integral arithmetic unit U1The output end output signal x is connected with an inverse proportion operation unit U2Inverse proportional arithmetic unit U2The output terminal outputs a signal-x.
The second branch comprises an integral operation unit U3Resistance R5Resistance R6And a capacitor C2Wherein, an integral operation unitU2The non-inverting input end of the operational amplifier is grounded, and an integral operation unit U2And the inverting input terminal and the capacitor C of2Is connected to one terminal of a capacitor C2Is passed through a resistor R6Receiving an input signal y while passing through a resistor R5And receiving an input signal-x, wherein the input signal-x is an output signal of the first branch. The second branch comprises two input terminals, two input signals-x and y of which are respectively passed through a resistor R5And a resistance R6Is connected with an integral operation unit U3Integral arithmetic unit U3The output terminal outputs a signal y, and the input signal-x of the second branch is the output signal of the first branch.
The third branch comprises an integral operation unit U5Resistance R7And a capacitor C3Wherein the resistance R7Connect and add integral arithmetic unit U3The inverting input terminal of (1), an integral operation unit U3And the inverting input terminal and the capacitor C of3Is connected to one terminal of a capacitor C3And the other end of (1) and an integral operation unit U3And the output end of the third branch is connected with the output end of the third branch. The third branch has only one input end, i.e. the output signal-x of the first branch is used as the input signal of the third branch to pass through the resistor R7Connecting integral arithmetic unit U5Integral arithmetic unit U5Outputs a signal z.
(2) Amplitude control method
The memristor feedback type self-conditioning hyperchaotic waveform generator is characterized in that the output hyperchaotic signal is provided with a non-branching knob for amplitude control and can pass through a rheostat R9Is achieved. When the coefficient m is introduced, the amplitude of the output three-dimensional chaotic signal also changes along with it, which can be represented by x → hx, y → hy, z → hz, u → u, t → t (h > 0), which leaves only one additional coefficient in three-dimensional space:
it can be seen that the parameter m varies
The amplitudes of the signals x, y and z can be controlled, and the amplitude of u can be kept unchanged without any influence of the frequencies of all the signals
(3) Bias control method
The memristive feedback type self-conditioning hyperchaotic waveform generator is characterized in that the output hyperchaotic signal is provided with a non-branching knob for bias control and can pass through V2Is achieved, as can be seen from equation (1), x → x, y → y, z → z-n, u → u, t → t, the system equation becomes:
therefore, the polarity change of the chaotic signal in the z-axis direction can be controlled by introducing a direct current feedback term n into a system equation, and V is used in a circuit equation2And (5) controlling.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.
Claims (3)
1. A memristor feedback type self-conditioning hyperchaotic waveform generator is characterized by comprising a memristor, a product operation unit, first to tenth resistors, first to third capacitors, a first integral operation unit, an inverse proportion operation unit, a second integral operation unit, a third integral operation unit and a first direct-current voltage source; wherein,
the output end of the memristor is connected with the input end of the product operation unit, the output end of the product operation unit is connected with one end of the third resistor, the other end of the third resistor is respectively connected with one end of the first resistor, one end of the second resistor, one end of the fourth resistor, one end of the eighth resistor, one end of the first capacitor and the inverting input end of the first integral operation unit, the other end of the eighth resistor is connected with the first direct-current voltage power supply, the other end of the first capacitor is respectively connected with the output end of the first integral operation unit and one end of the ninth resistor, the other end of the ninth resistor is respectively connected with one end of the tenth resistor and the inverting input end of the inverting proportional operation unit, the other end of the tenth resistor is respectively connected with the output end of the inverting proportional operation unit, one end of the seventh resistor and one end of the fifth resistor, and the other end of the seventh resistor is respectively connected with one end of the third capacitor, The inverting input ends of the third integral operation units are respectively connected, the other end of the third capacitor is connected with the output end of the third integral operation unit, the other end of the fifth resistor is respectively connected with one end of the sixth resistor, one end of the second capacitor and the inverting input end of the second integral operation unit, and the other end of the second capacitor is connected with the output end of the second integral operation unit.
2. The memristor feedback type self-conditioning hyperchaotic waveform generator according to claim 1, wherein the memristor comprises a first product operation unit, tenth to seventeenth resistors, a fourth capacitor, a second direct current voltage source, a first operational amplifier, a second operational amplifier, a third operational amplifier and an absolute value circuit; wherein,
one end of a thirteenth resistor is connected with one end of a fourteenth resistor, one end of a fourth capacitor and the inverting input end of the first operational amplifier respectively, the other end of the fourteenth resistor is connected with the output end of the first product operation unit, the output end of the first operational amplifier is connected with one end of a seventeenth resistor, the other end of the seventeenth resistor is connected with one end of an absolute value circuit, the other end of the absolute value circuit is connected with one end of a sixteenth resistor, the other end of the sixteenth resistor is connected with one end of a fifteenth resistor and the inverting input end of the second operational amplifier respectively, the output end of the second operational amplifier is connected with the other end of the fifteenth resistor and one end of an eleventh resistor respectively, the other end of the eleventh resistor is connected with one end of a tenth resistor, one end of a twelfth resistor and the inverting input end of the third operational amplifier respectively, and the other end of the twelfth resistor is connected with a second direct current voltage source, the other end of the tenth resistor is connected with the output end of the third operational amplifier.
3. The memristive feedback type self-conditioning hyperchaotic waveform generator according to claim 2, wherein the fourteenth resistor is a variable resistor.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116155242A (en) * | 2023-04-17 | 2023-05-23 | 南京信息工程大学 | Amplitude modulation and frequency modulation chaotic waveform generator without operational amplifier |
| CN118157635A (en) * | 2024-05-09 | 2024-06-07 | 南京信息工程大学 | Simple chaotic oscillator and regulation and control method |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116155242A (en) * | 2023-04-17 | 2023-05-23 | 南京信息工程大学 | Amplitude modulation and frequency modulation chaotic waveform generator without operational amplifier |
| CN118157635A (en) * | 2024-05-09 | 2024-06-07 | 南京信息工程大学 | Simple chaotic oscillator and regulation and control method |
| CN118157635B (en) * | 2024-05-09 | 2024-07-09 | 南京信息工程大学 | Simple chaotic oscillator and regulation and control method |
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