CN114499453A - Quality factor enhanced active filter and electronic equipment - Google Patents

Abstract

The invention discloses a quality factor enhanced active filter and electronic equipment, and relates to the technical field of integrated circuit band-pass filters. The method comprises the following steps: the first second-order quality factor enhancement active filter circuit and the second-order quality factor enhancement active filter circuit are respectively and electrically connected with the subtraction circuit; the first second-order quality factor enhancement active filter circuit and the second-order quality factor enhancement active filter respectively comprise a variable gain sub-circuit, an inductance-capacitance parallel harmonic oscillator circuit and a negative resistance feedback sub-circuit which are electrically connected in pairs; the subtraction circuit is connected with the variable gain sub-circuit; the method has the technical effects of large gain adjustment range, unchanged central frequency point when the gain and Q value are adjusted, tunable central frequency, good rectangular coefficient and high linearity, is convenient and integrated, and can be used in radio frequency front-end equipment.

Description

Quality factor enhancement active filter and electronic equipment

Technical Field

The invention relates to the technical field of integrated circuit band-pass filters, in particular to a quality factor enhanced active filter and electronic equipment.

Background

With the increasing of the technological level of CMOS (Complementary Metal-Oxide-Semiconductor), the feature size is decreasing, the transistor feature frequency is increasing, and the noise figure and linearity are improved to some extent. Meanwhile, the CMOS process is a future development trend of the rf integrated circuit due to its advantages of low cost, low power consumption, miniaturization, high integration, high reliability, and the like. The area of the chip is precious, the number of the radio frequency front-end filters can be greatly reduced by using the on-chip reconfigurable filter, and meanwhile, the interference problem can be solved as early as possible by using high frequency selectivity in a receiver chain.

At present, the inductance L has a smaller size and a larger quality factor at high frequency in a quality factor (Q) enhancement filter, so that an on-chip integrated filter based on a Q enhancement LC resonant cavity (a circuit which is formed after connecting an inductor and a capacitor and is in a resonant state) is very attractive. Among these, the tunability of the Q enhancement filter is very important, especially the tunability of the gain, Q value and center frequency.

However, the traditional Q enhancement filter has a small adjustment gain range and low adjustment precision, and reduces the reliability and stability of the Q enhancement filter.

Disclosure of Invention

The invention aims to provide a quality factor enhancement active filter and electronic equipment, and aims to solve the problems that the existing Q enhancement filter is small in gain adjustment range and low in adjustment precision, and the reliability and stability of the Q enhancement filter are reduced.

In a first aspect, the present invention provides a quality factor enhanced active filter, comprising:

the filter comprises a subtraction circuit, a first second-order quality factor enhancement active filter circuit and a second-order quality factor enhancement active filter circuit, wherein the first second-order quality factor enhancement active filter circuit and the second-order quality factor enhancement active filter circuit are respectively electrically connected with the subtraction circuit;

the first second-order quality factor enhancement active filter circuit and the second-order quality factor enhancement active filter respectively comprise a variable gain sub-circuit, an inductance-capacitance parallel harmonic oscillator circuit and a negative resistance feedback sub-circuit which are electrically connected in pairs; the subtraction circuit is connected with the variable gain sub-circuit;

the subtraction circuit is used for increasing the band-pass filtering frequency selectivity of the first second-order quality factor enhancement active filter circuit and the second-order quality factor enhancement active filter circuit to fourth order and increasing the rectangular coefficient of the quality factor enhancement active filter;

the two variable gain sub-circuits both adopt a cascode structure and are used for adjusting the gain of the quality factor enhancement active filter circuit in a larger range and inhibiting the drift of a central frequency point;

the inductance-capacitance parallel harmonic oscillator circuit is used for realizing the adjustment control of the resonance center frequency by changing the capacitance value of the inductance-capacitance parallel harmonic oscillator circuit;

the negative resistance feedback sub-circuit is used for adjusting the quality factor of the active filter.

Under the condition of adopting the technical scheme, the quality factor enhancement active filter provided by the embodiment of the invention comprises a subtraction circuit, and a first second-order quality factor enhancement active filter circuit and a second-order quality factor enhancement active filter circuit which are respectively and electrically connected with the subtraction circuit; the first second-order quality factor enhancement active filter circuit and the second-order quality factor enhancement active filter respectively comprise a variable gain sub-circuit, an inductance-capacitance parallel harmonic oscillator circuit and a negative resistance feedback sub-circuit which are electrically connected in pairs; the subtraction circuit is connected with the variable gain sub-circuit; the subtraction circuit is used for increasing the band-pass filtering frequency selectivity of the first second-order quality factor enhancement active filter circuit and the second-order quality factor enhancement active filter circuit to fourth order and increasing the rectangular coefficient of the quality factor enhancement active filter; the two variable gain sub-circuits both adopt a cascode structure and are used for adjusting the gain of the quality factor enhancement active filter circuit in a larger range and inhibiting the drift of a central frequency point; the inductance-capacitance parallel harmonic oscillator circuit is used for realizing the adjustment control of the resonance center frequency by changing the capacitance value of the inductance-capacitance parallel harmonic oscillator circuit; the negative resistance feedback sub-circuit is used for adjusting the quality factor of the active filter, so that the active filter has the technical effects of large gain adjustment range, unchanged central frequency point when the gain and Q value are adjusted, tunable central frequency, good rectangular coefficient and high linearity, is convenient to integrate, and can be used in radio frequency front-end equipment.

In a possible implementation manner, the common gate of the cascode structure corresponding to the variable gain sub-circuit in the two second-order quality factor enhancement active filter circuits is connected to a control voltage, the drain of the cascode structure is connected in parallel to the inductance-capacitance parallel resonator sub-circuit and the negative resistance feedback sub-circuit, the source of the cascode structure is connected to a tail current source, and the tail current source is implemented by a fixed-bias N-type common-source metal oxide semiconductor transistor.

In a possible implementation manner, the current source and the two transistors in the two second-order quality factor enhancement active filter circuits form a negative resistance feedback sub-circuit, the current source is implemented by an N-type common-source metal oxide semiconductor transistor, and the change of the current is implemented by changing the gate voltage of the N-type common-source metal oxide semiconductor transistor, so as to control the change of the quality factor.

In one possible implementation, the subtraction circuit includes a fifteenth common-source transistor, a sixteenth common-source transistor, a seventeenth common-source transistor, and an eighteenth common-source transistor;

the drain of the fifteenth common-source transistor is connected with the source of the seventeenth common-source transistor and the output port respectively, the source of the fifteenth common-source transistor is connected with the ground, the drain of the sixteenth common-source transistor is connected with the source of the eighteenth common-source transistor and the output port respectively, the source of the sixteenth common-source transistor is connected with the ground, the source of the seventeenth common-source transistor is connected with the power supply, and the source of the eighteenth common-source transistor is connected with the power supply.

In one possible implementation manner, the variable gain sub-circuit corresponding to the first second-order quality factor enhancing active filter circuit includes a first common source transistor, a second common source transistor, a third common gate transistor, a fourth common gate transistor, and a first current source; the variable gain sub-circuit corresponding to the second order quality factor enhancement active filter circuit comprises: the power supply comprises an eighth common-source transistor, a ninth common-gate transistor, a tenth common-gate transistor, an eleventh common-gate transistor and a second current source;

the first common-source transistor and the second common-source transistor are used for inputting differential radio-frequency signals, the drain electrode of the first common-source transistor and the drain electrode of the second common-source transistor are respectively connected with the source electrode of the third common-gate transistor and the source electrode of the fourth common-gate transistor, the other end of the first common-source transistor and the drain electrode of the second common-source transistor are connected with the first current source, and the grid electrodes of the third common-gate transistor and the fourth common-gate transistor are connected with a first resistor control voltage; the eighth common-source transistor and the ninth common-source transistor are used for inputting differential radio-frequency signals, a drain electrode of the eighth common-source transistor and a drain electrode of the ninth common-source transistor are respectively connected with a source electrode of the tenth common-gate transistor and a source electrode of the eleventh common-gate transistor, the other end of the eighth common-source transistor and the drain electrode of the ninth common-source transistor are connected with the second current source, and grid electrodes of the tenth common-gate transistor and the tenth common-gate transistor are connected with a second resistor control voltage;

the drains of the third common-gate transistor and the fourth common-gate transistor are connected with the corresponding inductive-capacitor parallel harmonic oscillator circuit, one end of the corresponding negative resistance feedback sub-circuit is connected with the inductive-capacitor parallel harmonic oscillator circuit, and the other end of the corresponding negative resistance feedback sub-circuit is connected with the first current source;

the drains of the tenth common-gate transistor and the eleventh common-gate transistor are connected with the corresponding parallel resonant sub-circuit of the inductance and the capacitance, one end of the corresponding negative resistance feedback sub-circuit is connected with the parallel resonant sub-circuit of the inductance and the capacitance, and the other end of the corresponding negative resistance feedback sub-circuit is connected with the second current source;

the gate of the seventeenth common-source transistor is connected with the drain of the tenth common-gate transistor, the gate of the fifteenth common-source transistor is connected with the drain of the third common-gate transistor, the gate of the sixteenth common-source transistor is connected with the drain of the fourth common-gate transistor, and the gate of the eighteenth common-source transistor is connected with the drain of the eleventh common-gate transistor.

In a possible implementation manner, the first common-source transistor, the second common-source transistor, the eighth common-source transistor, and the ninth common-source transistor all operate in a linear region, the third common-gate transistor, the fourth common-gate transistor, the tenth common-gate transistor, and the eleventh common-gate transistor operate in a saturation region, the first resistance control voltage and the second resistance control voltage are changed, transconductance of the first common-source transistor, the second common-source transistor, the eighth common-source transistor, and the ninth common-source transistor changes exponentially with the control voltage, load resistance and current remain unchanged, voltage gain of the circuit changes, and thus gain control is achieved, and linearity is improved by using the first current source and the second current source.

In one possible implementation manner, the inductance-capacitance parallel resonant sub-circuit comprises a first variable capacitor, a second variable capacitor, a third variable capacitor, a fourth variable capacitor, a capacitor array, a first inductor and a second inductor;

the two ends of the first inductor are connected with the capacitor array and the first variable capacitor and the second variable capacitor which are connected in series in parallel, a central plug is connected with a power supply, a first capacitor control voltage is connected with the junction of the first variable capacitor and the second variable capacitor, the two ends of the second inductor are connected with the capacitor array and the third variable capacitor and the fourth variable capacitor which are connected in series in parallel, the central plug is connected with a nineteenth common-source transistor with a short-circuited drain electrode and a grid electrode and the power supply in series, and a second capacitor control voltage is connected with the junction of the third variable capacitor and the fourth variable capacitor.

In one possible implementation, the negative-resistance feedback sub-circuit includes a fifth common-source transistor, a sixth common-source transistor, a seventh common-source transistor, a twelfth common-source transistor, a thirteenth common-source transistor, and a fourteenth common-source transistor;

a drain of the sixth common-source transistor is connected to a gate of the seventh common-source transistor, a source of the sixth common-source transistor is connected to a drain of the fifth common-source transistor, a drain of the seventh common-source transistor is connected to a gate of the sixth common-source transistor, a source of the seventh common-source transistor is connected to a drain of the fifth common-source transistor, a source of the fifth common-source transistor is connected to ground, a gate of the fifth common-source transistor is connected to the first current control voltage, a drain of the thirteenth common-source transistor is connected to a gate of the fourteenth common-source transistor, a source of the thirteenth common-source transistor is connected to a drain of the twelfth common-source transistor, a drain of the fourteenth common-source transistor is connected to a gate of the thirteenth common-source transistor, and a source of the fourteenth common-source transistor is connected to a drain of the twelfth common-source transistor, the source electrode of the twelfth common-source transistor is connected with the ground, and the grid electrode of the twelfth common-source transistor is connected with the second current control voltage.

In a possible implementation manner, the first common-source transistor, the second common-source transistor, the third common-source transistor, the fourth common-source transistor, the fifth common-source transistor, the sixth common-source transistor, the seventh common-source transistor, the eighth common-source transistor, the ninth common-source transistor, the tenth common-source transistor, the eleventh common-source transistor, the twelfth common-source transistor, the thirteenth common-source transistor, the fourteenth common-source transistor, the fifteenth common-source transistor, the sixteenth common-source transistor, the seventeenth common-source transistor, and the eighteenth common-source transistor are all N-type metal oxide semiconductor transistors, and the substrates are all connected to the corresponding ground;

the nineteenth common-source transistor is a P-type metal oxide semiconductor transistor, and the substrate is connected with a corresponding power supply.

In a second aspect, the present invention also provides an electronic device, comprising: one or more processors; and one or more machine readable media having instructions stored thereon that, when executed by the one or more processors, cause the apparatus to perform the quality factor enhancing active filter described in any of the possible implementations of the first aspect.

The beneficial effect of the electronic device provided by the second aspect is the same as that of the quality factor enhancing active filter described in the first aspect or any possible implementation manner of the first aspect, and details are not repeated here.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:

fig. 1 is a schematic diagram illustrating an overall circuit structure of a quality factor enhancing active filter according to an embodiment of the present application;

fig. 2 is a schematic circuit diagram illustrating a first second-order quality factor enhancing active filter circuit according to an embodiment of the present disclosure;

fig. 3 is a schematic diagram illustrating a simulation curve with a constant center frequency point when a gain of a Q-enhanced active filter is adjusted according to an embodiment of the present application;

fig. 4 shows a simulation diagram of tunable filter center frequency of a Q-enhanced active filter provided by an embodiment of the present application;

fig. 5 shows a simulation diagram of a tunable Q-enhanced active filter with a center frequency of 3GHz bandwidth provided by an embodiment of the present application;

fig. 6 is a data diagram illustrating simulation data of a Q-enhanced active filter provided by an embodiment of the present application;

fig. 7 is a schematic diagram of a hardware structure of an electronic device according to an embodiment of the present invention;

fig. 8 is a schematic structural diagram of a chip according to an embodiment of the present invention.

Description of the drawings:

01-a subtraction circuit; 02-a first second order quality factor enhancing active filter circuit; 03-a second order quality factor enhancing active filter circuit; a-a variable gain sub-circuit; b, an inductance capacitor is connected with the harmonic oscillator circuit in parallel; c-negative resistance feedback sub-circuit.

Detailed Description

In order to facilitate clear description of technical solutions of the embodiments of the present invention, in the embodiments of the present invention, terms such as "first" and "second" are used to distinguish the same items or similar items having substantially the same functions and actions. For example, the first threshold and the second threshold are only used for distinguishing different thresholds, and the sequence order of the thresholds is not limited. Those skilled in the art will appreciate that the terms "first," "second," etc. do not denote any order or quantity, nor do the terms "first," "second," etc. denote any order or importance.

It is to be understood that the terms "exemplary" or "such as" are used herein to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g.," is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present concepts related in a concrete fashion.

In the present invention, "at least one" means one or more, "a plurality" means two or more. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone, wherein A and B can be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of the singular or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, a and b combination, a and c combination, b and c combination, or a, b and c combination, wherein a, b and c can be single or multiple.

Fig. 1 is a schematic diagram illustrating an overall circuit structure of a quality factor enhancement active filter according to an embodiment of the present application, where the quality factor enhancement active filter includes:

a subtraction circuit 01, and a first second-order quality factor enhancement active filter circuit 02 and a second-order quality factor enhancement active filter circuit 03 electrically connected to the subtraction circuit 01, respectively;

the first second-order quality factor enhancing active filter circuit 02 and the second-order quality factor enhancing active filter 03 both comprise a variable gain sub-circuit A, an inductance-capacitance parallel resonant sub-circuit B and a negative resistance feedback sub-circuit C which are electrically connected in pairs; the subtraction circuit 01 is connected to the variable gain sub-circuit a.

The subtraction circuit is used for increasing the band-pass filtering frequency selectivity of the first second-order quality factor enhancement active filter circuit and the second-order quality factor enhancement active filter circuit to fourth order and increasing the rectangular coefficient of the quality factor enhancement active filter;

the two variable gain sub-circuits both adopt a cascode structure and are used for adjusting the gain of the quality factor enhancement active filter circuit in a larger range and inhibiting the drift of a central frequency point;

the inductance-capacitance parallel harmonic oscillator circuit is used for realizing the adjustment control of the resonance center frequency by changing the capacitance value of the inductance-capacitance parallel harmonic oscillator circuit;

the negative resistance feedback sub-circuit is used for adjusting the quality factor of the active filter.

The quality factor enhancement active filter provided by the embodiment of the invention comprises a subtraction circuit, and a first second-order quality factor enhancement active filter circuit and a second-order quality factor enhancement active filter circuit which are respectively electrically connected with the subtraction circuit; the first second-order quality factor enhancement active filter circuit and the second-order quality factor enhancement active filter respectively comprise a variable gain sub-circuit, an inductance-capacitance parallel harmonic oscillator circuit and a negative resistance feedback sub-circuit which are electrically connected in pairs; the subtraction circuit is connected with the variable gain sub-circuit; the subtraction circuit is used for increasing the band-pass filtering frequency selectivity of the first second-order quality factor enhancement active filter circuit and the second-order quality factor enhancement active filter circuit to fourth order and increasing the rectangular coefficient of the quality factor enhancement active filter; the two variable gain sub-circuits both adopt a cascode structure and are used for adjusting the gain of the quality factor enhancement active filter circuit in a larger range and inhibiting the drift of a central frequency point; the inductance-capacitance parallel harmonic oscillator circuit is used for realizing the adjustment control of the resonance center frequency by changing the capacitance value of the inductance-capacitance parallel harmonic oscillator circuit; the negative resistance feedback sub-circuit is used for adjusting the quality factor of the active filter, so that the active filter has the technical effects of large gain adjustment range, unchanged central frequency point when the gain and Q value are adjusted, tunable central frequency, good rectangular coefficient and high linearity, is convenient to integrate, and can be used in radio frequency front-end equipment.

Optionally, the common gate of the cascode structure corresponding to the variable gain sub-circuit in the two second-order quality factor enhancement active filter circuits (the first second-order quality factor enhancement active filter circuit 02 and the second-order quality factor enhancement active filter circuit 03) is connected to a control voltage, the drain of the cascode structure is connected in parallel to the inductor-capacitor parallel resonator sub-circuit and the negative resistance feedback sub-circuit, the source of the cascode structure is connected to a tail current source, and the tail current source is implemented by a fixed-bias N-type common-source metal oxide semiconductor transistor.

Optionally, the current source and the two transistors in the two second-order quality factor enhancement active filter circuits form a negative resistance feedback sub-circuit, the current source is realized by an N-type common-source metal oxide semiconductor transistor, and the change of the current is realized by changing the gate voltage of the N-type common-source metal oxide semiconductor transistor, so as to control the change of the quality factor.

Optionally, referring to fig. 1, the subtraction circuit 01 includes a fifteenth common-source transistor M15, a sixteenth common-source transistor M16, a seventeenth common-source transistor M17, and an eighteenth common-source transistor M18;

the drain of the fifteenth common-source transistor M15 is connected to the source of the seventeenth common-source transistor M17 and the output port, the source of the fifteenth common-source transistor M15 is connected to ground GND, the drain of the sixteenth common-source transistor M16 is connected to the source of the eighteenth common-source transistor M18 and the output port, the source of the sixteenth common-source transistor M16 is connected to ground GND, the source of the seventeenth common-source transistor M17 is connected to the power supply VDD, and the source of the eighteenth common-source transistor M18 is connected to the power supply VDD.

In the present application, the center frequency of the second-order Q enhancement active filter circuit is ω;

in the formula (1), C is the total capacitance value in the circuit, and L is the inductance value of the inductor;

the first second-order Q-enhanced active filter circuit has the center frequency of omega 1, and the LC resonant cavity and the negative resistance transfer function waveform are as follows:

the second-order Q-enhanced active filter circuit has a center frequency of omega 2, and the LC resonant cavity and the negative resistance transfer function have waveforms as follows:

subtracting the two functions (2) and (3) to obtain a fourth-order Q-enhanced active filter waveform function as follows:

in the formula, Q1 and Q2 represent quality factors of the second-order Q enhanced active circuit.

Optionally, fig. 2 shows a schematic circuit structure diagram of a first second-order quality factor enhancing active filter circuit provided in this embodiment of the present application, and referring to fig. 1 or fig. 2, the variable gain sub-circuit a corresponding to the first second-order quality factor enhancing active filter circuit 02 includes a first common-source transistor M1, a second common-source transistor M2, a third common-gate transistor M3, a fourth common-gate transistor M4, and a first current source Itail 1; the variable gain sub-circuit a corresponding to the second-order quality factor enhancing active filter circuit 03 comprises: an eighth common-source transistor M8, a ninth common-source transistor M9, a tenth common-gate transistor M10, an eleventh common-gate transistor M11, and a second current source Itail 2.

The first common-source transistor M1 and the second common-source transistor M2 are configured to input a differential radio frequency signal, a drain of the first common-source transistor M1 and a drain of the second common-source transistor M2 are respectively connected to a source of the third common-gate transistor M3 and a source of the fourth common-gate transistor M4, the other ends of the first common-gate transistor M1 and the second common-source transistor M2 are connected to the first current source Itail1, and gates of the third common-gate transistor M3 and the fourth common-gate transistor M4 are connected to a first resistance control voltage Vcr1 control; the eighth common-source transistor M8 and the ninth common-source transistor M9 are configured to input a differential radio frequency signal, a drain of the eighth common-source transistor M8 and a drain of the ninth common-source transistor M9 are connected to a source of the tenth common-gate transistor M10 and a source of the eleventh common-gate transistor M11, respectively, and the other end of the eighth common-source transistor M8 and the drain of the ninth common-source transistor M9 are connected to the second current source Itail2, gates of the tenth common-gate transistor M10 and the eleventh common-gate transistor M11 are connected to a second resistance control voltage Vcr 2control, and a tail current source is implemented by a fixed-bias N-type common-source MOS transistor.

In the present application, the gain control may be performed on the two second-order Q-enhancement active filter circuits by changing the first resistance control voltage Vcr1crontrol and the second resistance control voltage Vcr2crontrol, respectively.

It should be noted that, referring to fig. 1, the input impedance matching network includes a first resistor R1 and a second resistor R2, the first resistor R1 and the second resistor R2 are connected in series, two ends are connected to the input differential radio frequency signal, and the middle is connected to the bias voltage, so that the matching degree of the filter can be ensured.

In the present application, a variable gain sub-circuit, an inductance-capacitance (LC) parallel resonator sub-circuit, and a negative resistance feedback sub-circuit are subtracted by a subtraction circuit to form a four-order Q (quality factor) enhanced active filter circuit.

Optionally, referring to fig. 1 or fig. 2, the drains of the third common-gate transistor M3 and the fourth common-gate transistor M4 are connected to the corresponding inductance-capacitance parallel resonator sub-circuit B, one end of the corresponding negative resistance feedback sub-circuit C is connected to the inductance-capacitance parallel resonator sub-circuit B, and the other end of the corresponding negative resistance feedback sub-circuit C is connected to the first current source Itail 1.

Optionally, referring to fig. 1, the drains of the tenth common-gate transistor M10 and the eleventh common-gate transistor M11 are connected to the corresponding inductance-capacitance parallel resonator sub-circuit B, one end of the corresponding negative resistance feedback sub-circuit C is connected to the inductance-capacitance parallel resonator sub-circuit B, and the other end of the corresponding negative resistance feedback sub-circuit C is connected to the second current source Itail 2.

Optionally, referring to fig. 1, a gate of the seventeenth common-source transistor M17 is connected to a drain of the tenth common-gate transistor M10, a gate of the fifteenth common-source transistor M15 is connected to a drain of the third common-gate transistor M3, a gate of the sixteenth common-source transistor M16 is connected to a drain of the fourth common-gate transistor M4, and a gate of the eighteenth common-source transistor M18 is connected to a drain of the eleventh common-gate transistor M11.

Optionally, the first common-source transistor, the second common-source transistor, the eighth common-source transistor, and the ninth common-source transistor all operate in a linear region, the third common-gate transistor, the fourth common-gate transistor, the tenth common-gate transistor, and the eleventh common-gate transistor operate in a saturation region, the first resistance control voltage and the second resistance control voltage are changed, transconductance of the first common-source transistor, the second common-source transistor, the eighth common-source transistor, and the ninth common-source transistor exponentially changes with the control voltage, load resistance and current remain unchanged, and voltage gain of the circuit changes, so that gain control is achieved, and linearity is improved by using the first current source and the second current source.

Optionally, referring to fig. 1, the inductor-capacitor parallel resonant sub-circuit B includes a first variable capacitor C1, a second variable capacitor C2, a third variable capacitor C3, a fourth variable capacitor C4, a capacitor array, a first inductor L1, a second inductor L2, and a nineteenth common-source transistor M19.

Referring to fig. 1, two terminals of the first inductor L1 are connected in parallel to the capacitor array and the first variable capacitor C1 and the second variable capacitor C2 connected in series, a center plug is connected to a power supply VDD, a first capacitor control voltage Vcc1control is connected to a connection of the first variable capacitor C1 and the second variable capacitor C2, two terminals of the second inductor L2 are connected in parallel to the capacitor array and the third variable capacitor C3 and the fourth variable capacitor C4 connected in series, a center plug is connected in series to a drain-and-gate shorted nineteenth common-source transistor M19 and the power supply VDD, and a second capacitor control voltage Vcc2control is connected to a connection of the third variable capacitor C3 and the fourth variable capacitor C4.

Further, in the present application, the capacitor array is mainly composed of six pairs of discretely adjusted switched capacitors. The switch capacitor mainly comprises an NMOS transistor, a resistor and a fixed capacitor. After the two resistors are connected in series, two ends of the two resistors are connected with the NMOS transistor in parallel, and then two ends of the two resistors are respectively connected with the fixed capacitor in series. The two resistors are connected in series and then grounded in the middle, and the grid electrode of the NMOS transistor is connected with the switch control voltage.

In the present application, the capacitance value of the variable capacitor C may be adjusted by adjusting the capacitor array switch to change the first capacitor control voltage Vcc1control and the second capacitor control voltage Vcc2control, thereby implementing adjustment control of the resonance center frequency.

Optionally, referring to fig. 1, the negative feedback sub-circuit C includes a fifth common-source transistor M5, a sixth common-source transistor M6, a seventh common-source transistor M7, a twelfth common-source transistor M12, a thirteenth common-source transistor M13, and a fourteenth common-source transistor M14, and the change of the Q value is controlled by controlling a gate voltage of the fifth common-source transistor M5 to implement a change of a current.

Wherein, referring to fig. 1, a drain of the sixth common-source transistor M6 is connected to a gate of the seventh common-source transistor M7, a source of the sixth common-source transistor M6 is connected to a drain of the fifth common-source transistor M5, a drain of the seventh common-source transistor M7 is connected to a gate of the sixth common-source transistor M6, a source of the seventh common-source transistor M7 is connected to a drain of the fifth common-source transistor M5, a source of the fifth common-source transistor M5 is connected to ground, a gate of the fifth common-source transistor M5 is connected to a first current control voltage Vci1control, a drain of the thirteenth common-source transistor M13 is connected to a gate of the fourteenth common-source transistor M14, a source of the thirteenth common-source transistor M13 is connected to a drain of the twelfth common-source transistor M12, a drain of the fourteenth common-source transistor M14 is connected to a gate of the thirteenth common-source transistor M13, the source of the fourteenth common source transistor M14 is connected to the drain of the twelfth common source transistor M12, the source of the twelfth common source transistor M12 is connected to ground, and the gate of the twelfth common source transistor M12 is connected to the second current control voltage Vci2 control.

Optionally, the first common-source transistor M1, the second common-source transistor M2, the third common-source transistor M3, the fourth common-source transistor M4, the fifth common-source transistor M5, the sixth common-source transistor M6, the seventh common-source transistor M7, the eighth common-source transistor M8, the ninth common-source transistor M9, the tenth common-source transistor M10, the eleventh common-source transistor M11, the twelfth common-source transistor M12, the thirteenth common-source transistor M13, the fourteenth common-source transistor M14, the fifteenth common-source transistor M15, the sixteenth common-source transistor M16, the seventeenth common-source transistor M17 and the eighteenth common-source transistor M18 are all N-type metal oxide semiconductor transistors, and the substrates are connected to the corresponding grounds;

the nineteenth common-source transistor M19 is a P-type metal oxide semiconductor transistor, and the substrate is connected to a corresponding power supply.

For example, fig. 3 shows a schematic diagram of a simulation curve in which a center frequency point is not changed when the gain of a Q-enhanced active filter provided in the embodiment of the present application is adjusted, as shown in fig. 3, the simulation curve is an S21 simulation curve obtained based on SMIC 55nm CMOS process simulation in a Cadence simulation software tool, and fig. 3 shows that when the gains of two second-order Q-enhanced active filters are adjusted, the center frequency point of the second-order Q-enhanced active filter is not changed, and the center frequency point of a synthesized fourth-order Q-enhanced active filter is also not changed. Wherein the dotted line is the curve of the second-order Q-enhanced active filter, and the solid line is the curve of the Q-enhanced active filter of the present invention.

For example, fig. 4 shows a tunable simulation diagram of a filtering center frequency of a Q-enhanced active filter provided by the embodiment of the present application, fig. 5 shows a tunable simulation diagram of a center frequency of a Q-enhanced active filter provided by the embodiment of the present application with a bandwidth of 3GHz, fig. 6 shows a data diagram of simulation data of a Q-enhanced active filter provided by the embodiment of the present application, fig. 4 and fig. 5 are S21 simulation curves obtained by a Cadence simulation software tool based on an SMIC 55nm CMOS process simulation, and fig. 6 shows simulation data obtained by the simulation curves. Fig. 4, 5, 6 illustrate the ability of the Q-enhancement active filter to tune and linearity.

As can be seen from fig. 3, 4, 5, and 6, the present application has the technical effects of a large gain adjustment range, an unchanged central frequency point when the gain and Q values change, a tunable central frequency, a good rectangular coefficient, and a high linearity, is easy to integrate, and can be used in a radio frequency front end device.

Compared with a gain amplification structure in a traditional four-order Q-enhanced active filter circuit synthesized based on a subtraction circuit, the traditional four-order Q-enhanced active filter circuit synthesized based on the subtraction circuit directly controls a variable resistor to adjust gain and Q value, and different load capacitances are generated on an LC resonator, so that frequency drift is caused. The cascode and negative resistance current source structure adopted by the invention not only has a good gain adjustment range, but also has no obvious change of the central frequency point when the gain and the Q value are adjusted, thereby showing obvious advantages.

The quality factor enhancement active filter provided by the embodiment of the invention comprises a subtraction circuit, and a first second-order quality factor enhancement active filter circuit and a second-order quality factor enhancement active filter circuit which are respectively electrically connected with the subtraction circuit; the first second-order quality factor enhancement active filter circuit and the second-order quality factor enhancement active filter respectively comprise a variable gain sub-circuit, an inductance-capacitance parallel harmonic oscillator circuit and a negative resistance feedback sub-circuit which are electrically connected in pairs; the subtraction circuit is connected with the variable gain sub-circuit; the subtraction circuit is used for increasing the band-pass filtering frequency selectivity of the first second-order quality factor enhancement active filter circuit and the second-order quality factor enhancement active filter circuit to fourth order and increasing the rectangular coefficient of the quality factor enhancement active filter; the two variable gain sub-circuits both adopt a cascode structure and are used for adjusting the gain of the quality factor enhancement active filter circuit in a larger range and inhibiting the drift of a central frequency point; the inductance-capacitance parallel harmonic oscillator circuit is used for realizing the adjustment control of the resonance center frequency by changing the capacitance value of the inductance-capacitance parallel harmonic oscillator circuit; the negative resistance feedback sub-circuit is used for adjusting the quality factor of the active filter, so that the active filter has the technical effects of large gain adjustment range, unchanged central frequency point when the gain and Q value are adjusted, tunable central frequency, good rectangular coefficient and high linearity, is convenient to integrate, and can be used in radio frequency front-end equipment.

The quality factor enhancement active filter provided by the invention is applied to a hardware implementation method of a reserve pool calculation model shown in any one of fig. 1 to 6, which comprises a controller and at least one detection circuit electrically connected with the controller, and is not repeated here for avoiding repetition.

The electronic device in the embodiment of the present invention may be a device, or may be a component, an integrated circuit, or a chip in a terminal. The device can be mobile electronic equipment or non-mobile electronic equipment. By way of example, the mobile electronic device may be a mobile phone, a tablet computer, a notebook computer, a palm top computer, a vehicle-mounted electronic device, a wearable device, an ultra-mobile personal computer (UMPC), a netbook or a Personal Digital Assistant (PDA), and the like, and the non-mobile electronic device may be a server, a Network Attached Storage (NAS), a Personal Computer (PC), a Television (TV), a teller machine or a self-service machine, and the like, and the embodiment of the present invention is not particularly limited.

The electronic device in the embodiment of the present invention may be an apparatus having an operating system. The operating system may be an Android (Android) operating system, an ios operating system, or other possible operating systems, and embodiments of the present invention are not limited in particular.

Fig. 7 is a schematic diagram illustrating a hardware structure of an electronic device according to an embodiment of the present invention. As shown in fig. 7, the electronic device 100 includes a processor 110.

As shown in fig. 7, the processor 110 may be a general processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more ics for controlling the execution of programs according to the present invention.

As shown in fig. 7, the electronic device 100 may further include a communication line 140. Communication link 140 may include a path for transmitting information between the aforementioned components.

Optionally, as shown in fig. 7, the electronic device may further include a communication interface 120. The communication interface 120 may be one or more. The communication interface 120 may use any transceiver or the like for communicating with other devices or communication networks.

Optionally, as shown in fig. 7, the electronic device may further include a memory 130. The memory 130 is used to store computer-executable instructions for performing aspects of the present invention and is controlled for execution by the processor. The processor is used for executing the computer execution instructions stored in the memory, thereby realizing the method provided by the embodiment of the invention.

As shown in fig. 7, the memory 130 may be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a Random Access Memory (RAM) or other types of dynamic storage devices that can store information and instructions, an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compact disc, laser disc, optical disc, digital versatile disc, blu-ray disc, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer, but is not limited to such. The memory 130 may be separate and coupled to the processor 110 via a communication link 140. Memory 130 may also be integrated with processor 110.

Optionally, the computer-executable instructions in the embodiment of the present invention may also be referred to as application program codes, which is not specifically limited in this embodiment of the present invention.

In particular implementations, as one embodiment, processor 110 may include one or more CPUs, such as CPU0 and CPU1 in fig. 7, as shown in fig. 7.

In a specific implementation, as an embodiment, as shown in fig. 7, the terminal device may include a plurality of processors, such as a first processor 1101 and a second processor 1102 in fig. 7. Each of these processors may be a single core processor or a multi-core processor.

Fig. 8 is a schematic structural diagram of a chip according to an embodiment of the present invention. As shown in fig. 8, the chip 200 includes one or more than two (including two) processors 110.

Optionally, as shown in fig. 8, the chip further includes a communication interface 120 and a memory 130, and the memory 130 may include a read-only memory and a random access memory and provide operating instructions and data to the processor. The portion of memory may also include non-volatile random access memory (NVRAM).

In some embodiments, as shown in FIG. 8, memory 130 stores elements, execution modules or data structures, or a subset thereof, or an expanded set thereof.

In the embodiment of the present invention, as shown in fig. 8, by calling an operation instruction stored in the memory (the operation instruction may be stored in the operating system), a corresponding operation is performed.

As shown in fig. 8, the processor 110 controls the processing operation of any one of the terminal devices, and the processor 110 may also be referred to as a Central Processing Unit (CPU).

As shown in fig. 8, memory 130 may include both read-only memory and random access memory and provides instructions and data to the processor. A portion of memory 130 may also include NVRAM. For example, in applications where the memory, communication interface, and memory are coupled together by a bus system that may include a power bus, a control bus, a status signal bus, etc., in addition to a data bus. For clarity of illustration, however, the various buses are labeled as bus system 240 in fig. 8.

As shown in fig. 8, the method disclosed in the above embodiments of the present invention may be applied to a processor, or may be implemented by a processor. The processor may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in a processor or instructions in the form of software. The processor may be a general purpose processor, a Digital Signal Processor (DSP), an ASIC, an FPGA (field-programmable gate array) or other programmable logic device, discrete gate or transistor logic device, or discrete hardware components. The various methods, steps and logic blocks disclosed in the embodiments of the present invention may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present invention may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software module may be located in ram, flash memory, rom, prom, or eprom, registers, etc. storage media as is well known in the art. The storage medium is located in a memory, and a processor reads information in the memory and completes the steps of the method in combination with hardware of the processor.

In one aspect, a computer-readable storage medium is provided, in which instructions are stored, and when executed, the instructions implement the functions performed by the terminal device in the above embodiments.

In one aspect, a chip is provided, where the chip is applied in a terminal device, and the chip includes at least one processor and a communication interface, where the communication interface is coupled to the at least one processor, and the processor is configured to execute instructions to implement the functions performed by the hardware implementation method of the reserve pool computing model in the foregoing embodiments.

In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, the procedures or functions described in the embodiments of the present invention are performed in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, a terminal, a user device, or other programmable apparatus. The computer program or instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer program or instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire or wirelessly. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that integrates one or more available media. The usable medium may be a magnetic medium, such as a floppy disk, a hard disk, a magnetic tape; or optical media such as Digital Video Disks (DVDs); it may also be a semiconductor medium, such as a Solid State Drive (SSD).

While the invention has been described in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a review of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

While the invention has been described in conjunction with specific features and embodiments thereof, it will be evident that various modifications and combinations can be made thereto without departing from the spirit and scope of the invention. Accordingly, the specification and figures are merely exemplary of the invention as defined in the appended claims and are intended to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (10)

1. A quality factor enhanced active filter, characterized in that the quality factor enhanced active filter comprises:

the filter comprises a subtraction circuit, a first second-order quality factor enhancement active filter circuit and a second-order quality factor enhancement active filter circuit, wherein the first second-order quality factor enhancement active filter circuit and the second-order quality factor enhancement active filter circuit are respectively electrically connected with the subtraction circuit;

the first second-order quality factor enhancement active filter circuit and the second-order quality factor enhancement active filter respectively comprise a variable gain sub-circuit, an inductance-capacitance parallel harmonic oscillator circuit and a negative resistance feedback sub-circuit which are electrically connected in pairs; the subtraction circuit is connected with the variable gain sub-circuit;

the subtraction circuit is used for increasing the band-pass filtering frequency selectivity of the first second-order quality factor enhancement active filter circuit and the second-order quality factor enhancement active filter circuit to fourth order and increasing the rectangular coefficient of the quality factor enhancement active filter;

the two variable gain sub-circuits both adopt a cascode structure and are used for adjusting the gain of the quality factor enhancement active filter circuit in a larger range and inhibiting the drift of a central frequency point;

the inductance-capacitance parallel harmonic oscillator circuit is used for realizing the adjustment control of the resonance center frequency by changing the capacitance value of the inductance-capacitance parallel harmonic oscillator circuit;

the negative resistance feedback sub-circuit is used for adjusting the quality factor of the active filter.

2. The quality factor enhanced active filter according to claim 1, wherein the common gate of the cascode structure corresponding to the variable gain sub-circuit in two second-order quality factor enhanced active filter circuits is connected to a control voltage, the drain of the cascode structure is connected in parallel to the inductor-capacitor parallel resonator sub-circuit and the negative resistance feedback sub-circuit, the source of the cascode structure is connected to a tail current source, and the tail current source is implemented by a fixed-bias N-type cascode mos transistor.

3. The quality factor enhanced active filter of claim 1, wherein the two second-order quality factor enhanced active filter circuits comprise a negative feedback sub-circuit formed by a current source and two transistors, the current source is implemented by an N-type common-source mos transistor, and the variation of the quality factor is controlled by changing the gate voltage of the N-type common-source mos transistor to implement the variation of the current.

4. The quality-factor-enhanced active filter of claim 1, wherein the subtraction circuit comprises a fifteenth common-source transistor, a sixteenth common-source transistor, a seventeenth common-source transistor, and an eighteenth common-source transistor;

the drain of the fifteenth common-source transistor is connected with the source of the seventeenth common-source transistor and the output port respectively, the source of the fifteenth common-source transistor is connected with the ground, the drain of the sixteenth common-source transistor is connected with the source of the eighteenth common-source transistor and the output port respectively, the source of the sixteenth common-source transistor is connected with the ground, the source of the seventeenth common-source transistor is connected with the power supply, and the source of the eighteenth common-source transistor is connected with the power supply.

5. The QF-AMF of claim 4, wherein the variable gain sub-circuit corresponding to the first second-order QF-AMF circuit comprises a first common-source transistor, a second common-source transistor, a third common-gate transistor, a fourth common-gate transistor, a first current source; the variable gain sub-circuit corresponding to the second order quality factor enhancement active filter circuit comprises: the power supply comprises an eighth common-source transistor, a ninth common-gate transistor, a tenth common-gate transistor, an eleventh common-gate transistor and a second current source;

the first common-source transistor and the second common-source transistor are used for inputting differential radio-frequency signals, the drain electrode of the first common-source transistor and the drain electrode of the second common-source transistor are respectively connected with the source electrode of the third common-gate transistor and the source electrode of the fourth common-gate transistor, the other end of the first common-source transistor and the drain electrode of the second common-source transistor are connected with the first current source, and the grid electrodes of the third common-gate transistor and the fourth common-gate transistor are connected with a first resistor control voltage; the eighth common-source transistor and the ninth common-source transistor are used for inputting differential radio-frequency signals, a drain electrode of the eighth common-source transistor and a drain electrode of the ninth common-source transistor are respectively connected with a source electrode of the tenth common-gate transistor and a source electrode of the eleventh common-gate transistor, the other end of the eighth common-source transistor and the drain electrode of the ninth common-source transistor are connected with the second current source, and grid electrodes of the tenth common-gate transistor and the tenth common-gate transistor are connected with a second resistor control voltage;

the drains of the third common-gate transistor and the fourth common-gate transistor are connected with the corresponding inductive-capacitor parallel harmonic oscillator circuit, one end of the corresponding negative resistance feedback sub-circuit is connected with the inductive-capacitor parallel harmonic oscillator circuit, and the other end of the corresponding negative resistance feedback sub-circuit is connected with the first current source;

the drains of the tenth common-gate transistor and the eleventh common-gate transistor are connected with the corresponding parallel resonant sub-circuit of the inductance and the capacitance, one end of the corresponding negative resistance feedback sub-circuit is connected with the parallel resonant sub-circuit of the inductance and the capacitance, and the other end of the corresponding negative resistance feedback sub-circuit is connected with the second current source;

the gate of the seventeenth common-source transistor is connected with the drain of the tenth common-gate transistor, the gate of the fifteenth common-source transistor is connected with the drain of the third common-gate transistor, the gate of the sixteenth common-source transistor is connected with the drain of the fourth common-gate transistor, and the gate of the eighteenth common-source transistor is connected with the drain of the eleventh common-gate transistor.

6. The quality-factor enhanced active filter of claim 5, wherein the first, second and eighth common-source transistors, the ninth common-source transistor all operate in a linear region, the third common-gate transistor, the fourth common-gate transistor, the tenth common-gate transistor and the eleventh common-gate transistor work in a saturation region, the first resistance control voltage and the second resistance control voltage are changed, the transconductance of the first common-source transistor, the second common-source transistor, the eighth common-source transistor and the ninth common-source transistor is exponentially changed along with the control voltage, the load resistance and the current are kept unchanged, the voltage gain of the circuit is changed, therefore, gain control is realized, and linearity is improved by adopting the first current source and the second current source.

7. The quality factor enhanced active filter of claim 5, wherein the LC parallel resonator sub-circuit comprises a first variable capacitor, a second variable capacitor, a third variable capacitor, a fourth variable capacitor, a capacitor array, a first inductor and a second inductor;

the two ends of the first inductor are connected with the capacitor array and the first variable capacitor and the second variable capacitor which are connected in series in parallel, a central plug is connected with a power supply, a first capacitor control voltage is connected with the junction of the first variable capacitor and the second variable capacitor, the two ends of the second inductor are connected with the capacitor array and the third variable capacitor and the fourth variable capacitor which are connected in series in parallel, the central plug is connected with a nineteenth common-source transistor with a short-circuited drain electrode and a grid electrode and the power supply in series, and a second capacitor control voltage is connected with the junction of the third variable capacitor and the fourth variable capacitor.

8. The quality factor enhanced active filter of claim 7, wherein the negative-resistance feedback sub-circuit comprises a fifth common-source transistor, a sixth common-source transistor, a seventh common-source transistor, a twelfth common-source transistor, a thirteenth common-source transistor, and a fourteenth common-source transistor;

a drain of the sixth common-source transistor is connected to a gate of the seventh common-source transistor, a source of the sixth common-source transistor is connected to a drain of the fifth common-source transistor, a drain of the seventh common-source transistor is connected to a gate of the sixth common-source transistor, a source of the seventh common-source transistor is connected to a drain of the fifth common-source transistor, a source of the fifth common-source transistor is connected to ground, a gate of the fifth common-source transistor is connected to the first current control voltage, a drain of the thirteenth common-source transistor is connected to a gate of the fourteenth common-source transistor, a source of the thirteenth common-source transistor is connected to a drain of the twelfth common-source transistor, a drain of the fourteenth common-source transistor is connected to a gate of the thirteenth common-source transistor, and a source of the fourteenth common-source transistor is connected to a drain of the twelfth common-source transistor, the source electrode of the twelfth common-source transistor is connected with the ground, and the grid electrode of the twelfth common-source transistor is connected with the second current control voltage.

9. The quality-factor-enhanced active filter of claim 8, wherein the first common-source transistor, the second common-source transistor, the third common-gate transistor, the fourth common-gate transistor, the fifth common-source transistor, the sixth common-source transistor, the seventh common-source transistor, the eighth common-source transistor, the ninth common-source transistor, the tenth common-gate transistor, the eleventh common-gate transistor, the twelfth common-source transistor, the thirteenth common-source transistor, the fourteenth common-source transistor, the fifteenth common-source transistor, the sixteenth common-source transistor, the seventeenth common-source transistor and the eighteenth common-source transistor are all N-type metal oxide semiconductor transistors, and substrates are all connected to corresponding grounds;

the nineteenth common-source transistor is a P-type metal oxide semiconductor transistor, and the substrate is connected with a corresponding power supply.

10. An electronic device, comprising: one or more processors; and one or more machine readable media having instructions stored thereon that, when executed by the one or more processors, cause an apparatus to perform the quality factor enhancing active filter of any of claims 1-9.

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