CN114498646A

CN114498646A - Three-level active power filter and control method thereof

Info

Publication number: CN114498646A
Application number: CN202210357222.3A
Authority: CN
Inventors: 高晗璎; 杨睿祺; 张炜昊; 刘向南
Original assignee: Harbin University of Science and Technology
Current assignee: Harbin University of Science and Technology
Priority date: 2022-04-02
Filing date: 2022-04-02
Publication date: 2022-05-13

Abstract

A three-level active power filter and a control method thereof relate to the field of power quality control. The method aims to solve the problems that the traditional model is large in prediction calculation amount and difficult in weight factor selection, and the current tracking effect and the APF compensation performance are seriously influenced. The invention obtains a reference voltage vector V_refTo obtain a reference voltage vector V_refProjection vector V on alpha and beta axes_αSum vector V_β(ii) a Determining a reference voltage vector V_refObtaining a voltage vector in the quadrilateral sector; and traversing the voltage vectors in the quadrilateral sectors to obtain an optimal switching state sequence. The invention has small calculated amount, does not need to select weight factors and increasesThe current tracking effect is enhanced, and the compensation performance of the active power filter is improved.

Description

Three-level active power filter and control method thereof

Technical Field

The invention relates to the field of power quality control, in particular to a three-level active power filter and a control method thereof.

Background

With the advancement of power electronics technology and the development of manufacturing, more and more nonlinear devices are put into production and manufacturing. The input of these non-linear loads will cause huge harmonic interference and reactive influence to the grid. If the power grid is not treated, huge pollution is brought to the power grid, and great economic loss and safety accidents are caused. The Active Power Filter (APF) has good dynamic response, real-time performance and controllability, and is an ideal device for compensating harmonic waves and improving the quality of electric energy. The three-level active power filter has the advantages of large capacity, more output levels, small filter inductance and the like. The optimization research of the three-level control algorithm mainly focuses on the harmonic current tracking control strategy. As a novel current tracking control algorithm, model prediction has the advantages of fast dynamic response, flexible control, good stability and the like, and is widely applied to control of the power converter.

In general, model predictive control is performed by sampling the current output current of a device at the present time, substituting the current output current into a mathematical model of a controlled object, and predicting current information to be output from the device in the future from current or past current information. Model prediction involves a rolling optimization process, requiring a significant amount of processing time, reducing the dynamic performance of model predictive control. When the multi-cost function is controlled, the expected control effect can be obtained by adjusting the weight factor. The weight factor reflects the importance of the cost function and plays a decisive role in the control effect of the target; although model prediction can unify a plurality of constraints by adjusting weight factors, it is difficult to adjust weight coefficients in engineering.

Disclosure of Invention

In order to solve the above problems, the present invention provides a method and an apparatus for controlling a three-level active power filter, which solve the problems of large prediction calculation amount, difficult weight factor selection, and serious influence on the current tracking effect and the compensation performance of the active power filter in the conventional MPC.

The invention provides a three-level active power filter, which comprises an inverter unit and a control unit, wherein the inverter unit comprises a midpoint clamping three-level inverter circuit, and the control unit comprises:

a reference voltage vector acquisition module for acquiring a reference voltage vector V_refObtaining the reference voltage vector V_refIn the alpha and beta axesProjection vector V of_αAnd V_β；

A sector judgment module for judging the vector V_αAnd V_βDetermining a reference voltage vector V_refObtaining a voltage vector in the quadrilateral sector;

and the optimal switching state sequence output module is used for traversing the voltage vectors in the quadrilateral sectors to obtain an optimal switching state sequence.

Furthermore, the three-level active power filter further comprises a sampling unit, wherein the sampling unit comprises a power grid voltage sampling circuit, an alternating current sampling circuit and a direct current capacitor voltage sampling circuit.

The invention provides a control method of a three-level active power filter, which comprises the following steps:

s1, obtaining a reference voltage vector V_refObtaining the reference voltage vector V_refProjection vector V on alpha and beta axes_αSum vector V_β；

S2, judging reference voltage vector V_refObtaining a voltage vector in the quadrilateral sector;

and S3, traversing the voltage vectors in the quadrilateral sectors to obtain an optimal switching state sequence.

Further, the vector V_αSum vector V_βRespectively as follows:

wherein i_α(k) And i_β(k) Actual compensation currents of the active power filter at the moment k are respectively; i.e. i_α(k +1) and i_β(k +1) dividing the predicted value of the compensation current at the k +1 moment; t is_sAnd in the system sampling period, L is an alternating current side output filter inductor, and R is inductor internal resistance.

Further, the sector division method includes:

by means of straight lines

And the beta coordinate axis is divided into six quadrilateral areas of I, II, III, IV, V and VI;

when V is_αIs greater than 0 and

then reference voltage vector V_refIn the quadrangular region I; when V is_α＞0、V_βIs greater than 0 and

then reference voltage vector V_refIn the quadrilateral area II; when V is_α≤0、V_βIs greater than 0 and

then reference voltage vector V_refIn the quadrilateral area III; when V is_αIs < 0 and

then reference voltage vector V_refIn the quadrilateral area IV; when V is_α＜0、V_βIs < 0 and

then reference voltage vector V_refIn the quadrilateral area V; when V is_α＞0、V_βIs < 0 and

then reference voltage vector V_refIn the quadrilateral area VI.

Furthermore, the quadrilateral region contains eight vectors, and redundant vectors in the eight vectors are removed to obtain seven voltage vectors.

Further, step S3 includes:

s31, calculating the output voltage u of the APF under the switching state of the seven voltage vectors_αAnd u_β；

S32, according to the voltage u_αAnd u_βCalculating a predicted value i of the compensation current at the moment k +1_α(k +1) and i_β(k+1)；

S33, calculating the predicted value i of the reference harmonic current at the moment k +1^*(k+1)；

S34, predicting the compensation current i at the moment k +1_α(k +1) and i_βPrediction values of reference harmonic current at (k +1) and (k +1) moments

And

substituting the value function g into a switch state sequence corresponding to the minimum value function, wherein the value function is as follows:

step S3 includes: output voltage u of APF under switching state of seven voltage vectors_αAnd u_βThe calculation method comprises the following steps:

wherein S is_xAs a switching function, x ═ a, b, c, switching function S_xThe method specifically comprises the following steps:

wherein S is_x1、S_x1、S_x1And S_x1Respectively representing four power switch tubes on each bridge arm of the three-level active power filter.

As described above, the present invention has the following advantages compared with the prior art:

1. the control method of the invention is realized by an improved Model Predictive Control (MPC) algorithm of a value function based on sector judgment, only uses a predicted value of a reference harmonic current and a predicted value of a compensation current to form the value function for determining an optimal voltage vector, does not need to consider a midpoint potential error, does not need to introduce a weight coefficient, omits the setting and setting processes of the weight coefficient, reduces the complexity of calculation,

2. the method divides the sector again, reduces the rolling optimization times from 27 switch states to 7 switch states through sector judgment, selects the switch state corresponding to the minimum value function through calculating the value function, greatly reduces the rolling quantity of the voltage vector, shortens the operation time of the model predictive control algorithm, and has strong practicability.

3. Harmonic current needing to be compensated is extracted from load current through an ip-iq detection method, and the harmonic current is used as given current, so that the compensation current and the given current achieve a better tracking effect.

4. According to the method, the number of rolling voltage vectors can be reduced, the problem of midpoint potential voltage does not need to be considered in the calculation process of the value function by providing the redundant small vectors, a good compensation effect can be achieved only by considering errors, and as can be seen from the attached drawing 19, the method for removing the redundant small vectors is selected in the specific embodiment of the method, and the effect of reducing midpoint potential fluctuation can be achieved.

5. The invention is suitable for occasions such as reactive power compensation, rail transit, wind power generation and the like, and has wide applicability.

Drawings

Fig. 1 is an overall schematic block diagram of a three-level active power filter of a sector judgment-based unit price function improved MPC algorithm according to an embodiment of the present invention;

FIG. 2 is a topology diagram of an NPC three-level main circuit according to an embodiment of the present invention;

FIG. 3 is a three-level spatial vector diagram of an NPC according to an embodiment of the present invention;

fig. 4 is an equivalent circuit diagram corresponding to different vectors according to an embodiment of the present invention, fig. 4a is a large vector equivalent circuit diagram according to an embodiment of the present invention, fig. 4b is a medium vector equivalent circuit diagram according to an embodiment of the present invention, fig. 4c is a small vector equivalent circuit diagram according to an embodiment of the present invention, and fig. 4d is a zero vector equivalent circuit diagram according to an embodiment of the present invention;

FIG. 5 is a block diagram of a conventional model predictive control according to an embodiment of the present invention;

FIG. 6 is a three-level voltage vector diagram according to an embodiment of the present invention;

FIG. 7 is a flow chart of the embodiment of the present invention for predicting and controlling the unit price function improved model based on sector judgment;

FIG. 8 shows a driving circuit of 2SD315AI according to an embodiment of the present invention;

FIG. 9 is an AC current sampling circuit according to an embodiment of the present invention;

FIG. 10 is a grid voltage sampling circuit according to an embodiment of the present invention;

FIG. 11 is a DC capacitor voltage sampling circuit according to an embodiment of the present invention;

FIG. 12 is a diagram of the predicted tracking effect of the phase A reference harmonic current in the comparison algorithm of the present invention;

FIG. 13 is a diagram of the predicted value of the A-phase reference harmonic current and the error of the compensation current according to the comparative algorithm of the present invention;

FIG. 14 is a diagram illustrating the tracking effect of the predicted value of the phase A reference harmonic current according to the embodiment of the present invention;

FIG. 15 is a diagram of the phase A reference harmonic current prediction value and compensation current error results for the implementation of the present invention;

FIG. 16 is a graph of the overall voltage waveform of the DC side capacitor of the comparative algorithm of the present invention;

FIG. 17 is a graph of midpoint potential fluctuation for a comparative algorithm in accordance with an embodiment of the present invention;

FIG. 18 is a graph of the overall voltage waveform of the DC-side capacitor in accordance with the present invention;

FIG. 19 is a graph of the fluctuation of the midpoint potential in accordance with the practice of the present invention;

FIG. 20 is a time consuming graph of a comparative algorithm according to an embodiment of the present invention;

FIG. 21 is a time-consuming diagram of an algorithm according to an embodiment of the present invention;

FIG. 22 is a waveform illustrating a current simulation of the compensated phase network according to an embodiment of the present invention;

fig. 23 is a diagram of a phase a grid current THD according to an embodiment of the present invention;

FIG. 24 is a diagram illustrating the value of the flag for the on/off status according to the present invention;

FIG. 25 is a diagram illustrating the result of the evaluation of the sector judgment flag1 according to the present invention;

FIG. 26 is a flowchart of a main routine of the embodiment of the present invention;

FIG. 27 is a flow chart of A/D interrupt according to an embodiment of the present invention.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict.

It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.

As shown in fig. 1, the present embodiment provides a three-level active power filter, which includes a sampling unit, an inverting unit, a control unit, and a driving unit;

the sampling unit comprises an alternating current sampling circuit, a power grid voltage sampling circuit and a direct current capacitor voltage sampling circuit and is used for sampling the current power grid voltage, the harmonic current, the compensation current of an APF system and the voltage values of two capacitors at the direct current side;

in a specific embodiment, the method for obtaining the harmonic current includes:

using i_p-i_qCurrent detectionThe measuring method extracts an active component in the load current, filters high-frequency interference in the active current by using a sliding mean filtering method, and subtracts the filtered active current from the load current to obtain a reactive current and a harmonic current to be compensated. The harmonic current is used as given current of the inverter and is input into the MPC unit together with the compensation current, the switching state is output, and finally the compensation of harmonic and reactive power on the side of the power grid is realized.

The inverter unit is a Neutral Point Clamped (NPC) three-level inverter, as shown in fig. 2, and includes two dc-side capacitors C1 and C2, three pairs of diode clamp circuits, and twelve power switching tubes, which form a-phase bridge arm, b-phase bridge arm, and C-phase bridge arm connected in parallel, and a power switching tube S_a1、S_a2、S_a3And S_a4Form an a-phase bridge arm, S_b1、S_b2、S_b3And S_b4Form a b-phase bridge arm and a power switch tube S_c1、S_c2、S_c3And S_c4And the midpoints of the three pairs of diodes are connected with the midpoint of the direct-current side capacitor.

The control unit is used for realizing capacitor voltage stabilization, current tracking control, coordinate transformation, controller closed-loop control and drive waveform generation, and the control unit comprises:

a reference voltage vector acquisition module for acquiring a reference voltage vector V_refObtaining the reference voltage vector V_refProjection vector V on alpha and beta axes_αSum vector V_β；

A sector judgment module for judging the reference voltage vector V_refObtaining a voltage vector in the quadrilateral sector;

The modules in the control unit may be implemented in the form of software programs, or may be implemented in the form of hardware module circuits, or may be implemented in the form of software programs combined with hardware modules. In the present example.

In a specific embodiment, the control unit adopts a DSP + FPGA architecture, in the working process, a DSP chip is used for processing sampling data and realizing the algorithm of sector judgment MPC, and all modules in the control unit are loaded in the DSP chip through software programs to realize the operation; the FPGA chip is used for receiving PWM signals sent by the DSP chip after model prediction algorithm operation, decoding the signals to generate 12 paths of PWM signals, and then performing dead zone configuration to be used as a PWM port of the DSP chip.

The DSP chip selects TMS320F28335 of TI company, the FPGA chip selects EP4CE15E22C8N of ALTERA company, the DSP chip is mainly responsible for calculation of processed sampling signals, instruction current extraction and sector MPC judgment algorithms, PWM signals are sent to the FPGA in parallel, the FPGA is mainly used as a PWM port of the DSP, a dead zone is added into the PWM signals, and the PWM is amplified by a driving circuit and drives power switch tubes in each phase inverter to work.

The driving unit is used for amplifying the low-level and low-power control signal output by the FPGA, so that the driving unit can drive the power switch tube. As shown in fig. 8, the driving circuit of this embodiment selects a driving module with a model number of 2SD315AI, which is introduced by the company condept, switzerland, and has two operating modes, i.e., a direct mode and a half-bridge mode, in which 8 pins MOD of the driver is shorted to VDD, and operates in the direct mode, at this time, channels a and B do not have a relationship, the two channels operate independently, and RC1 and RC2 are shorted to GND, and at this time, the state output SO1/SO2 also operates independently. The 8-pin MOD of the driver is in short circuit with the GND, the driver works in a half-bridge mode, dead time is generated between two channels, the dead time is adjusted by an RC (resistor-capacitor) network between

pins

5 and 7, at the moment, INB is connected with high level enable, and INA is a total input end of two signals.

In a specific embodiment, the ac sampling circuit is shown in fig. 9, and includes sampling of the load-side current and sampling of the inverter output current. The current is changed into milliampere level through the mutual inductor, the phase is compensated through the amplification of the proportional circuit, the filtering is carried out after the bias voltage is added, and the current is input into the DSP.

In a specific embodiment, the grid voltage sampling circuit is shown in fig. 10, in which the grid voltage sampling circuit is implemented by two 100K resistors and 1: 1, converting the voltage into a small voltage signal through a proportional circuit, increasing bias voltage, filtering the small voltage signal through a filter circuit, and inputting the small voltage signal into a control chip DSP.

In an embodiment, as shown in fig. 11, the voltage of the bus is reduced to within 3V by the dc capacitor voltage sampling circuit, and then the voltage is input to the DSP through the isolation of the voltage follower.

The control method of the three-level active power filter comprises the following steps:

s1, obtaining a reference voltage vector V_refProjection vector V on alpha and beta axes_αAnd V_β；

Three operating states of the NPC three-level topology of the present embodiment are shown in table 1:

TABLE 1 switching State vs. output Voltage relationship

In the above table: 1 represents that the switch tube is turned on, 0 represents that the switch tube is turned off, and x is a, b and c.

The switching function is defined as follows:

in the formula: s_xFor the output level function, x is a, b, c, which are the three legs of the three-phase inverter.

Assuming that a three-phase power grid is symmetrical and undistorted and only contains fundamental wave components, a three-phase load is symmetrical and ignores line parasitic inductance, only an alternating current side output filter inductance is considered, and L is equal to L_a＝L_b＝L_cNeglecting the loss of system lines and devices, only considering the internal resistance of the inductor and the internal resistances of the three-phase inductors are equal, namely R is R_a＝R_b＝R_cThe capacitance values of the capacitors on the direct current side are equal and are all C. The NPC three-level APF mathematical model of the present embodiment is built based on the above assumptions and Kirchhoff's Voltage Law (KVL)Comprises the following steps:

in the formula u_sa、u_sb、u_scFor three-phase mains voltage, i_ca、i_cb、i_ccAs compensation current of APF, u_AO、u_BO、u_COIs the potential difference between the output point of the inverter and the neutral point O at the DC side of the NPC topology_ONIs the voltage between the neutral point O of the NPC topology DC side and the neutral point N of the power grid_AO、u_BO、u_COExpressed by formula (3):

from the foregoing assumptions:

combining the formulas (2), (3) and (4) to obtain the difference u between the midpoint potential on the DC side and the AC reference point potential_ON：

The NPC three-level APF output voltage u_yN(y-A, B, C) and a switching function S_x(x ═ a, b, c) satisfies the following relationship:

as shown in fig. 3, 27 voltage vectors exist in the NPC topology switch state vector of the present embodiment, including 6 large vectors, 6 medium vectors, 12 small vectors, and 3 zero vectors. The large vectors include PNN (V2), PPN (V4), NPN (V6), NPP (V8), NNP (V10) and PNP (V12), the medium vectors include PNO (V1), PON (V3), OPN (V5), NPO (V7), NOP (V9) and ONP (V11), the small vectors include ONO (V13), POP (V14), ONN (V15), POO (V16), OON (V17), PPO (V18), NON (V19), OPO (V20), NOO (V21), OPP (V22), NNO (V23) and OOP (V24), the zero vectors include V25), OONNO (V26) and PPP (V27).

In order to analyze the influence of each vector on the midpoint potential, the equivalent circuits corresponding to the above four vectors are first analyzed, as shown in fig. 4.

Fig. 4a) shows that the large vector (PNN) acts on the entire bus voltage, and does not form a loop with the midpoint O, and the rest 5 large vectors do so, so that the large vector acts only on the entire bus voltage on the dc side, and does not affect the midpoint potential voltage; when the output voltage vector is a middle vector, one phase is connected with the middle point O, the other two phases are respectively connected with the positive end and the negative end of the bus voltage and form a loop with the middle point O, so that the balance of the middle point potential is influenced, but the influence of the middle point potential is not controlled. The small vectors may be divided into positive and negative small vectors.

Fig. 4c) and d) show that the small vectors affect the midpoint potential balance because they are electrically connected to the midpoint O and form a loop when they act. When the output state of the switch tube belongs to a zero vector.

Fig. 4e) shows that, although all three bridge arms are connected to the midpoint O, no current loop is formed, and the midpoint potential balance is not affected, and the remaining two zero vectors (PPP) and (NNN) are not connected to the midpoint O, and naturally, the midpoint potential is not affected. The effect of the four voltage vectors on the dc side midpoint potential is shown in table 2.

TABLE 2 influence of Voltage vector on midpoint potential

Midpoint current of i_oThree-phase load current i_a、i_b、i_cThe direction of the outflow midpoint and the direction of the outflow inverter are respectively taken as positive directions to obtain midpoint current i_oThe correspondence between the redundant small vectors and the load current is shown in table 3.

TABLE 3 i_oCorresponding relation with redundant small vector and output current

According to the attached Table 3, i_oAnd the mathematical relation expression of the output compensation current of the APF system is as follows:

i_o＝-(i_ca|S_a|+i_cb|S_b|+i_cc|S_c|) (7)

the DC side capacitance relation is:

in the formula: v_dc1、V_dc2Are respectively a capacitor C₁、C₂The value of the voltage.

Defining a voltage deviation V_o＝V_dc1-V_dc2In combination (7) and (8), the following results are obtained:

in the formula: x is a, b, c.

And (3) performing Clarke transformation on the established APF mathematical model to obtain:

in the formula:

wherein

Clarke transformation of formula (6) gives:

discretizing the continuous signal by using an Euler discretization method for facilitating subsequent calculation, and discretizing a derivative term in the formula (10) to obtain:

in the formula: i.e. i_α(k)、i_β(k) APF actual compensation current at the time k; i.e. i_α(k+1)、i_β(k +1) represents the predicted compensation current at time k + 1; t is_sRepresenting the system sampling period.

The combined type (10), the formula (12) and the formula (13) are as follows:

in the formula: u. of_αβ(k) The voltage output by APF at the moment k; e.g. of the type_αβ(k) Is the grid voltage at time k.

Since it is important to keep the dc-side capacitance voltage stable, the model prediction control also considers the balance of the midpoint potential while keeping a good current tracking effect, and discretization of equation (9) is obtained:

in the formula: v_o(k+1)、V_o(k) And respectively obtaining deviation predicted values and deviation sampling values of the two capacitors at the moment k +1 and the moment k.

Substituting formula (15) for formula (9) yields the following formula:

this embodiment requires a reference voltage vector V_refProjected on the alpha and beta axes, transformed by equation (14):

in order to enable the system to achieve a better current tracking effect, the predicted compensation current is equal to the predicted value of the harmonic given current, namely:

in the formula: i.e. i_αβ(k +1) represents i_α(k +1) and i_β(k +1), representing the predicted compensation current at time k + 1;

the projections of the reference voltage vectors obtained by the joint formula (17) and the formula (18) on the alpha axis and the beta axis are respectively:

re-sectoring the three-level voltage vector diagram described in fig. 3 to obtain the NPC three-level voltage vector diagram shown in fig. 6, the partitioning method includes:

by means of straight lines

And the beta axis will be divided into I, II,And III, IV, V and VI, wherein the quadrilateral area contains eight vectors, the eight vectors comprise a large vector, two medium vectors, two small vectors and three zero vectors, and the redundant small vectors are removed to obtain seven voltage vectors which are to-be-rolled optimized vectors.

When V is_αIs greater than 0 and

then reference voltage vector V_refIn the quadrilateral area VI.

Taking quadrilateral I as an example, the vectors to be scrolled for optimization are shown in table 4. Compared with the traditional model prediction, the rolling times and the system calculation amount are greatly reduced.

TABLE 4 region I vectors to be scrolled optimized

The three switching states of each leg of the NPC three-level inverter are denoted by P, O and N, respectively, and the switching states of the small vectors (hereinafter referred to as small vector combinations) always appear in pairs. Table 5 shows the effect of small vector combinations on the DC-side capacitor voltage, where i_oIs the current flowing from the midpoint of the DC side, i_k(k ═ a, b, c) is an unsigned current i_oThe arrows indicate the decrease and increase of the capacitor voltage. It can be seen that although the output voltage vector is the same for each pair of small vector combinations, the effect on the dc side capacitor voltage is opposite. Therefore, as long as the optimal switching state obtained by the cost function is a small vector combination, its effect on the dc-side capacitor voltage can be evaluated according to table 5. Then, according to this effect, an optimum switching state capable of balancing the midpoint potential voltage on the dc side is selected from the two redundant combinations. For example, assume that at time t, the optimal switch state obtained by the cost function is ONN and i_aIs greater than 0. According to Table 5, the switch state applied to the system at time t +1 will decrease the capacitor voltage u_dc2. However, at time t u_dc1Greater than u_dc2The switch state ONN will increase the DC side midpoint voltage imbalance, and if the switch state POO is used instead of the optimal switch state ONN for output, u will be reduced_dc1ONN is eliminated as redundant hours.

TABLE 5 influence of small vector combinations on DC-side capacitor voltage

S3, traversing the voltage vectors in the quadrilateral sectors to obtain an optimal switching state sequence, which specifically includes:

s31, calculating the voltage u of the APF output in the seven voltage vectors in the switching state_αAnd u_β；

The switching states of the seven voltage vectors are converted into switching functions, and the switching functions are substituted into formula (11), namely the following formula, to obtain the voltage u of the output of the APF in each switching state_αAnd u_β。

Voltage u of output of APF_αAnd u_βIn formula (14), i.e., in the following formula, the predicted value i of the compensation current at the time k +1 is obtained_α(k +1) and i_β(k+1)。

S33, calculating the predicted value of the reference harmonic current at the k +1 moment

And

And

and substituting the value function g into the value function g to screen out a corresponding switch state sequence when the value function is the minimum value function.

The predicted value of the reference harmonic current at the moment k +1 is i^*(k +1), the desired predicted value of the compensation current is i (k +1), i^*The error between (k +1) and i (k +1) is Δ i (k +1), and the function for solving the error generally has three forms, i.e. integral error, absolute error and square error, and the expressions are respectively as follows:

Δi(k+1)＝|i^*(k+1)-i(k+1)| (21)

Δi(k+1)＝|i^*(k+1)-i(k+1)|² (22)

when the system only has one target to be controlled, the control results obtained by using the three error functions are almost the same; when the system has two or more control targets, the accuracy of the error function adopting the formula (21) is reduced to some extent, and the control effect is not the error function adopting the formula (22). Compared with the latter two error functions, the value function established by selecting the integral error function has higher precision and smaller error, and the integral operation is contained in the formula, so that the actual controller can generate larger time delay.

According to the NPC three-level APF system cost function, the prior art generally selects the square error function as the model of the cost function, which can be obtained from equation (22):

the current tracking effect is taken as a value function, and the balance of the midpoint potential on the direct current side is considered, and the value function can be expressed as:

in the formula: g₂＝|V_o(k+1)|。

The final expression of the cost function is then:

in the formula: lambda [ alpha ]₁、λ₂Are weight coefficients.

The weight coefficient λ needs to be considered in the cost function₁、λ₂And a weight coefficient λ₁、λ₂The determination process is difficult, and if the weighting factor is not properly selected, the current tracking effect and the compensation effect of the APF are seriously affected, therefore, the cost function of this embodiment adopts a cost function which no longer needs to consider the midpoint potential error, and the specific form of the cost function obtained by equations (21) and (25) is:

in the formula:

for reference to the predicted value of the harmonic current at the time k +1, i_αβAnd (k +1) is the predicted compensation current value at the moment k + 1.

The predicted value of the reference harmonic current at the time k +1

The method is obtained by a Lagrange extrapolation interpolation method, and the formula of the Lagrange interpolation method is as follows:

considering both accuracy and calculated amount, the invention selects n to be 2:

as shown in fig. 5 and 7, the conventional control method includes sampling the current grid voltage, the harmonic current, the APF system compensation current, and the dc-side two-capacitor voltage value, predicting the reference harmonic current at the time k +1 by using the lagrange interpolation method, performing rolling optimization on 27 switch states in NPC three levels, predicting compensation current output by the APF system at the k +1 moment and capacitance voltage error on a direct current side at each rolling, calculating a cost function according to the formula (25), judging the minimum cost function after 27 cycles, and finally outputting a switch state sequence corresponding to the minimum cost function to finish the model prediction control process.

12-25, there are graphs showing simulation and comparison results of the conventional MPC system and the sector judgment based unit price function modified MPC system of the present invention by MATLAB/Simulink system simulation software. Fig. 12 is a diagram showing the tracking effect of the predicted value of the a-phase reference harmonic current of the conventional MPC, fig. 13 is a diagram showing the predicted value and the compensation current error of the a-phase reference harmonic current of the conventional MPC algorithm, the current tracking error range is ± 2.5A, fig. 14 is a diagram showing the tracking effect of the predicted value of the a-phase reference harmonic current of the present invention, and fig. 15 is a diagram showing the predicted value and the compensation current error of the a-phase reference harmonic current of the improved MPC algorithm of the present invention.

Fig. 16 is a voltage waveform diagram of the whole dc-side capacitor of the conventional MPC, in which the voltage amplitude fluctuates around 801V and can maintain stable fluctuation. FIG. 17 is a diagram of the DC side midpoint potential waveform of the conventional MPC algorithm, with the fluctuation range being + -1.4V. Fig. 18 is a voltage waveform diagram of the whole dc-side capacitor of the present invention, which can be stabilized around 800V and has a small fluctuation, and fig. 19 is a diagram of the fluctuation condition of the midpoint potential of the present invention, which shows that the fluctuation is stable and the fluctuation range is 0.37V, and compared with the conventional MPC algorithm, the fluctuation range is smaller, and a better voltage stabilization effect is achieved.

FIG. 20 is a graph of the algorithm elapsed time for compensation using a conventional MPC algorithm, which measures a program run time of 59.2 μ s. The run time of the MPC algorithm segment was 39 mus. FIG. 21 is a graph showing the time consumption of the algorithm when the modified MPC algorithm is compensated based on the unit price function of the sector judgment, the running time of the whole program is 38.4 mus, and the running time of the single target modified MPC algorithm based on the sector judgment is 18 mus. The comparison in the figures shows that the conventional algorithm requires 27 comparison operations at a time, whereas the modified MPC algorithm requires only 7 comparison operations when selecting the optimal vector. Thus, compared with the traditional MPC algorithm, the running time of the improved MPC control algorithm is shortened by more than half, and the running time of the algorithm is greatly shortened.

Fig. 22 is a simulation waveform diagram of phase grid current after compensation of an active power filter of the unit price value function improved MPC algorithm based on sector judgment, fig. 23 is a diagram of a phase grid current THD, fig. 24 is a diagram of a switch state flag value taking diagram, and fig. 25 is a diagram of a sector judgment flag1 value taking result.

A main program flowchart of the system of the present invention is shown in fig. 26. The TMS320F28335 is used for controlling, and the main program comprises an initialization function, a main function, an interrupt service function, an upper computer communication function and the like. The interrupt program comprises A/D sampling, a phase-locked loop and the realization of a sector judgment MPC algorithm. In the a/D interrupt flow chart shown in fig. 26, after the interrupt is performed, the interrupt flag bit is cleared first to create a condition for the next interrupt, the current, the voltage, and the dc side capacitor voltage of the power grid are sampled, the bias is filtered out by a filter, the phase of the power grid is locked, the harmonic extraction is performed on the load current, the obtained information is sent to a model predictive control algorithm, the optimal switching state is output by rolling optimization calculation, and the switching state information is sent to the FPGA.

The flow chart of the interrupt subroutine is shown in fig. 27. The A/D interruption is used for completing sampling of harmonic current, phase locking of power grid voltage, coordinate transformation, filtering, control of direct current side voltage and current tracking control algorithm operation, sending data to the FPGA, and generating 12 paths of PWM waves after the FPGA realizes a unique modulation algorithm.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims

1. A three-level active power filter is characterized by comprising an inverter unit and a control unit, wherein the inverter unit comprises a midpoint clamping three-level inverter circuit, and the control unit comprises:

a reference voltage vector acquisition module for acquiring a reference voltage vector V_refObtaining the reference voltage vector V_refProjection vector V on alpha and beta axes_αAnd V_β；

2. The control device of the three-level active power filter according to claim 1, further comprising a sampling unit, wherein the sampling unit comprises a grid voltage sampling circuit, an alternating current sampling circuit and a direct current capacitor voltage sampling circuit.

3. A control method of a three-level active power filter is characterized by comprising the following steps:

S2, according to the vector V_αAnd V_βDetermining a reference voltage vector V_refAcquiring a voltage vector in the quadrilateral sector;

4. A method as claimed in claim 3, wherein the vector V is a vector of values_αSum vector V_βRespectively as follows:

5. The method of claim 4, wherein the sectorization method comprises:

by means of straight lines

when V is_αIs greater than 0 and

then reference voltage vector V_refIn the quadrilateral area VI.

6. The method as claimed in claim 5, wherein the quadrilateral area contains eight vectors, and redundant vectors of the eight vectors are removed to obtain seven voltage vectors.

7. The method of claim 6, wherein the step S3 includes:

And

8. the method of claim 7, wherein the step S3 includes: output voltage u of APF under switching state of seven voltage vectors_αAnd u_βThe calculation method comprises the following steps: