CN114497208A - High electron mobility transistor device and method for testing the same - Google Patents

High electron mobility transistor device and method for testing the same Download PDF

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Publication number
CN114497208A
CN114497208A CN202011275475.3A CN202011275475A CN114497208A CN 114497208 A CN114497208 A CN 114497208A CN 202011275475 A CN202011275475 A CN 202011275475A CN 114497208 A CN114497208 A CN 114497208A
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field plate
drain
gate
test
electrode
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张昇
魏珂
陈晓娟
刘新宇
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Junction Field-Effect Transistors (AREA)

Abstract

The present disclosure provides a high electron mobility transistor device and a test method, the device including: a source (6) connected to the source test electrode layout (13); a drain (7) connected to a drain test electrode layout (14); a gate (8) located between the source (6) and the drain (7) and connected to the gate test electrode layout (15); a field plate (10) located between the gate (8) and the drain (7), connected to the field plate test electrode layout (16); wherein the source test electrode layout (13), the drain test electrode layout (14), the gate test electrode layout (15) and the field plate test electrode layout (16) are electrically insulated from each other. The device can separately add bias to a radio frequency signal and a direct current signal so as to improve the power efficiency characteristic of the device; in addition, the field plate is biased in different states, so that different suppression effects on the electric field under the grid are achieved, the working voltage of the device is improved, and high-power application is further achieved.

Description

High electron mobility transistor device and method for testing the same
Technical Field
The disclosure relates to the technical field of electronic information, in particular to a high electron mobility transistor device and a test method thereof.
Background
A GaN-based High Electron Mobility Transistor (HEMT) device is a core device of a power amplifier, and at present, GaN-based devices have entered the research of millimeter wave band, the application field of the device is further expanded, and higher requirements are put forward on the device performance. One of the problems faced by GaN-based HEMTs is the influence of high electric field strength, particularly, as the devices enter millimeter wave band application, the source-drain spacing of the devices is further shortened, and the increase of the peak electric field of the gate feet seriously limits the high-voltage and high-power application of the devices. The conventional method for inhibiting the electric field intensity is to introduce a field plate structure, but for a millimeter wave device, the introduction of the field plate structure brings great parasitic capacitance, seriously affects the frequency characteristic of the device, and is unfavorable for realizing a high-frequency high-power device.
Disclosure of Invention
Technical problem to be solved
In view of the above technical problems, it is a primary object of the present disclosure to provide a high electron mobility transistor device for solving at least one of the above technical problems.
(II) technical scheme
To achieve the above objects, the present disclosure provides a high electron mobility transistor device, comprising,
a source connected to a source test electrode layout (Pad);
a drain connected to the drain test Pad;
a gate electrode between the source electrode and the drain electrode, connected to the gate test Pad;
a field plate, which is located between the gate and the drain and connected to the field plate test Pad;
the source electrode test Pad, the drain electrode test Pad, the grid electrode test Pad and the field plate test Pad are electrically insulated from each other.
Optionally, the device further comprises a second semiconductor layer, and the source electrode, the drain electrode, the gate electrode and the field plate are grown on the second semiconductor layer.
Optionally, the device further comprises a second semiconductor layer, a passivation layer is deposited between the source and drain electrodes, and the field plate is disposed on the passivation layer.
Optionally, a groove is formed in the passivation layer through etching, the field plate is located on the groove, and the depth of the groove is 0-120 nm.
Optionally, the field plate is a Γ -type field plate or a T-type field plate or a vertical field plate.
Optionally, the Γ -type field plate comprises a first portion and a second portion connected to each other, the second portion is located on a side of the first portion away from the second semiconductor layer and has an angle with the first portion, the second portion and the side of the first portion away from the second semiconductor layer have a common first surface, and a third sidewall of the second portion close to the gate electrode and a second sidewall of the first portion close to the gate electrode are located on the same boundary line; the second part at least covers the part between the second side wall of the first part and the first side wall of the first part close to the drain electrode; a first air space is arranged between the surface of the first side wall and the second part close to the drain electrode and the surface of the drain electrode far away from the second semiconductor.
Optionally, the length of the second portion along the direction from the gate to the drain is less than or equal to the distance between the gate and the drain.
Optionally, the field plate gate pin structure is right-angled or U-shaped or V-shaped.
Optionally, the field plate test Pad has a length greater than or equal to 50 μm and a width greater than or equal to 50 μm.
Another aspect of the present disclosure provides a method for testing a high electron mobility transistor device, including: s1, connecting the source electrode, the drain electrode, the grid electrode and the field plate with the corresponding test Pad respectively; s2, performing radio frequency test on the device, adding a direct current signal to the field plate, and adding a radio frequency signal to the grid; and S3, performing direct current test on the device, adding a direct current signal to the field plate, and applying preset voltage or not to the field plate according to the test requirement.
(III) advantageous effects
The high electron mobility transistor device provided by the present disclosure has the following beneficial effects:
(1) through increasing field plate test Pad, be connected field plate lead wire and field plate test Pad alone, when the radio frequency test, add radio frequency offset through the grid, the field plate adds direct current offset, has realized that radio frequency signal and direct current signal separately add, has promoted the efficiency of device.
(2) By adjusting different bias states of the field plate, the distribution of the electric field at the edge of the gate pin can be well inhibited, the breakdown characteristic of the device is improved, and the enhancement device is realized.
Drawings
Fig. 1 schematically illustrates a top view of a HEMT device structure proposed by an embodiment of the present disclosure;
fig. 2 schematically illustrates a HEMT device according to an embodiment of the present disclosure, wherein fig. 2 is a cross-sectional view of a dotted line portion in fig. 1 along a direction a-a;
fig. 3 schematically illustrates a HEMT device according to another embodiment of the present disclosure, wherein fig. 3 is a cross-sectional view of a dotted line portion in fig. 1 along a-a direction;
fig. 4 schematically illustrates a HEMT device proposed in still another embodiment of the present disclosure, wherein fig. 4 is a sectional view of a dotted line portion in fig. 1 along a-a direction;
fig. 5 shows simulated distribution diagrams of electric field strength under a gate of the HEMT device of the present disclosure and the HEMT device of the prior art under different respective bias conditions of the field plate during the dc signal test;
FIG. 6 is an enlarged view of the dotted line portion of FIG. 5;
FIG. 7 shows a graph of DC transfer simulation results for a HEMT device of the prior art at different barrier layer thicknesses;
fig. 8 shows a dc transfer simulation result curve of the HEMT device proposed by the embodiment of the present disclosure at different thicknesses of the barrier layer;
fig. 9 schematically shows a flowchart of a method for manufacturing a HEMT device according to an embodiment of the present disclosure;
fig. 10 schematically shows a flowchart of a HEMT device testing method proposed by the embodiment of the present disclosure.
Description of the reference numerals
1-a substrate; 2-a first semiconductor layer; 3-an insertion layer; 4-a second semiconductor layer; 5-a cap layer; 6-source electrode; 7-a drain electrode; 8-a grid electrode; 9-a passivation layer; 10-a field plate; 11-a groove; 12-a nucleation layer; 13-source test Pad; 14-drain test Pad; 15-grid test Pad; 16-field plate test Pad; a 101- Γ type field plate first portion; a 102- Γ type field plate second portion; 110-first air space.
Detailed Description
For a better understanding of the objects, aspects and advantages of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Also, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.
As described in the background art, the field plate structure introduced to suppress the electric field strength of the HEMT device in the prior art may cause a large parasitic capacitance, which seriously affects the frequency characteristics of the HEMT device, and is disadvantageous for realizing a high-frequency high-power device.
In order to solve the above problems, the present application finds through research that: the double-gate structure has obvious advantages in the aspect of improving the power efficiency characteristic of the device, and the working voltage of the device can be effectively improved and the power and the efficiency can be improved by adding bias to the radio-frequency signal and the direct-current signal separately. Therefore, the design of a reasonably and normative field plate structure and a peripheral test Pad is very important, so that the test requirements can be met, and the parasitic influence brought by the test Pad can be reduced. Based on this, this application has proposed a HEMT device.
Fig. 1 schematically illustrates a top view of a HEMT device according to an embodiment of the present disclosure, as shown in fig. 1, the HEMT device includes a source 6 connected to a source test Pad 13; a drain 7 connected to a drain test Pad 14; a gate 8, which is located between the source 6 and the drain 7, and is connected with a gate test Pad 15; a field plate 10, which is located between the gate 8 and the drain 7, and connected to the field plate test Pad 16; the source test Pad13, the drain test Pad 4, the gate test Pad15 and the field plate test Pad16 are electrically insulated from each other.
The source electrode 6 and the drain electrode 7 in the present disclosure are formed by stacking a titanium layer, an aluminum layer, a nickel layer, and a gold layer, the gate electrode 8 is formed by stacking a nickel layer and a gold layer, and the field plate 10 may be formed by stacking a nickel layer and a gold layer or by stacking a titanium layer and a gold layer.
Further, in order to facilitate the test, the field plate test Pad16 of the HEMT device of the present disclosure is provided with a length of 50 μm or more and a width of 50 μm or more. The materials and dimensions of the field plate test Pad and the other test pads in the present disclosure may be selected according to actual test needs as long as the test needs can be satisfied.
In the HEMT device described above, by adding the field plate test Pad16 and connecting the field plate 10 individual lead to the field plate test Pad16, the following effects can be achieved: on one hand, when the device is subjected to radio frequency test, direct current bias can be added to the field plate 10, and radio frequency bias is added to the grid 8, so that the separation of radio frequency signals and direct current signals is realized, and the efficiency of the device is improved. On the other hand, when the device is subjected to a direct current test, any bias meeting the test requirement can be added to the field plate 10 by combining the test performance index requirement, so that the electric field intensity at the edge of the gate pin of the gate 8 can be well inhibited, the working voltage of the device is improved, and the enhancement of the device is realized earlier.
In an embodiment of the present disclosure, there is provided a HEMT device, as shown in fig. 2, further comprising a substrate 1, a first semiconductor layer 2, and a second semiconductor layer 4, wherein the first semiconductor layer 2 is grown on a surface of the substrate 1, the second semiconductor layer 4 is grown on a surface of the first semiconductor layer 2 away from the substrate 1, wherein the first semiconductor layer 2 and the second semiconductor layer 4 form a heterojunction, and a two-dimensional electron gas (2-DEG) is generated between the first semiconductor layer 2 and the second semiconductor layer 4; the source electrode 6, the drain electrode 7, the gate electrode 8, and the field plate 10 are grown on the surface of the second semiconductor layer 4 away from the first semiconductor layer 2, wherein the gate electrode 8 is located between the source electrode 6 and the drain electrode 7, the field plate 10 is located between the gate electrode 8 and the drain electrode 7, and the source electrode 6, the drain electrode 7, the gate electrode 8, and the field plate 10 are connected to the corresponding test pads, respectively, that is, the source electrode 6 is connected to the source test Pad13, the drain electrode 7 is connected to the drain test Pad14, the gate electrode 8 is connected to the gate test Pad15, and the field plate 10 is connected to the field test Pad 16.
The material of the substrate in the present disclosure includes silicon carbide, the material of the first semiconductor layer and the second semiconductor layer may be any two semiconductor materials that can form two-dimensional electron gas in the prior art, and those skilled in the art can select suitable materials to form the first semiconductor layer and the second semiconductor layer in the present disclosure according to practical situations. In an embodiment of the present disclosure, the material of the first semiconductor layer includes GaN, and the material of the second semiconductor layer includes AlGaN.
In another embodiment of the present disclosure, as shown in fig. 3, the HEMT device further includes a passivation layer 9 deposited between the source electrode 6 and the drain electrode 7, and the field plate 10 is disposed on the passivation layer 9. The passivation layer 9 covers the exposed surface of the second semiconductor layer 4 and the exposed surface of the gate electrode 8, thereby suppressing current collapse of the device and further protecting the device. The passivation layer material in the present disclosure may be selected from conventional insulating dielectric materials in the existing semiconductor field, such as silicon nitride, aluminum nitride, and aluminum oxide, as long as the function of suppressing current collapse is achieved.
Further, in the embodiment of the present disclosure, as shown in fig. 3, the passivation layer 9 may be etched to form a groove 11, and the field plate 10 is disposed on the groove 11, wherein the depth of the groove is 0 to 120 nm.
In the HEMT device, the field plate 10 is arranged on the groove 11 formed by etching the passivation layer 9, the thickness of the passivation layer 9 below the field plate is small, and the field plate 10 can also penetrate through the passivation layer 9 and directly contact with the second semiconductor layer 4. The groove 11 is etched on the passivation layer 9, so that the distance between the field plate 10 and a channel current carrier is shortened in the vertical direction, the electric field intensity at the edge of a grid can be effectively reduced, the breakdown voltage of a device is further improved, namely the working voltage of the device is improved, the output power of the device is increased, the passivation layer 9 can better protect structures such as a grid 8, and the reliability of the device is further ensured.
In another embodiment of the present disclosure, as shown in fig. 4, the HEMT device further includes: an insertion layer 3, a cap layer 5 and a nucleation layer 12, wherein the insertion layer 3 is located between the first semiconductor layer 2 and the second semiconductor layer 4 and is used for improving the threshold limiting capability of a two-dimensional electron gas (2-DEG); a cap layer 5 provided on a surface of the second semiconductor layer 4 remote from the first semiconductor layer 1, for protecting an interface of the second semiconductor layer 4; the nucleation layer 12 is located between the substrate 1 and the first semiconductor layer 2 to improve the nucleation quality of the first semiconductor layer 2.
The insertion layer, the cap layer and the nucleation layer in the present disclosure may be made of any suitable material as long as the above functions can be achieved, for example, the material of the insertion layer may include A1N, the material of the cap layer may include GaN, and the material of the nucleation layer includes A1N.
In the embodiment of the present disclosure, when the field plate 10 is disposed on the groove 11, the etching depth of the groove 11 needs to be considered in combination with the distance between the field plate 10 and the gate 8 and the drain 7 and the length of the field plate 10 along the direction from the gate 8 to the drain 7, for example, when the etching depth of the groove 11 is greater than or equal to 80nm, the peak value of the electric field intensity of the gate pin may exceed the peak value of the electric field intensity of the gate pin due to the deeper etching depth, and at this time, the field plate 10 needs to extend to a certain distance along the direction from the gate 8 to the drain 7, so that the electric field intensity at the edge of the gate pin of the field plate due to the introduction of the field plate can be suppressed or avoided.
In the embodiment of the present disclosure, the position of the field plate 10 between the gate 8 and the drain 7 affects the suppression effect on the electric field strength of the gate leg. For example, when the field plate 10 is close to the gate 8, the field plate 10 has a strong suppression effect on the gate leg electric field strength, whereas when the field plate 10 is close to the drain 7, the suppression effect of the field plate 10 on the gate leg electric field strength is insignificant.
The field plate 10 in the present disclosure may be any structure, and those skilled in the art can select a gate with a suitable structure according to practical situations.
In the embodiment of the present disclosure, the field plate 10 structure of the HEMT device may be an Γ -type field plate or a T-type field plate or a vertical field plate. Further, the gate pin structure of the field plate 10 may be a right angle, U-shaped, V-shaped, or other suitable structure.
As shown in fig. 2-4, the Γ -type field plate structure 10 of the present disclosure includes a first portion 101 and a second portion 102 connected to each other, where the second portion 102 is located on a side of the first portion 101 away from the second semiconductor layer 4 and forms an angle with the first portion 101, the second portion 102 and the first portion 101 have a common first surface, and a third sidewall of the second portion 102 close to the gate 8 and a second sidewall of the first portion 101 close to the gate 8 are located on a same boundary line; the second portion 102 covers at least a portion between the second sidewall of the first portion 101 and the first sidewall of the first portion 101 near the drain 7. A first air gap 110 is formed between the surface of the first sidewall and the second portion 102 close to the drain 7 and the surface of the drain 7 far from the second semiconductor 4.
In the embodiment of the present disclosure, the first portion 101 and the second portion 102 may be formed by a plane or a curved surface (e.g., an S-shaped curved surface), or may be formed by a curved surface and a plane, and an included angle between the first portion 101 and the second portion 102 may be an acute angle or a right angle, or another suitable included angle.
The first air space in the present disclosure is not limited to the form in fig. 2 to 4 described above, but may be in other forms.
Further, in the embodiment of the present disclosure, a length of the second portion 102 along the direction from the gate 8 to the drain 7 is less than or equal to a distance between the gate 8 and the drain 7. The design can effectively inhibit or avoid the influence of the electric field intensity at the edge of the field plate grid pin caused by the introduction of the field plate when the field plate is etched deeply (for example, the etching depth is greater than or equal to 80 nm).
In the embodiment of the present disclosure, the T-type field plate structure is different from the Γ -type field plate structure in that a second portion of the T-type field plate structure connected to the first portion further extends a certain distance in a direction pointing to the gate 8 from the drain electrode 7, and a second air gap is provided between a surface of the extended portion of the T-type field plate structure close to the gate 8 and a surface of the gate 8 away from the second semiconductor layer 4. Other features of the T-type field plate structure are the same as those of the Γ -type field plate structure, and are not described herein again.
In the embodiment of the present disclosure, the vertical field plate structure is different from the Γ -type field plate structure in that the vertical field plate does not have a second portion, and other features are the same as the Γ -type field plate structure, and are not described herein again.
In another embodiment of the present disclosure, a method for manufacturing a high electron mobility transistor device is provided, a flow of which is shown in fig. 9, and the method specifically includes:
s1, growing a source electrode, a drain electrode and a grid electrode on the second semiconductor layer, wherein the grid electrode is located between the source electrode and the drain electrode, and the source electrode and the drain electrode form ohmic contact;
s2, depositing a passivation layer between the source electrode and the drain electrode by adopting a plasma enhanced chemical vapor deposition method;
s3, etching the passivation layer to form a groove by adopting a dry ICP method;
s4, forming a field plate structure on the groove by adopting multi-layer photoresist photoetching, then evaporating metal, and stripping to obtain the field plate structure;
and S5, forming a peripheral Pad layout by stacking Ti/Ni/Ti/Au/Ti metals, and leading out the source electrode, the drain electrode, the grid electrode and the field plate for testing.
In yet another embodiment of the present disclosure, a method for testing a high electron mobility transistor device is further provided, the flow of which is shown in fig. 10, and specifically includes:
s1, connecting the source electrode 6, the drain electrode 7, the gate electrode 8 and the field plate 10 to the corresponding test Pad respectively;
s2, performing radio frequency test on the device, adding a direct current signal to the field plate 10, and adding a radio frequency signal to the grid 8;
and S3, performing direct current test on the device, adding a direct current signal to the field plate 10, and applying a preset voltage or not to the field plate 10 according to the test requirement.
And S4, ending the test.
In order to make the technical solutions of the present disclosure more clearly understood by those skilled in the art, the technical solutions of the present disclosure will be described below with reference to specific embodiments.
Examples
The structure of the HEMT device is shown in fig. 4, and specifically, comprises a substrate 1, a first semiconductor layer 2; the semiconductor device comprises an insertion layer 3, a second semiconductor layer 4, a cap layer 5, a source electrode 6, a drain electrode 7, a gate electrode 8, a passivation layer 9, a field plate 10, a groove 11, a nucleation layer 12, a source test Pad13, a drain test Pad14, a gate test Pad15 and a field plate test Pad 16.
Specifically, the substrate 1 is a SiC substrate, the first semiconductor layer 2 is a GaN layer having a thickness of 2.5 μm, the insertion layer 3 is an A1N layer having a thickness of 1nm, the second semiconductor layer 4 is AlGaN having a thickness of 20nm, the cap layer 5 is a GaN layer having a thickness of 1 nm; the source electrode 6 and the drain electrode 7 are formed by stacking a titanium layer, an aluminum layer, a nickel layer and a gold layer, and the distance between the source electrode 6 and the drain electrode 7 is 2.4 mu m; the grid 8 is formed by overlapping a nickel layer and a gold layer, the vertical width of the grid 8 is 200nm, the height of the grid 8 is 450nm, the horizontal width of the grid is 600nm, and the distance between the grid 8 and the drain is 1.4 mu m; the passivation layer 9 is a silicon nitride layer and is provided with a groove 11, the width of the groove is 400nm, the thickness of the passivation layer below the groove 11 is 30nm, the thickness of the passivation layer at other positions is 120nm, and the distance between one side of the groove 11 close to the grid and the grid 8 is 300 nm;
the field plate 10 is formed by stacking a titanium layer and a gold layer, the field plate 10 is an inverted L-shaped field plate and comprises a first portion 101 and a second portion 102, wherein the first portion is in a vertical structure, the width of the first portion is 200nm, the height of the first portion is 450nm, the second portion is in a horizontal structure, an included angle between the first portion and the second portion is a right angle, the second portion covers a part between a second side wall of the first portion 101 and a first side wall of the first portion 101, which is close to the drain electrode 7, and the length of the second portion is 400 nm; the first part is located in the groove 11 formed by etching the passivation layer 9, and a first air gap 110 is formed between the surface of the first sidewall and the second part 102, which is close to the drain electrode 7, and the surface of the drain electrode 7, which is far away from the second semiconductor 4; the nucleation layer 12 is an AlN layer with a thickness of 2 nm. The source test Pad13, the drain test Pad14, the gate test Pad15 and the field plate test Pad16 are formed by stacking Ti/Ni/Ti/Au/Ti metals.
In the testing process of the HEMT device, voltages are respectively applied to the field plate 10 and the grid 8 according to experimental requirements, wherein a direct current signal is added to the field plate 10, and a radio frequency signal is added to the grid 8.
Comparative example
The difference from the embodiment is that: the HEMT device does not comprise a field plate test Pad16 and a field plate 10, the grid 8 is connected with a grid test Pad15 through a lead, in the test process, voltage is applied to the grid 8 according to experiment requirements, and direct current signals and radio frequency signals are respectively added to the grid 8 according to the test requirements.
Fig. 5 is a distribution diagram of the electric field intensity under the gate in the off state of the HEMT device when the gate voltage, the source voltage, and no voltage is applied to the field plate respectively, in the direct current signal test by simulating the HEMT device of the comparative example and the example. Fig. 6 is an enlarged view of a dotted line portion in fig. 5. Wherein, the gate voltage Vgs is-6V, and the source electrode is grounded.
As is evident from fig. 5 and 6: (1) the HEMT device in this embodiment has a more significant suppression effect of the gate-leg peak electric field than the HEMT device in the prior art under the same bias (Vgs ═ 6V); (2) the field plate is biased in different states, and has different inhibiting effects on the electric field under the grid; (3) the relationship between the field plate bias condition and the electric field strength suppression is as follows: the field plate bias same grid voltage > the field plate bias same source voltage > the field plate does not apply voltage.
Fig. 7 and 8 are graphs of the results of dc transfer simulation at different barrier layer thicknesses by simulating HEMTs of comparative and example. Wherein, the device drain voltage Vds is 10V, and the ratio of the gate bias voltage Vgs: 6-2V, the field plate voltage Vgs2 is 0V, and the source electrode is grounded.
As can be seen from a comparison of fig. 7 and 8: (1) with the reduction of the thickness of the barrier layer of the device, the threshold voltage of the HEMT device in the embodiment is positively floated, and an enhancement type device is gradually realized; (2) the HEMT device of this example can realize the enhancement mode device earlier than the HEMT device of the comparative example at the same barrier layer thickness.
In summary, the present disclosure provides a high electron mobility transistor device, in which a field plate test Pad is added, and a field plate lead is separately connected to the field plate test Pad, so that, on one hand, during radio frequency test, radio frequency bias is added through a gate, and direct current bias is added to the field plate, thereby realizing separate addition of radio frequency signals and direct current signals, and improving the efficiency of the device. On the other hand, by adjusting different bias states of the field plate, the distribution of the electric field at the edge of the grid pin can be well inhibited, the breakdown characteristic of the device is improved, and the enhancement type device is realized.
The above-mentioned embodiments, objects, technical solutions and advantages of the present disclosure are further described in detail, it should be understood that the above-mentioned embodiments are only examples of the present disclosure, and should not be construed as limiting the present disclosure, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure.

Claims (10)

1. A high electron mobility transistor device, comprising:
a source (6) connected to a source test electrode layout (13);
a drain (7) connected to a drain test electrode layout (14);
a gate (8) located between the source (6) and the drain (7) and connected to a gate test electrode layout (15);
a field plate (10) between the gate (8) and the drain (7) connected to a field plate test electrode layout (16);
wherein the source test electrode layout (13), the drain test electrode layout (14), the gate test electrode layout (15) and the field plate test electrode layout (16) are electrically insulated from each other.
2. The hemt device of claim 1, further comprising a second semiconductor layer (4), wherein said source electrode (6), said drain electrode (7), said gate electrode (8) and said field plate (10) are grown in said second semiconductor layer (4).
3. The hemt device of claim 1, further comprising a second semiconductor layer (4) with a passivation layer (9) deposited between the source electrode (6) and the drain electrode (7), the field plate (10) being disposed on the passivation layer (9).
4. The HEMT device according to claim 3, wherein the passivation layer (9) is etched to form a groove (11), the field plate (10) is located on the groove (11), and the depth of the groove (11) is 0-120 nm.
5. The hemt device of any one of claims 2 to 4, wherein said field plate (10) is a Γ -type field plate or a T-type field plate or a vertical field plate.
6. The hemt device of claim 5, wherein said Γ -type field plate comprises a first portion (101) and a second portion (102) connected to each other, said second portion (102) being located on a side of said first portion (101) remote from said second semiconductor layer (4) and having an angle with said first portion (101), said second portion (102) having a common first surface with a side of said first portion (101) remote from said second semiconductor layer (4), a third sidewall of said second portion (102) near said gate electrode (8) being located on the same borderline as a second sidewall of said first portion (101) near said gate electrode (8); the second portion (102) covers at least the portion between the second sidewall of the first portion (101) and the first sidewall of the first portion (101) close to the drain (7);
a first air gap (110) is arranged between the surface of the first side wall and the second part (102) close to the drain electrode (7) and the surface of the drain electrode (7) far away from the second semiconductor (4).
7. The hemt device of claim 6, wherein a length of said second portion (102) along a direction from said gate (8) to said drain (7) is less than or equal to a spacing between said gate (8) and said drain (7).
8. The hemt device of claim 1, wherein said field plate (10) gate leg structure is right angle or U-shaped or V-shaped.
9. The hemt device of claim 1, wherein said field plate test electrode layout (16) has a length greater than or equal to 50 μm and a width greater than or equal to 50 μm.
10. A method of testing a hemt device, comprising:
s1, connecting the source electrode (6), the drain electrode (7), the grid electrode (8) and the field plate (10) with the corresponding test electrode layout respectively;
s2, performing radio frequency test on the device, adding a direct current signal to the field plate (10), and adding a radio frequency signal to the grid (8);
and S3, performing direct current test on the device, adding a direct current signal to the field plate (10), and applying a preset voltage or not applying a voltage to the field plate (10) according to the test requirement.
CN202011275475.3A 2020-11-13 2020-11-13 High electron mobility transistor device and method for testing the same Pending CN114497208A (en)

Priority Applications (1)

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Applications Claiming Priority (1)

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Publication Number Publication Date
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