CN114497205A - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
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- CN114497205A CN114497205A CN202210081195.1A CN202210081195A CN114497205A CN 114497205 A CN114497205 A CN 114497205A CN 202210081195 A CN202210081195 A CN 202210081195A CN 114497205 A CN114497205 A CN 114497205A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 60
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 230000004888 barrier function Effects 0.000 claims abstract description 114
- GPBUGPUPKAGMDK-UHFFFAOYSA-N azanylidynemolybdenum Chemical compound [Mo]#N GPBUGPUPKAGMDK-UHFFFAOYSA-N 0.000 claims abstract description 93
- 239000000758 substrate Substances 0.000 claims abstract description 61
- 238000000034 method Methods 0.000 claims description 45
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 32
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical group [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 26
- 239000010703 silicon Substances 0.000 claims description 26
- 229910052710 silicon Inorganic materials 0.000 claims description 26
- 239000010936 titanium Substances 0.000 claims description 25
- 238000000231 atomic layer deposition Methods 0.000 claims description 24
- 229910052719 titanium Inorganic materials 0.000 claims description 23
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 22
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 22
- 229910052750 molybdenum Inorganic materials 0.000 claims description 22
- 239000011733 molybdenum Substances 0.000 claims description 22
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 20
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 20
- 239000000463 material Substances 0.000 claims description 18
- 238000009792 diffusion process Methods 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 238000000277 atomic layer chemical vapour deposition Methods 0.000 claims 1
- 238000005229 chemical vapour deposition Methods 0.000 description 23
- 230000008569 process Effects 0.000 description 20
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 10
- 229910052801 chlorine Inorganic materials 0.000 description 10
- 239000000460 chlorine Substances 0.000 description 10
- 238000006243 chemical reaction Methods 0.000 description 6
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 6
- 239000002243 precursor Substances 0.000 description 6
- 150000001875 compounds Chemical class 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000007769 metal material Substances 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 238000000427 thin-film deposition Methods 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- VXEGSRKPIUDPQT-UHFFFAOYSA-N 4-[4-(4-methoxyphenyl)piperazin-1-yl]aniline Chemical compound C1=CC(OC)=CC=C1N1CCN(C=2C=CC(N)=CC=2)CC1 VXEGSRKPIUDPQT-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 125000001309 chloro group Chemical group Cl* 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910001092 metal group alloy Inorganic materials 0.000 description 2
- GICWIDZXWJGTCI-UHFFFAOYSA-I molybdenum pentachloride Chemical compound Cl[Mo](Cl)(Cl)(Cl)Cl GICWIDZXWJGTCI-UHFFFAOYSA-I 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 239000012713 reactive precursor Substances 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 239000005049 silicon tetrachloride Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- 239000013077 target material Substances 0.000 description 2
- XJDNKRIXUMDJCW-UHFFFAOYSA-J titanium tetrachloride Chemical compound Cl[Ti](Cl)(Cl)Cl XJDNKRIXUMDJCW-UHFFFAOYSA-J 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
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- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Composite Materials (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Materials Engineering (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The embodiment of the disclosure discloses a semiconductor structure and a manufacturing method thereof, wherein the semiconductor structure comprises: a substrate; an oxide layer on and/or within the substrate; the barrier layer covers the oxide layer and is in contact with the oxide layer; wherein the barrier layer comprises a silicon-doped and/or titanium-doped molybdenum nitride layer.
Description
Technical Field
The present disclosure relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for manufacturing the same.
Background
The semiconductor structure, such as a gate stack structure, includes an oxide layer on a substrate, a molybdenum nitride layer on the oxide layer, and a conductive layer on the molybdenum nitride layer, wherein the molybdenum nitride layer is used for blocking metal materials in the conductive layer from migrating into the oxide layer and the substrate.
However, the adhesion between the molybdenum nitride layer and the oxide layer is poor.
Disclosure of Invention
An embodiment of the present disclosure provides a semiconductor structure, including:
a substrate;
an oxide layer on and/or within the substrate;
the barrier layer covers the oxide layer and is in contact with the oxide layer;
wherein the barrier layer comprises a silicon-doped and/or titanium-doped molybdenum nitride layer.
In some embodiments, the barrier layer is silicon-doped molybdenum nitride; wherein the atomic number ratio of silicon to molybdenum in the barrier layer is between 0.1 and 0.9.
In some embodiments, the barrier layer is titanium doped molybdenum nitride; wherein the atomic number ratio of titanium to molybdenum in the barrier layer is between 0.1 and 0.9.
In some embodiments, the barrier layer is titanium-doped and silicon-doped molybdenum nitride; wherein the atomic number ratio of silicon to molybdenum in the barrier layer is between 0.1 and 0.3, and the atomic number ratio of titanium to molybdenum is between 0.1 and 0.3.
In some embodiments, the oxide layer comprises at least one of silicon oxide and silicon oxynitride.
In some embodiments, the semiconductor structure further comprises: a conductive layer overlying the barrier layer.
In some embodiments, the material of the conductive layer comprises molybdenum.
In some embodiments, the substrate includes a trench therein, the oxide layer covers sidewalls and a bottom surface of the trench, and the conductive layer fills the trench.
In some embodiments, the semiconductor structure is a Dynamic Random Access Memory (DRAM) and the conductive layer is a wordline.
The embodiment of the present disclosure also provides a manufacturing method of a semiconductor structure, including:
providing a substrate, and forming an oxide layer on and/or in the substrate;
forming a barrier layer on the oxide layer; wherein the barrier layer comprises a silicon-doped and/or titanium-doped molybdenum nitride layer.
In some embodiments, forming a barrier layer on the oxide layer comprises:
forming a doping layer on the oxidation layer, wherein the doping layer comprises a titanium nitride layer and/or a silicon nitride layer;
forming a molybdenum nitride layer on the doped layer;
and performing a thermal diffusion process to diffuse the doping layer and the molybdenum nitride layer mutually to form the barrier layer.
In some embodiments, the thickness of the doped layer and the thickness of the molybdenum nitride layer both range between 1 nanometer and 9 nanometers.
In some embodiments, the doped layer and the molybdenum nitride layer are formed using an atomic layer deposition method or a chemical vapor deposition method.
In some embodiments, forming a barrier layer on the oxide layer comprises:
depositing doping layers and molybdenum nitride layers on the oxide layer in sequence, wherein the doping layers comprise titanium nitride layers and/or silicon nitride layers;
and executing a thermal diffusion process to enable the doped layer and the molybdenum nitride layer to diffuse mutually to form the barrier layer.
In some embodiments, the number of doped layers ranges between 2-5 and the number of molybdenum nitride layers ranges between 2-4.
In some embodiments, the ratio of the total thickness of each doped layer to the thickness of the barrier layer ranges between 0.1 and 0.9.
In some embodiments, the barrier layer has a thickness between 1 nanometer and 10 nanometers.
In some embodiments, after forming the barrier layer on the oxide layer, the method further includes: and forming a conductive layer on the barrier layer, wherein the material of the conductive layer comprises molybdenum.
The embodiment of the present disclosure provides a semiconductor structure and a manufacturing method thereof, wherein the semiconductor structure includes: a substrate; an oxide layer on and/or within the substrate; the barrier layer covers the oxide layer and is in contact with the oxide layer; wherein the barrier layer comprises a silicon-doped and/or titanium-doped molybdenum nitride layer. According to the embodiment of the disclosure, the molybdenum nitride layer doped with silicon and/or titanium is used as the barrier layer, so that the gap between the barrier layer and the oxide layer can be effectively reduced, the adhesion between the barrier layer and the oxide layer is improved, and the performance of the semiconductor structure is improved.
The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features and advantages of the disclosure will be apparent from the description and drawings, and from the claims.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
Fig. 1 is a schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure;
fig. 2 is a schematic diagram of a semiconductor structure according to another embodiment of the present disclosure;
fig. 3 is a flow chart of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;
fig. 4a to 4e are process flow diagrams of a semiconductor structure according to an embodiment of the present disclosure;
fig. 5a to 5f are process flow diagrams of a semiconductor structure according to another embodiment of the present disclosure.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. It will be apparent, however, to one skilled in the art, that the present disclosure may be practiced without one or more of these specific details. In other instances, well-known features of the art have not been described in order to avoid obscuring the present disclosure; that is, not all features of an actual embodiment are described herein, and well-known functions and structures are not described in detail.
In the drawings, the size of layers, regions, elements, and relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on … …", "adjacent … …", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on … …," "directly adjacent to … …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. And the discussion of a second element, component, region, layer or section does not necessarily imply that the first element, component, region, layer or section is necessarily present in the disclosure.
Spatial relational terms such as "under … …," "under … …," "below," "under … …," "over … …," "above," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below … …" and "below … …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
The semiconductor structure, such as a gate stack structure, includes an oxide layer on a substrate, a molybdenum nitride layer on the oxide layer, and a conductive layer on the molybdenum nitride layer, wherein the molybdenum nitride layer is used for blocking metal materials in the conductive layer from migrating into the oxide layer and the substrate.
However, it has been found that when a molybdenum nitride layer is deposited on an oxide layer, voids are easily generated at the interface between the molybdenum nitride layer and the oxide layer, resulting in poor adhesion between the molybdenum nitride layer and the oxide layer, which affects the performance of the semiconductor structure.
Based on this, the following technical scheme of the embodiment of the disclosure is proposed:
an embodiment of the present disclosure provides a semiconductor structure, including: a substrate; an oxide layer on and/or within the substrate; the barrier layer covers the oxide layer and is in contact with the oxide layer; wherein the barrier layer comprises a silicon-doped and/or titanium-doped molybdenum nitride layer.
According to the embodiment of the disclosure, the molybdenum nitride layer doped with silicon and/or titanium is used as the barrier layer, so that the gap between the barrier layer and the oxide layer can be effectively reduced, the adhesion between the barrier layer and the oxide layer is improved, and the performance of the semiconductor structure is improved.
The following detailed description of the embodiments of the disclosure refers to the accompanying drawings. In describing the embodiments of the present disclosure in detail, the drawings are not to be taken as being generally to scale, and are for illustrative purposes only and should not be taken as limiting the scope of the present disclosure.
Fig. 1 and fig. 2 are schematic views of a semiconductor structure according to an embodiment of the present disclosure. The semiconductor structure provided by the embodiment of the present disclosure is further described in detail with reference to fig. 1 and fig. 2.
As shown in fig. 1, the semiconductor structure includes: a substrate 10; an oxide layer 11 on the substrate 10; a barrier layer 12 covering the oxide layer 11 and contacting the oxide layer 11; wherein the barrier layer 12 comprises a silicon-doped and/or titanium-doped molybdenum nitride layer.
The substrate may be a semiconductor substrate and may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In a particular embodiment, the substrate is a silicon substrate, which may be doped or undoped.
The oxide layer 11 is located on the substrate 10, and the barrier layer 12 covers a surface of the oxide layer 11. In one embodiment, the oxide layer 11 includes at least one of silicon oxide and silicon oxynitride. The oxide layer 11 may be formed using one or more thin film deposition processes; in particular, the thin film deposition process includes, but is not limited to, a Chemical Vapor Deposition (CVD) process, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, an Atomic Layer Deposition (ALD) process, or a combination thereof. But not limited thereto, the oxide layer 11 may also be formed by performing a thermal oxidation process on the substrate 10.
In one embodiment, the barrier layer 12 is silicon-doped molybdenum nitride; wherein, the number of silicon atoms is not too small and not too large; the number of silicon atoms is too small, and the effect of improving the adhesion is not great; too large a number of silicon atoms may deteriorate the barrier properties of the barrier layer 12. In a specific embodiment, the atomic number ratio of silicon to molybdenum in the barrier layer 12 is between 0.1 and 0.9, such as between 0.2 and 0.8, or between 0.4 and 0.6.
In another embodiment, the barrier layer 12 is titanium doped molybdenum nitride; wherein, the number of titanium atoms is not too small nor too much; the number of titanium atoms is too small, and the effect of improving the adhesion is not great; too much amount of titanium atoms may deteriorate the barrier properties of the barrier layer 12. In a specific embodiment, the atomic number ratio of titanium to molybdenum in the barrier layer 12 is between 0.1 and 0.9, such as between 0.2 and 0.8, or between 0.4 and 0.6.
In another embodiment, the barrier layer 12 is titanium-doped and silicon-doped molybdenum nitride; in other words, the barrier layer 12 comprises both titanium and silicon; wherein, the number of titanium and silicon atoms is not too small and not too much; the number of titanium and silicon atoms is too small, and the effect of improving the adhesion is not great; too large a number of titanium and silicon atoms may deteriorate the barrier properties of the barrier layer 12. In a specific embodiment, the atomic number ratio of silicon to molybdenum in the barrier layer 12 is between 0.1 and 0.3, such as 0.2; the atomic number ratio of titanium to molybdenum is between 0.1 and 0.3, for example 0.2.
According to the embodiment of the disclosure, the molybdenum nitride layer including silicon doping and/or titanium doping is used as the barrier layer 12, so that the gap between the barrier layer 12 and the oxide layer 11 can be effectively reduced, the adhesion between the barrier layer 12 and the oxide layer 11 is improved, and the performance of the semiconductor structure is improved.
The barrier layer 12 may be formed by depositing a doped layer followed by a molybdenum nitride layer and then performing a thermal diffusion process. In particular, the doped layer comprises a titanium nitride layer and/or a silicon nitride layer. In a specific embodiment, the thickness of the doped layer ranges between 1nm to 9nm, for example, 4nm to 6 nm; the thickness of the molybdenum nitride layer ranges between 1nm and 9nm, for example, 4nm to 6 nm.
In other embodiments, the barrier layer 12 may be formed by alternately depositing doped layers and molybdenum nitride layers in order to make the silicon doping and/or titanium doping in the barrier layer 12 more uniform. Specifically, doping layers and molybdenum nitride layers are alternately deposited, and then a thermal diffusion process is performed; the doped layer comprises a titanium nitride layer and/or a silicon nitride layer. At this time, each doped layer and eachA thin layer of molybdenum nitride, in a specific embodiment, the barrier layer 12 has a thickness of between 1nm and 10 nm; the thickness of each doped layer can be selected from
To
To (c) to (d); the thickness of each molybdenum nitride layer can be selected from
To
To (c) to (d); the ratio of the total thickness of the doped layers to the total thickness of the molybdenum nitride layer may optionally be in the range of 0.1-0.9. The number of doped layers and molybdenum nitride layers varies with the thickness of each doped layer and each molybdenum nitride layer, given the thickness of the barrier layer 12. Optionally, the number of the doped layers is between 2 and 5; the number of the molybdenum nitride layers is between 2 and 4.
The process for forming the doping layer and the molybdenum nitride layer may be an atomic layer deposition method or a chemical vapor deposition method. Atomic Layer Deposition (ALD) and Chemical Vapor Deposition (CVD) utilize gaseous reactive precursors to form a layer of a target material on a substrate through a series of reactions at a temperature. In the related art, when a molybdenum nitride layer is formed on an oxide layer by Atomic Layer Deposition (ALD) or Chemical Vapor Deposition (CVD), a reaction precursor containing chlorine (e.g., molybdenum pentachloride) is used. The applicant of the present disclosure finds that the chlorine-containing precursor of molybdenum nitride is not resistant to high temperature, so that the formation of the molybdenum nitride layer can only be performed at a relatively low temperature, but the relatively low temperature reduces the rate of chlorine release, so that the finally formed molybdenum nitride layer has a relatively high chlorine content, and the chlorine can corrode the oxide layer, so that a plurality of voids are generated at the interface of the molybdenum nitride layer and the oxide layer, and the adhesion of the molybdenum nitride layer and the oxide layer is affected. When the doping layer is formed by adopting an atomic layer deposition method (ALD) or a chemical vapor deposition method (CVD), the adopted reaction precursor (such as silicon tetrachloride and/or titanium tetrachloride) has good thermal stability, so that the deposited silicon nitride layer and/or titanium nitride layer has less residual chlorine atoms, the gap at the junction of the finally formed barrier layer and the oxide layer can be reduced, and the adhesion of the barrier layer and the oxide layer is enhanced.
In one embodiment, the semiconductor structure further comprises: the conductive layer 13, the conductive layer 13 covers the barrier layer 12, the barrier layer 12 is located between the conductive layer 13 and the oxide layer 11, and is used for blocking the metal material in the conductive layer 13 from migrating into the oxide layer 11 and the substrate 10, and the oxide layer 11 is used for electrically isolating the conductive layer 13 from the substrate 10. In a specific embodiment, the material of the conductive layer 13 includes molybdenum. But is not limited thereto, the material of the conductive layer 13 may further include tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy, or any combination thereof. The forming process of the conductive layer 13 may be Chemical Vapor Deposition (CVD), plasma enhanced CVD (pecvd), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), electroplating, electroless plating, sputtering, or the like.
The oxide layer 11 shown in fig. 1 is located on the substrate 10, in this embodiment, the semiconductor structure may be a Dynamic Random Access Memory (DRAM), and the conductive layer 13 may be a gate layer of a transistor located in a peripheral region of the DRAM.
In another embodiment provided by the present disclosure, the oxide layer 11 is located within the substrate 10, as shown in fig. 2. The substrate 10 includes a trench T therein, the oxide layer 11 covers sidewalls and a bottom surface of the trench T, and the conductive layer 13 fills the trench T. The barrier layer 12 is located between the oxide layer 11 and the conductive layer 13, and the barrier layer 12 covers the sidewalls and the bottom surface of the oxide layer 11. The above layers are described in the above embodiments, and are not described herein. Here, the semiconductor structure may be a dynamic random access memory, and the conductive layer 13 may be a word line buried in the substrate 10. But not limited thereto, the conductive layer 13 may also be a conductive Via, such as a Through Silicon Via (Through Silicon Via), for transmitting signals between different semiconductor structures.
The embodiment of the present application further provides a method for manufacturing a semiconductor structure, as shown in fig. 3, the method includes the following steps:
The method for fabricating the semiconductor structure according to the embodiment of the present disclosure is further described in detail with reference to fig. 4a to 4e and fig. 5a to 5 f.
First, step 301 is performed to provide a substrate 10, and an oxide layer 11 is formed on the substrate 10, as shown in fig. 4 a.
The substrate may be a semiconductor substrate and may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In a specific embodiment, the substrate is a silicon substrate, which may be doped or undoped.
As shown in fig. 4a, the oxide layer 11 is formed on the substrate 10, wherein the oxide layer 11 includes at least one of silicon oxide and silicon oxynitride, and the oxide layer 11 is used to electrically isolate a subsequently formed conductive layer 13 (refer to fig. 1) from the substrate 10. The oxide layer 11 may be formed using one or more thin film deposition processes; in particular, the thin film deposition process includes, but is not limited to, a Chemical Vapor Deposition (CVD) process, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, an Atomic Layer Deposition (ALD) process, or a combination thereof. But not limited thereto, the oxide layer 11 may also be formed by performing a thermal oxidation process on the substrate 10.
Next, step 302 is executed to form a barrier layer 12 on the oxide layer 11; wherein the barrier layer 12 comprises a silicon-doped and/or titanium-doped molybdenum nitride layer, as shown in fig. 4b-4 e.
In one embodiment, the barrier layer 12 is silicon-doped molybdenum nitride; wherein the atomic number ratio of silicon to molybdenum in the barrier layer 12 is between 0.1 and 0.9. But not limited thereto, in another embodiment, the barrier layer 12 is titanium doped molybdenum nitride; wherein the atomic number ratio of titanium to molybdenum in the barrier layer 12 is between 0.1 and 0.9. In another embodiment, the barrier layer 12 is titanium-doped and silicon-doped molybdenum nitride; wherein the atomic number ratio of silicon to molybdenum is between 0.1 and 0.3, and the atomic number ratio of titanium to molybdenum is between 0.1 and 0.3. According to the embodiment of the disclosure, the molybdenum nitride layer including silicon doping and/or titanium doping is used as the barrier layer 12, so that the gap between the barrier layer 12 and the oxide layer 11 can be effectively reduced, the adhesion between the barrier layer 12 and the oxide layer 11 is improved, and the performance of the semiconductor structure is improved.
In one embodiment, forming a barrier layer 12 on the oxide layer 11 includes:
forming a doping layer 121 on the oxide layer 11, wherein the doping layer 121 comprises a titanium nitride layer and/or a silicon nitride layer, as shown in fig. 4 b;
forming a molybdenum nitride layer 122 on the doped layer 121, as shown in fig. 4 c;
a thermal diffusion process is performed to diffuse the doped layer 121 and the molybdenum nitride layer 122 into each other, so as to form the barrier layer 12, as shown in fig. 4 e.
Here, the doping layer 121 may be any one of a silicon nitride layer and a titanium nitride layer, but is not limited thereto, and the doping layer 121 may also be a combination of a titanium nitride layer and a silicon nitride layer, which may be alternately distributed. In a more specific embodiment, the thickness of the doped layer 121 and the thickness of the molybdenum nitride layer 122 each range between 1 nanometer and 9 nanometers.
In this embodiment, the doped layer 121 and the molybdenum nitride layer 122 are each one layer in number. But not limited thereto, the number of the doped layers 121 may be multiple layers as shown in fig. 4 d. In one embodiment, as shown in fig. 4d and 4e, forming a barrier layer 12 on the oxide layer 11 includes:
depositing doping layers 121 and molybdenum nitride layers 122 alternately on the oxide layer 11 in sequence, wherein the doping layers 121 comprise titanium nitride layers and/or silicon nitride layers, as shown in fig. 4 d;
a thermal diffusion process is performed to diffuse the doped layer 121 and the molybdenum nitride layer 122 into each other, so as to form the barrier layer 12, as shown in fig. 4 e.
In this embodiment, the number of the doping layers 121 is multiple, any one of the multiple doping layers 121 may be a silicon nitride layer or a titanium nitride layer, or may be a combination of a silicon nitride layer and a titanium nitride layer, and any two adjacent doping layers 121 are separated by a molybdenum nitride layer 122. In one embodiment, the number of doped layers 121 ranges between 2-5 and the number of molybdenum nitride layers 122 ranges between 2-4. In one embodiment, the ratio of the total thickness of each doped layer 121 to the thickness of the barrier layer 12 ranges between 0.1 and 0.9. In a more specific embodiment, the thickness of the barrier layer 12 is between 1 nanometer and 10 nanometers.
In one embodiment, the doping layer 121 and the molybdenum nitride layer 122 are formed by using an atomic layer deposition method or a chemical vapor deposition method.
Atomic Layer Deposition (ALD) and Chemical Vapor Deposition (CVD) utilize gaseous reactive precursors to form a layer of a target material on a substrate through a series of reactions at a temperature. In the related art, when a molybdenum nitride layer is formed on an oxide layer by Atomic Layer Deposition (ALD) or Chemical Vapor Deposition (CVD), a reaction precursor containing chlorine (e.g., molybdenum pentachloride) is used. The applicant of the present disclosure finds that the chlorine-containing precursor of molybdenum nitride is not resistant to high temperature, so that the formation of the molybdenum nitride layer can only be performed at a relatively low temperature, but the relatively low temperature reduces the rate of chlorine release, so that the finally formed molybdenum nitride layer has a relatively high chlorine content, and the chlorine can corrode the oxide layer, so that a plurality of voids are generated at the interface of the molybdenum nitride layer and the oxide layer, and the adhesion of the molybdenum nitride layer and the oxide layer is affected. When the doping layer is formed by adopting an atomic layer deposition method (ALD) or a chemical vapor deposition method (CVD), the adopted reaction precursor (such as silicon tetrachloride and/or titanium tetrachloride) has good thermal stability, so that residual chlorine atoms in the deposited silicon nitride layer and/or titanium nitride layer are less, the gap at the junction of the finally formed barrier layer and the oxide layer can be reduced, and the adhesion of the barrier layer and the oxide layer is improved.
In an embodiment, after forming the barrier layer 12 on the oxide layer 11, the method further includes: an electrically conductive layer 13 is formed on the barrier layer 12, the material of the electrically conductive layer 13 comprising molybdenum, as shown in fig. 1. But is not limited thereto, the material of the conductive layer 13 may further include tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy, or any combination thereof. The conductive layer 13 may be formed on the barrier layer 12 using a process such as Chemical Vapor Deposition (CVD), plasma enhanced CVD (pecvd), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), electroplating, electroless plating, sputtering, and the like. The barrier layer 12 is used to block the metal material in the conductive layer 13 from migrating into the oxide layer 11 and the substrate 10.
An oxide layer 11 shown in fig. 4a to 4e is formed on the substrate 10, in this embodiment, the semiconductor structure may be a Dynamic Random Access Memory (DRAM), and the conductive layer 13 may be a gate layer of a transistor located in a peripheral region of the DRAM.
In another embodiment provided by the present disclosure, the oxide layer 11 is formed in the substrate 10, as shown in fig. 5a to 5 f.
First, referring to fig. 5a and 5b, an oxide layer 11 is formed in the substrate 10, including:
forming a patterned mask (not shown in the figure) on the substrate 10, performing an etching process on the substrate 10 by using the patterned mask as an etching mask, and etching from the surface of the substrate 10 to the inside of the substrate 10 to form a trench T, as shown in fig. 5 a; the forming process of the groove T can be dry etching, such as plasma etching; the shape of the trench T opening may be a rectangle extending within the substrate 10, but is not limited thereto, and the shape of the trench T opening may also be a circle or an ellipse.
The oxide layer 11 is formed in the trench T, and the oxide layer 11 covers the sidewall and the bottom surface of the trench T, as shown in fig. 5 b.
Next, as shown in fig. 5c-5f, a barrier layer 12 is formed on the oxide layer 11, wherein the barrier layer 12 comprises a silicon-doped and/or titanium-doped molybdenum nitride layer.
In one embodiment, forming a barrier layer 12 on the oxide layer 11 includes:
forming a doping layer 121 on the oxide layer 11, wherein the doping layer 121 covers the sidewall and the bottom surface of the oxide layer 11, and the doping layer 121 comprises a titanium nitride layer and/or a silicon nitride layer, as shown in fig. 5 c;
forming a molybdenum nitride layer 122 on the doped layer 121, wherein the molybdenum nitride layer 122 covers the sidewalls and the bottom surface of the doped layer 121, as shown in fig. 5 d;
a thermal diffusion process is performed to diffuse the doped layer 121 and the molybdenum nitride layer 122 into each other, so as to form the barrier layer 12, as shown in fig. 5 f.
Here, the doping layer 121 may be one of a silicon nitride layer or a titanium nitride layer. But not limited thereto, the doped layer 121 may also be a combination of titanium nitride layers and silicon nitride layers, which may be alternately distributed. In a specific embodiment, the thickness of the doped layer 121 and the thickness of the molybdenum nitride layer 122 are both in a range of 1nm to 9 nm.
In this embodiment, the doped layer 121 and the molybdenum nitride layer 122 are each one layer in number. But not limited thereto, the number of the doped layers 121 may also be multiple layers, as shown in fig. 5 e. In one embodiment, as shown in fig. 5e and 5f, forming a barrier layer 12 on the oxide layer 11 includes:
depositing doping layers 121 and molybdenum nitride layers 122 on the sidewalls and the bottom surface of the oxide layer 11 in sequence, wherein the doping layers 121 comprise titanium nitride layers and/or silicon nitride layers, as shown in fig. 5 e;
a thermal diffusion process is performed to diffuse the doped layer 121 and the molybdenum nitride layer 122 into each other, so as to form the barrier layer 12, as shown in fig. 5 f.
In this embodiment, the number of the doping layers 121 is multiple, any one of the multiple doping layers 121 may be a silicon nitride layer or a titanium nitride layer, or may be a combination of a silicon nitride layer and a titanium nitride layer, and any two adjacent doping layers 121 are separated by a molybdenum nitride layer 122. In one embodiment, the number of doped layers 121 ranges between 2-5 and the number of molybdenum nitride layers 122 ranges between 2-4. In one embodiment, the ratio of the total thickness of each doped layer 121 to the thickness of the barrier layer 12 ranges between 0.1 and 0.9. In a more specific embodiment, the thickness of the barrier layer 12 is between 1 nanometer and 10 nanometers.
The process of forming the doped layer 121 and the molybdenum nitride layer 122 is the same as that described above, and thus, the description thereof is omitted.
Finally, as shown in fig. 2, after forming a barrier layer 12 on the oxide layer 11, a conductive layer 13 is formed on the barrier layer 12, and the conductive layer 13 fills the trench T. In this embodiment, the semiconductor structure may be a dynamic random access memory, and the conductive layer 13 may be a word line embedded in the substrate 10, or the conductive layer 13 may also be a conductive Via, such as a Through Silicon Via (Through Silicon Via), for transmitting signals between different semiconductor structures.
It should be understood that the above-described steps can be changed in sequence by those skilled in the art without departing from the scope of the present disclosure, and that the above-described is only an alternative embodiment of the present disclosure and is not intended to limit the scope of the present disclosure, and any modification, equivalent replacement, and improvement made within the spirit and principle of the present disclosure should be included in the scope of the present disclosure.
Claims (18)
1. A semiconductor structure, comprising:
a substrate;
an oxide layer on and/or within the substrate;
the barrier layer covers the oxide layer and is in contact with the oxide layer;
wherein the barrier layer comprises a silicon-doped and/or titanium-doped molybdenum nitride layer.
2. The semiconductor structure of claim 1, wherein the barrier layer is silicon-doped molybdenum nitride; wherein the atomic number ratio of silicon to molybdenum in the barrier layer is between 0.1 and 0.9.
3. The semiconductor structure of claim 1, wherein the barrier layer is titanium doped molybdenum nitride; wherein the atomic number ratio of titanium to molybdenum in the barrier layer is between 0.1 and 0.9.
4. The semiconductor structure of claim 1, wherein the barrier layer is titanium-doped and silicon-doped molybdenum nitride; wherein the atomic number ratio of silicon to molybdenum in the barrier layer is between 0.1 and 0.3, and the atomic number ratio of titanium to molybdenum is between 0.1 and 0.3.
5. The semiconductor structure of claim 1, wherein the oxide layer comprises at least one of silicon oxide and silicon oxynitride.
6. The semiconductor structure of claim 1, further comprising: a conductive layer overlying the barrier layer.
7. The semiconductor structure of claim 6, wherein a material of the conductive layer comprises molybdenum.
8. The semiconductor structure of claim 6, wherein the substrate comprises a trench therein, the oxide layer covers sidewalls and a bottom surface of the trench, and the conductive layer fills the trench.
9. The semiconductor structure of claim 8, wherein the semiconductor structure is a Dynamic Random Access Memory (DRAM) and the conductive layer is a wordline.
10. A method of fabricating a semiconductor structure, comprising:
providing a substrate, and forming an oxide layer on and/or in the substrate;
forming a barrier layer on the oxide layer; wherein the barrier layer comprises a silicon-doped and/or titanium-doped molybdenum nitride layer.
11. The method of claim 10, wherein forming a barrier layer over the oxide layer comprises:
forming a doping layer on the oxidation layer, wherein the doping layer comprises a titanium nitride layer and/or a silicon nitride layer;
forming a molybdenum nitride layer on the doped layer;
and performing a thermal diffusion process to diffuse the doping layer and the molybdenum nitride layer mutually to form the barrier layer.
12. The method of claim 11, wherein the thickness of the doped layer and the thickness of the molybdenum nitride layer are each in a range of 1nm to 9 nm.
13. The method of claim 11, wherein the doping layer and the molybdenum nitride layer are formed by atomic layer deposition or chemical vapor deposition.
14. The method of claim 10, wherein forming a barrier layer over the oxide layer comprises:
depositing doping layers and molybdenum nitride layers on the oxide layer in sequence, wherein the doping layers comprise titanium nitride layers and/or silicon nitride layers;
and performing a thermal diffusion process to diffuse the doping layer and the molybdenum nitride layer mutually to form the barrier layer.
15. The method as claimed in claim 14, wherein the number of doped layers is in the range of 2-5, and the number of molybdenum nitride layers is in the range of 2-4.
16. The method of claim 15, wherein a ratio of a total thickness of each doped layer to a thickness of the barrier layer is in a range of 0.1-0.9.
17. The method of claim 15, wherein the barrier layer has a thickness of between 1nm and 10 nm.
18. The method of claim 10, further comprising, after forming a barrier layer on the oxide layer: and forming a conductive layer on the barrier layer, wherein the material of the conductive layer comprises molybdenum.
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| CN117238848B (en) * | 2023-11-15 | 2024-02-02 | 合肥晶合集成电路股份有限公司 | Contact hole structure and forming method thereof |
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