CN114496972A

CN114496972A - Ball grid array package and package substrate thereof

Info

Publication number: CN114496972A
Application number: CN202011253285.1A
Authority: CN
Inventors: 许哲铭; 林松源; 旋乃仁; 王侑信
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2020-11-11
Filing date: 2020-11-11
Publication date: 2022-05-13

Abstract

The disclosure relates to a ball grid array package and a package substrate thereof. A package substrate is suitable for a ball grid array package. The substrate includes two board contacts, two solder ball pads, two communication holes and two signal lines, wherein the connection line of the two board contacts is perpendicular to the connection line of the two solder ball pads, the two signal lines respectively connect the two board contacts to the communication holes, each signal line includes a wiring section, a proximity section and a bifurcation section which are connected in sequence, the two wiring sections are arranged substantially in parallel, the two proximity sections are arranged substantially in parallel and are substantially symmetrical to the connection line of the solder ball pads, and the bifurcation section is substantially symmetrical to the connection line of the solder ball pads and is respectively electrically connected with the two communication holes.

Description

Ball grid array package and package substrate thereof

Technical Field

The present invention relates to a package substrate, and more particularly, to a substrate for ball grid array package and the ball grid array package.

Background

Ball Grid Array (Ball Grid Array) Packaging is a Surface-mounting Packaging technology for Packaging chips (Integrated Circuits) on a circuit board. The circuit board has a plurality of solder balls arranged in an array, a plurality of contacts for electrically connecting the chip, and a plurality of wires for electrically connecting the contacts and the solder balls, respectively. Wherein, the design requirement of the wiring for transmitting the differential signal (differential signal) is higher than the requirement of the wiring for transmitting other signals.

In the united states, patent application No. 2016/0358866, "Package substrate Differential impedance optimization for 25G bps and beyond", published on 8.12.2016 and patent application No. 2018/0368260, "High-speed printed circuit board and Differential wiring method of", published on 20.12.2018, the Differential wiring is designed to overcome the signal delay problem, Differential reflection loss (Differential return loss), and Differential insertion loss (Differential insertion loss) of Differential signals caused by different lengths of positive and negative wirings.

Disclosure of Invention

According to some embodiments, a ball grid array package includes a chip and a substrate. The chip includes two chip contacts. The substrate includes two board contacts, two solder ball pads, two vias, and two signal lines. The connection line of the two board contacts is a contact connection line, and the two chip contacts are electrically connected with the two board contacts. The connection line of the two ball pads is the connection line of the bonding pad, and the connection line of the contact is not substantially parallel to the connection line of the bonding pad. The two through holes are substantially symmetrical to the bonding pad connection line, and the two through holes are respectively and electrically connected with the two ball pads. Each signal line comprises a wiring section, a proximity section and a bifurcation section which are connected in sequence, wherein the two wiring sections are respectively and electrically connected with the two board contacts and are arranged in a substantially parallel way, the two proximity sections are arranged in a substantially parallel way and are substantially symmetrical to the welding pad connecting line, and the bifurcation section is substantially symmetrical to the welding pad connecting line and is respectively and electrically connected with the two communicating holes.

According to some embodiments, a junction of each of the diverging section and the proximal section is located at a distance of 100 to 250 μm from the ball pad.

According to some embodiments, the lengths of the bifurcated segments are substantially the same.

According to some embodiments, each of the branch sections includes an oblique section and a straight section, the two oblique sections are respectively electrically connected to the two adjacent sections, and the two straight sections are substantially parallel to the bonding pad connection line and are respectively electrically connected to the two through holes.

According to some embodiments, each of the branch sections sequentially includes an oblique section, a straight section and a lead-in section, the two oblique sections are respectively electrically connected to the two adjacent sections, the two straight sections are substantially parallel to the solder ball pad connection line, and the two lead-in sections are respectively electrically connected to the two communication holes.

According to some embodiments, each oblique segment has an angle of 35 to 55 degrees with respect to a connection line of the solder ball pad, each oblique segment has a distance of 50 to 150 micrometers from the adjacent solder ball pad, each straight segment has a distance of 50 to 150 micrometers from the adjacent solder ball pad, and an outer diameter of each solder ball pad is 300 to 600 micrometers.

According to some embodiments, the two signal lines have a predetermined impedance, and the length of each of the two branches has a predetermined relationship with the distance between the two vias, wherein the predetermined relationship makes the impedance of the two vias lower than the predetermined impedance and the impedance of the two branches higher than the predetermined impedance.

According to some embodiments, a package substrate is adapted to package a chip having two chip contacts. The package substrate includes two board contacts, two solder ball pads, two vias, and two signal lines. One of the two board contacts is a contact connection line, and the two board contacts are suitable for electrically connecting the two chip contacts. One of the two solder ball pads is a solder pad connection line, and the contact connection line is not substantially parallel to the solder pad connection line. The two through holes are substantially symmetrical to the bonding pad connection line, and the two through holes are respectively and electrically connected with the two ball pads. Each signal line includes a wiring section, a proximity section and a branch section which are connected in sequence, the two wiring sections are respectively and electrically connected with the two board contacts and are arranged in parallel, the two proximity sections are arranged in parallel and are symmetrical to the bonding pad connection line, and the branch section is symmetrical to the bonding pad connection line and is respectively and electrically connected with the two communication holes.

In summary, according to some embodiments, the differential signal lines of the package substrate include a branch section, the branch section is symmetrical to the pad connecting line and electrically connected to the via, and the via is also symmetrical to the pad connecting line, so that the lengths of the two signal lines in the same pair of differential signal lines are substantially the same, and the time difference in the transmission of the differential signal is reduced. In some embodiments, the impedance of the differential signal line can be made closer to the designed impedance by adjusting the relationship between the length of the branch section and the fifth distance.

Drawings

FIG. 1A illustrates a bottom view of a ball grid array package, according to some embodiments;

FIG. 1B illustrates a side view of the ball grid array package of FIG. 1A;

FIG. 2 illustrates a partial top view of a chip, wire and ball pads of a ball grid array package (cover not shown), according to some embodiments;

FIG. 3 is a partial perspective view of a chip, a pair of differential signal lines and ball pads of a BGA package according to some embodiments (only one pair of differential signal lines is shown);

FIG. 4 illustrates a partial schematic view of a chip, wire and ball pads of a ball grid array package, according to some embodiments;

FIG. 5 is a graph of differential reflection loss of a pair of differential signal lines of FIGS. 2 and 4;

FIG. 6 is a graph of differential insertion loss of a pair of differential signal lines of FIGS. 2 and 4;

FIG. 7 is a graph of insertion loss of the Mode-converted (Mode Conversion) differential to common Mode noise for the pair of differential signal lines in FIGS. 2 and 4;

FIG. 8 is a diagram of a Time Domain Reflectometry (TDR) signal for a pair of differential signal lines of FIGS. 2 and 4;

FIG. 9 illustrates a partial enlarged view of a pair of differential signal lines according to some embodiments; and

FIG. 10 illustrates a partial enlarged view of a pair of differential signal lines, according to some embodiments.

Detailed Description

Referring to fig. 1A and 1B, fig. 1A illustrates a bottom view of a ball grid array package, according to some embodiments. FIG. 1B illustrates a side view of the ball grid array package of FIG. 1A. A Ball Grid Array Package (BGA Package) includes a substrate 10, a chip 20, solder balls 30, and a cover 40. The substrate 10 has a plurality of wirings (Circuit Traces) for electrically connecting a plurality of contacts (described later) of the chip 20 to the plurality of solder balls 30, respectively. The cover 40 covers the chip 20 and the substrate 10 to protect the wiring on the chip 20 and the substrate 10. In some embodiments, the contacts of the chip 20 are electrically connected to the corresponding wires by wire bonds, respectively. In some embodiments, the chip 20 is a flip chip, and the chip 20 is electrically connected to the corresponding wiring in a flip chip manner. In some embodiments, the substrate 10 is a circuit board, which may be a multi-layer circuit board, such as but not limited to a four-layer or six-layer circuit board, the number of layers of the circuit board being designed according to the characteristics and the number of contacts of the chip 20. In some embodiments, the material of the cover 40 is metal, plastic, glass or ceramic.

Referring to fig. 2, fig. 2 illustrates a partial top view of a chip, wires and ball pads of a ball grid array package according to some embodiments (only a portion of the chip, a portion of the wires and a portion of the ball pads are shown, and the cover 40 is not shown). Chip 20 includes a plurality of chip contacts 22(chip contacts), and in some embodiments, chip contacts 22 include

differential die contacts

24a,24b,26a,26b and common die contacts 28. Wherein, the

differential die pads

24a,24b are called the first pair of differential die pads, which are the positive and negative terminal pads, respectively, and are used to transmit differential signals (differential signals); the

differential die pads

26a,26b are referred to as a second pair of differential die pads for transmitting differential signals. Typically die bond 28 may be an output bond, an input bond, or a sense bond.

The substrate 10 includes a plurality of board contacts 12(substrate contacts), and in some embodiments the board contacts 12 include

differential board contacts

14a,14b,16a,16b and general board contacts 18 (

differential board contacts

14a,14b are referred to below as a first pair of differential board contacts;

differential board contacts

16a,16b are referred to below as a second pair of differential board contacts).

The board contacts 12 are electrically connected to the chip contacts 22 respectively. In the embodiment of fig. 2, the board contacts 12 are electrically connected to the corresponding chip contacts 22 by differential leads 17a, differential leads 17b and common leads 17c, respectively, wherein the differential leads 17a,17b are leads for connecting the

differential board contacts

14a,14b,16a,16b and the

differential die contacts

24a,24b,26a,26b, and the common leads 17c are leads for connecting the common board contacts 18 and the common die contacts 28.

The substrate 10 includes a plurality of communication holes 52, and in some embodiments, the communication holes 52 include

differential communication holes

54a,54b,56a,56b and a general communication hole 58 (the

differential communication holes

54a,54b are referred to as a first pair of differential communication holes; and the

differential communication holes

56a,56b are referred to as a second pair of differential communication holes).

The substrate 10 includes a plurality of signal lines 62 (i.e., the aforementioned wiring), and the signal lines 62 are used to electrically connect the board contacts 12 to the communication holes 52, respectively. In some embodiments, the signal lines 62 include

differential signal lines

64a,64b,66a,66b and common signal lines 68 (the

differential signal lines

64a,64b are referred to as a first pair of differential signal lines; and the

differential signal lines

66a,66b are referred to as a second pair of differential signal lines).

The substrate 10 includes a plurality of ball pads 72 (illustrated by circles formed by dotted lines), and each of the ball pads 72 is electrically connected to the via 52. In some embodiments, the ball pads 72 include

differential ball pads

74a,74b,76a,76b and a common ball pad 78 (the

differential ball pads

74a,74b are referred to below as a first pair of differential ball pads; the

differential ball pads

76a,76b are referred to below as a second pair of differential ball pads).

The connection line of the first pair of

differential board contacts

14a,14b is referred to as a contact connection line L1 (a virtual connection line, shown in a generally horizontal orientation, the contact connection line L1 includes extension lines that extend beyond the first pair of

differential board contacts

14a,14 b). In some embodiments, contact line L1 is a line connecting the positions of the positive and negative terminal

differential plate contacts

14a,14b of the first pair of

differential plate contacts

14a,14b, such as, but not limited to, a line connecting the centers of the positive and negative terminal

differential plate contacts

14a,14b (as shown in fig. 2), a line connecting the vertices of the positive and negative terminal

differential plate contacts

14a,14b, or a line connecting the bottom ends of the positive and negative terminal

differential plate contacts

14a,14 b. The connection line between the first pair of

differential ball pads

74a,74b is referred to as a pad connection line L2 (a virtual connection line, shown in a generally vertical orientation, the pad connection line L2 includes an extension line that extends beyond the first pair of

differential ball pads

74a,74 b). In some embodiments, the pad connection line L2 is a connection line between the positions of the positive and negative side

differential ball pads

74a,74b of the first pair of

differential ball pads

74a,74b, such as but not limited to a connection line between the centers of the positive and negative side

differential ball pads

74a,74b (as shown in fig. 2), or a connection line between the same quartile point (quartile point) of the positive and negative side

differential ball pads

74a,74 b. In the embodiment of fig. 2, the contact line L1 is not substantially parallel to the pad line L2. In some embodiments, the non-substantially parallel relationship between the contact line L1 and the pad line L2 is substantially perpendicular (as shown in fig. 2), or the angle between the contact line L1 and the pad line L2 is substantially 45 degrees, or between 45 degrees and 90 degrees (hereinafter "non-substantially parallel"). In some embodiments, the first pair of

differential ball pads

74a,74b is near a side (the lower boundary of fig. 2) of the substrate 10, and the pad connection line L2 is substantially perpendicular to the side. In the embodiment of fig. 2, the first pair of

differential ball pads

74a,74b is located near the bottom edge of the substrate 10 (i.e., the lower edge, in the orientation of fig. 2, corresponding to the lower boundary of the substrate of fig. 1A). In some embodiments, the pad connection line L2 'of the second pair of

differential ball pads

76a,76b is not substantially parallel to the contact connection line L1' of the second pair of

differential board contacts

16a,16 b.

At least one pair of the

differential vias

54a,54b,56a,56b is disposed substantially symmetrically to the corresponding pad connecting lines L2, L2'. In the embodiment of fig. 2, the first pair of

differential vias

54a,54b is symmetrical to the pad connection line L2, and the second pair of

differential vias

56a,56b is symmetrical to the pad connection line L2'.

Please read it in conjunction with fig. 3. FIG. 3 is a partial perspective view of a chip, a pair of differential signal lines, and ball pads of a BGA package according to some embodiments (only one pair of differential signal lines is shown). Fig. 3 shows the first pair of

differential die contacts

24a,24b, the first pair of

differential plate contacts

14a,14b, the first pair of

differential signal lines

64a,64b, the first pair of

differential vias

54a,54b, and the first pair of

differential ball pads

74a,74b (the first pair of differential signal lines 64a,6b will be described below with the corresponding device names not being referred to as "first pair" for brevity). As can be seen from fig. 3, the substrate 10 is a multi-layer board, the

differential board contacts

14a,14b and the

differential signal lines

64a,64b are located on the top layer of the substrate 10, the

differential ball pads

74a,74b are located on the bottom layer of the substrate 10, the

differential signal lines

64a,64b are electrically connected to the

differential vias

54a,54b, and the

differential vias

54a,54b are electrically connected to the top layer and the bottom layer and are electrically connected to the

differential ball pads

74a,74b located on the bottom layer. In addition, the

solder balls

30a,30b are electrically connected to the corresponding differential

solder ball pads

74a,74 b.

The differential signal line 64a includes a wiring section 80a, a proximity section 82a and a branch section 84a electrically connected in sequence, and the differential signal line 64b includes a wiring section 80b, a proximity section 82b and a branch section 84b electrically connected in sequence. The two ends of the differential signal line 64a are electrically connected to the differential board contact 14a and the differential via 54a, respectively, and the two ends of the differential signal line 64b are electrically connected to the differential board contact 14b and the differential via 54b, respectively, i.e. one end of the

wiring segment

80a,80b is electrically connected to the

differential board contact

14a,14b, respectively, and one end of the branching

segment

84a,84b is electrically connected to the differential via 54a,54b, respectively.

The

wire segments

80a,80b are arranged substantially in parallel, and thus, the lengths of the two

wire segments

80a,80b are substantially the same. In some embodiments, the

wiring segments

80a,80b include a plurality of turns, and the number and angle of the turns depend on the overall wiring requirements of the substrate 10. The

wire segments

80a,80b are bent into the neighboring

segments

82a,82b at an appropriate distance from the

differential ball pads

74a,74b, and the neighboring

segments

82a,82b are substantially parallel and substantially symmetrical to the pad connection line L2 (see fig. 2), so that the lengths of the neighboring

segments

82a,82b are substantially the same. In some embodiments, the lengths of the respective

adjacent segments

82a,82b are substantially different (e.g., the lengths of the

adjacent segments

82a,82b of the first pair of

differential signal lines

64a,64b are different from the adjacent segments of the second pair of

differential signal lines

66a,66b as shown in fig. 2). In some embodiments, the lengths of each pair of

proximal segments

82a,82b are substantially the same. When the

adjacent segments

82a,82b are separated from the

differential ball pads

74a,74b by a predetermined distance (described later), the

adjacent segments

82a,82b are respectively turned into

branch segments

84a,84b, and the

branch segments

84a,84b are substantially symmetrical to the pad connection line L2, so the lengths of the

branch segments

84a,84b are substantially the same. Therefore, the lengths of the

differential signal lines

64a,64b are substantially the same, so that the time for the differential signal to be transmitted between the

differential board contacts

14a,14b and the

differential communication holes

54a,54b is substantially the same, and the quality of the differential signal transmission is correspondingly improved. In some embodiments, the aforementioned symmetry may be at least one of length symmetry, width symmetry, and shape symmetry.

Next, to illustrate the signal transmission characteristics of the embodiment of fig. 2, referring to fig. 4, fig. 4 is a partial schematic diagram of a chip, wiring and solder pads of a ball grid array package according to some embodiments, and the embodiment of fig. 4 is a previous generation ball grid array package of the present invention, wherein differential signal lines 69a,69b are used to electrically connect

differential board contacts

19a,19b to differential vias 59a,59b, respectively. In the embodiment of fig. 4, the differential vias 59a,59b are located on the same side of the pad connection line L2 (i.e., on the right side of the pad connection line L2 in fig. 4), and the differential signal lines 69a,69b do not have the

close sections

82a,82b and the

branch sections

84a,84b of the embodiment of fig. 3, but rather include large-angled turns (turns) to electrically connect to the differential vias 59a,59 b. When the angle between the contact line L1 and the pad line L2 is substantially 45 degrees, 45 degrees to 90 degrees, or substantially 90 degrees (substantially perpendicular, as in the embodiment of fig. 4) (i.e., "substantially parallel" as mentioned above), the turning angle of the differential signal lines 69a,69b causes the two differential signal lines 69a,69b to generate a length difference, which causes the differential signal lines 69a,69b to transmit differential signals with a performance different from that of the embodiment of fig. 2.

Referring to fig. 5, fig. 5 is a graph of Differential reflection Loss (Differential reflection Loss) of a pair of Differential signal lines in fig. 2 and 4, wherein the horizontal axis of the graph represents frequency in GHz (10)⁹Hertz, gigahertz); the vertical axis represents differential reflection loss in dB (Decibel). Reference RL4 in fig. 5 is a differential reflection loss curve RL4 of the differential signal lines 69a,69b in fig. 4, the differential signal is inputted from the

differential die pads

24a,24b at the chip 20 side, and the intensity of the reflected signal is received from the

differential die pads

24a,24b to obtain a differential reflection loss curve RL 4. Similarly, reference RL2 in fig. 5 is a differential reflection loss curve RL2 of the

differential signal lines

64a,64b of fig. 2, the differential signal is inputted from the

differential die pads

24a,24b at the chip 20 side, and the reflected signal intensity is received from the

differential die pads

24a,24b to obtain a differential reflection loss curve RL 2. As can be seen from the comparison of the graphs, the signal frequency is less than about 18GHz (corresponding to about 36Gbps, 36x 10)⁹Bit rate), the differential reflection loss curve RL2 of the embodiment of fig. 2 is better than the differential reflection loss curve RL4 of the embodiment of fig. 4. Thus, in the case where the embodiment of FIG. 4 meets the transmission requirement of differential signals, the embodiment of FIG. 2 has better differential reflection loss in applications with a rate less than about 36 Gbps.

Referring to fig. 6, fig. 6 shows a graph of Differential Insertion Loss (GHz) of a pair of Differential signal lines in fig. 2 and 4, wherein the horizontal axis of the graph represents frequency; the vertical axis represents differential insertion loss in dB. The reference IL4 in FIG. 6 is the differential insertion loss curve IL4 of the differential signal lines 69a,69b of FIG. 4, the differential signal being output from the

differential die pads

24a,24b on the chip 20 sideIn addition, the differential signal is received from the

solder balls

30a and 30b to obtain the differential insertion loss curve IL 4. Similarly, reference IL2 in fig. 6 is a differential insertion loss curve IL2 of the

differential signal lines

64a,64b of fig. 2, which are input from the

differential pads

24a,24b on the chip 20 and received from the

solder balls

30a,30b to obtain a differential insertion loss curve IL 2. As can be seen from the comparison of the graphs, the signal frequency is less than about 27GHz (corresponding to about 54Gbps, 54x 10)⁹Bit rate), the differential insertion loss curve IL2 of the embodiment of fig. 2 is better than the differential insertion loss curve IL4 of the embodiment of fig. 4. As can be seen from the differential insertion loss graph, even though the

differential signal lines

64a,64b of the embodiment of fig. 2 include the

branch sections

84a,84b, the

branch sections

84a,84b belong to the single-ended-like signal lines, the effect of the single-ended-like signal lines for transmitting differential signals is generally less good, but the differential insertion loss curve IL2 of the

differential signal lines

64a,64b of the embodiment of fig. 2 for transmitting differential signals is still better than the differential insertion loss curve IL4 of the embodiment of fig. 4. Thus, in the case where the embodiment of FIG. 4 meets the transmission requirement of differential signals, the embodiment of FIG. 2 has better differential insertion loss for applications with a rate less than about 54 Gbps.

Referring to fig. 7, fig. 7 is a graph illustrating an insertion loss of a differential-Mode signal (differential-Mode signal) to a common-Mode noise (common-Mode noise) in a Mode Conversion (Mode Conversion) of a pair of differential signal lines in fig. 2 and 4, wherein a horizontal axis of the insertion loss graph represents a frequency in GHz; the vertical axis represents the insertion loss in dB for mode conversion. Referring to fig. 7, MC4 is a mode-converted insertion loss curve MC4 of the differential signal lines 69a,69b of fig. 4, and a differential-mode signal (differential-mode signal) is inputted from the

differential die pads

24a,24b at the chip 20 side and receives common-mode noise generated by the differential signal lines from the

solder balls

30a,30b to obtain a mode-converted insertion loss curve MC 4. The differential signal lines 69a,69b in fig. 4 have a large angle of transition, so that the symmetry of the positive and negative terminal differential signal lines 69a,69b is not good enough, and the poor symmetry indirectly causes common-mode noise (common-mode noise) on the transmission of the differential signal. Reference MC2 in fig. 7 is an insertion loss curve MC2 of mode conversion of the

differential signal lines

64a,64b of fig. 2, a differential mode signal is inputted from the

differential pads

24a,24b of the chip 20, and common mode noise generated by the differential signal due to the wiring is received from the

solder balls

30a,30b to obtain an insertion loss curve MC2 of mode conversion. As can be seen from a comparison of the graphs, the insertion loss curve MC2 for the mode conversion of the embodiment of fig. 2 is about 6dB better than the insertion loss curve MC4 for the mode conversion of the embodiment of fig. 4.

Referring to fig. 8, fig. 8 is a graph of Time Domain Reflectometry (TDR) of a pair of differential signal lines of fig. 2 and 4, where the horizontal axis represents Time in nanoseconds (ns, 10)^-9Seconds); the vertical axis represents the time domain reflected impedance in Ohms (Ohms). TDR4 shown in fig. 8 is a differential time domain reflection curve TDR4 of the differential signal lines 69a,69b of fig. 4, the impedance of the time domain reflectometer is 100 ohms, the test signal of the time domain reflectometer is inputted from the

solder balls

30a,30b and transmitted to the

differential pads

24a,24b, i.e. the starting time of the horizontal axis of the differential time domain reflectometer is calculated from the input of the test signal from the

solder balls

30a,30b, the preset impedance (also referred to as the design impedance) of the differential signal lines 69a,69b of fig. 4 is 90 ohms, the interval BV4 shown in fig. 8 (the interval of about 2.5 to 2.53ns in the horizontal axis) reflects the impedance curve of the test signal transmitted to the differential via holes 59a,59b through the

solder balls

30a,30b, the impedance measured after the test signal enters the differential signal lines 69a,69b (about 2.53ns in the horizontal axis) rises to approach to the preset impedance 90, and the position of the W mark 4 shows that the test signal leaves the

differential pad

19a,19b and into the differential leads 17a,17 b. It can be seen that the resistance between the

solder balls

30a,30b and the differential via holes 59a,59b is about 77 ohms at the lowest, and about 13 ohms lower than the predetermined resistance (90 ohms).

In fig. 8, denoted TDR2 is a differential time domain reflection curve TDR2 of the

differential signal lines

64a,64b of fig. 2, the test signal of the time domain reflectometer is inputted from the

solder balls

30a,30b and transmitted to the

differential die pads

24a,24b, the predetermined impedance of the

differential signal lines

64a,64b of fig. 2 is 90 ohms, denoted BV2 interval (horizontal axis about 2.5-2.53 ns interval) in fig. 8 reflects the impedance curve of the test signal transmitted to the differential via

holes

54a,54b via the

solder balls

30a,30b, denoted BS interval (horizontal axis about 2.53-2.54 ns interval) reflects the impedance curve BS of the test signal measured at the

branch segments

84a,84b, after denoted BS is W2, the impedance of the test signal measured at the

near segments

82a,82b and the

wiring segments

80a,80b (horizontal axis about 2.54 ns), which is near the predetermined impedance 90 ohms, and the position of the denoted W2 denotes the position of the test signal leaving the

differential pad

14a,14b and into the differential leads 17a,17 b. It can be seen that, since the distance between the differential via

holes

54a,54b of the embodiment of fig. 2 is longer than the distance between the differential via holes 59a,59b of the embodiment of fig. 4, the impedance of the differential via

holes

54a,54b of fig. 2 is higher than the impedance of the differential via holes 59a,59b, so that the impedance between the

solder balls

30a,30b and the differential via holes 59a,59b of the embodiment of fig. 2 is at least about 86 ohms and at most about 95 ohms, and the impedance between the preset impedance (90 ohms) plus and minus 5 ohms, so that the impedance between the

solder balls

30a,30b and the differential via holes 59a,59b of the embodiment of fig. 2 is closer to the preset impedance than the embodiment of fig. 4.

As can be seen from the above, the embodiment of fig. 2 has better electrical characteristics than the embodiment of fig. 4.

Although fig. 2 shows that the chip 20 includes a plurality of pairs of

differential die pads

24a,24b,26a,26b, the implementation is not limited thereto, and the chip 20 may include only one pair of

differential die pads

24a,24b or 26a,26 b. Similarly, the substrate 10 may only include a pair of

differential board contacts

14a,14b or 16a,16b, a pair of

differential signal lines

64a,64b or 66a,66b, and a pair of

differential vias

54a,54b or 56a,56 b.

Referring to fig. 9, fig. 9 is a partially enlarged view of a pair of differential signal lines according to some embodiments. In some embodiments, the diverging

sections

84a,84b diverge away from the pad connection line L2 (see fig. 2) from the

proximal sections

82a,82b, and the distance D1 (hereinafter referred to as the first distance) between the junction of the diverging

sections

84a,84b and the

proximal sections

82a,82b and the differential solder ball pad 74a is about 100 micrometers (um) to about 250 micrometers. As can be seen in fig. 3, the diverging

sections

84a,84b are located on the top layer of the substrate 10, the differential ball pad 74a is located on the bottom layer of the substrate 10, and the first distance D1 indicates the distance from the bond pad line L2 to the edge of the differential ball pad 74a from the center point of the two junctions of the diverging

sections

84a,84b and the

adjacent sections

82a,82b from the perspective of fig. 9 (i.e., the top view of fig. 3).

In some embodiments, the diverging

segments

84a,84b include angled sub-segments 86a,86b, straight sub-segments 88a,88b, and lead-in sub-segments 89a,89 b. The

oblique segments

86a,86b are electrically connected to the

adjacent segments

82a,82b, respectively, the

straight segments

88a,88b are substantially parallel to the pad connection line L2 and both ends thereof are electrically connected to the

oblique segments

86a,86b and the lead-in

segments

89a,89b, respectively, and the lead-in

segments

89a,89b are electrically connected to the

differential vias

54a,54b, respectively.

In some embodiments, the angle θ between the

oblique segments

86a,86b and the bonding pad connection line L2 is about 35 degrees to 55 degrees (e.g., 45 degrees), each

oblique segment

86a,86b is about 50 to 150 microns from the adjacent differential ball pad 74a (hereinafter referred to as the second distance D2), each straight segment is about 50 to 150 microns from the adjacent ball pad (hereinafter referred to as the third distance D3), the outer diameter of each ball pad is about 300 microns to 600 microns (hereinafter referred to as the fourth distance D4), and the distance between the

differential vias

54a,54b is about 70 to 600 microns (hereinafter referred to as the fifth distance D5). The second, third, fourth, and fifth distances D2, D3, D4, D5 refer to the distances from the perspective of fig. 9 (i.e., the top view of fig. 3).

In some embodiments, the

differential vias

54a,54b are located on a vertical line perpendicular to a midpoint of the pad connection line L2 (the connection line of the centers of the

differential ball pads

74a,74 b), so that the lengths of the

vias

54a,54b electrically connected to the

differential ball pads

74a,74b are substantially the same. The lengths of the pairs of

differential board contacts

14a,14b,16a,16b to the

differential ball pads

74a,74b,76a,76b of the substrate 10 are respectively substantially the same, so that the difference in the transmission time of the differential signals is reduced.

In some embodiments, referring to fig. 8 and fig. 9, the lengths of the

branch sections

84a,84b and the fifth distance D5 have a predetermined relationship such that the impedance of the two

differential vias

54a,54b is lower than a predetermined impedance (i.e., a designed impedance) and the impedance of the

branch sections

84a,84b is higher than the predetermined impedance. As shown in fig. 8, the impedance curve BV4 of the

solder balls

30a,30b and the differential via

holes

54a,54b of the embodiment of fig. 4 is lower than the predetermined impedance and lower than the impedance curve BV2 of the embodiment of fig. 2. In some embodiments, by adjusting the distance between the

difference communication holes

54a,54b (the fifth distance D5), the impedance of the

difference communication holes

54a,54b can be properly controlled, i.e., the distance between the

difference communication holes

54a,54b is increased, and the impedance of the

difference communication holes

54a,54b is increased. Next, the

branch sections

84a,84b belong to a single-ended signal line, and the impedance (i.e. the impedance curve BS in fig. 8) of the branch sections is higher than the predetermined impedance of the

adjacent section

82a,82b and the

wiring section

80a,80b, so that the impedance of the

branch sections

84a,84b can be adjusted by adjusting the lengths of the

branch sections

84a,84b, and the longer the lengths of the

branch sections

84a,84b are, the higher the impedance is. In this embodiment, the predetermined relationship between the lengths of the

branch sections

84a,84b and the fifth distance D5 is adjusted such that the impedance of the two

differential communication holes

54a,54b is lower than the predetermined impedance (i.e. the designed impedance) and the impedance of the

branch sections

84a,84b is higher than the predetermined impedance (e.g. the impedance curve between BV2 to BS in fig. 8), thereby obtaining better transmission quality of the differential signal lines. The predetermined relationship may be adjusted by, for example, but not limited to, adjusting an angle θ between the oblique sub-segments 86a,86b and the bonding pad connection line L2, adjusting the second distance D2, adjusting the third distance D3, adjusting an angle between the straight sub-segments 88a,88b and the oblique sub-segments 86a,86b, lengthening or shortening the length of the lead-in sub-segments 89a,89b (even removing the whole lead-in sub-segments 89a,89b, which will be described later), and the like. In addition, the length of the

branch sections

84a,84b and the upper and lower limits of the fifth distance D5 are restricted by the overall layout of the substrate 10, for example, the

branch sections

84a,84b and the adjacent layout should maintain a specified distance to maintain the signal transmission quality between the

branch sections

84a,84b and the adjacent layout; for example, the distance between the differential via

holes

54a and 54b (the fifth distance D5) cannot be so short that the signal quality transmitted through the differential via

holes

54a and 54b is affected, and the fifth distance D5 cannot be so large that the signal quality is affected by the proximity between the differential via

holes

54a and 54b and the adjacent wiring.

Referring next to fig. 10, fig. 10 is a partially enlarged view of a pair of differential signal lines according to some embodiments. In some embodiments, the branch segments 84a ', 84 b' include oblique segments 86a ', 86 b' and straight segments 88a ', 88 b', the oblique segments 86a ', 86 b' being electrically connected to the

proximate segments

82a,82b, respectively, the straight segments 88a ', 88 b' being substantially parallel to the pad connection line L2 and electrically connected to the

differential vias

54a,54b, respectively. The fifth distance D5 ' of the embodiment of fig. 10 is longer than the fifth distance D5 of fig. 9 such that the diverging segments 84a ', 84b ' of the embodiment of fig. 10 do not have lead-in sub-segments 89a,89 b. Next, the included angle θ ' between the diagonal segments 86a ', 86b ' and the bonding pad connecting line L2 in the embodiment of fig. 10 is smaller than the included angle θ between the

diagonal segments

86a,86b and the bonding pad connecting line L2 in fig. 9. In this embodiment, the length of the first distance D1' shown in fig. 10 is longer than the length of the first distance D1 shown in fig. 9. In some embodiments (not shown), the diverging

sections

84a,84b include

oblique sections

86a,86b and lead-in

sections

89a,89b, while the

non-straight sections

88a,88b, i.e., the

oblique sections

86a,86b and lead-in

sections

89a,89b are arranged in a slightly diamond shape.

Referring to fig. 2 and 3 again, according to some embodiments, a package substrate 10 is suitable for packaging a chip 20, and the chip 20 has two

differential die pads

24a and 24 b. The package substrate 10 includes two

differential board contacts

14a,14b, two

differential ball pads

74a,74b, two

differential vias

54a,54b, and two

differential signal lines

64a,64 b. The connection line of the two

differential board contacts

14a,14b is a contact connection line L1, and the two

differential board contacts

14a,14b are adapted to electrically connect the two

differential die contacts

24a,24 b. The connection line between the two

differential ball pads

74a,74b is pad connection line L2, and the contact connection line L1 is substantially perpendicular to the pad connection line L2. The two

differential vias

54a,54b are substantially symmetrical to the pad connection line L2, and the two

differential vias

54a,54b are electrically connected to the two

differential ball pads

74a,74b, respectively. Each

differential signal line

64a,64b includes a

wiring segment

80a,80b, a

proximal segment

82a,82b, and a

branch segment

84a,84b connected in sequence, the two

wiring segments

80a,80b are electrically connected to the two

differential board contacts

14a,14b respectively and arranged substantially in parallel, the two

proximal segments

82a,82b are arranged substantially in parallel and substantially symmetrical to the pad connection line L2, the

branch segments

84a,84b are substantially symmetrical to the pad connection line L2 and electrically connected to the two

differential vias

54a,54b respectively.

Therefore, the package substrate 10 can better transmit differential signals when packaging the differential die pads of the chip.

In summary, in some embodiments, the differential signal lines of the package substrate include a branch section, the branch section is symmetrical to the pad connecting line and electrically connected to the differential via, and the differential via is also symmetrical to the pad connecting line, so that the lengths of the two differential signal lines in the same pair of differential signal lines are substantially the same, and the time difference in differential signal transmission is reduced. In some embodiments, the impedance of the differential signal line and the differential via can be made closer to the designed impedance by adjusting the relationship between the length of the branch section and the fifth distance.

[ notation ] to show

10 base plate

14a differential board contact

14b differential board contact

16a differential board contact

16b differential board contact

17a differential lead

17b differential lead

17c general lead wire

18 general board contact

19a differential board contact

19b differential board contact

20: chip

22 chip contact

24a differential die bond

24b differential die bond

26a differential crystal junction

26b differential crystal junction

28 normal crystal connection point

30 solder ball

30a solder ball

30b solder ball

40: a covering body

52 communicating hole

54a differential communication hole

54b differential communication hole

56a differential communication hole

56b differential communication hole

58 general communication hole

59a differential communication hole

59b differential communication hole

62: signal line

64a differential signal line

64b differential signal line

66a differential signal line

66b differential signal lines

68 general signal line

69a differential signal line

69b differential signal line

72 ball pad

74a differential solder ball pad

74b differential solder ball pad

76a differential solder ball pad

76b differential solder ball pad

78 general solder ball pad

80a Wiring segment

80b wiring segment

82a proximity section

82b proximity segment

84a branch section

84 a' branch section

84b branch section

84 b' branch section

86a oblique subsection

86 a' oblique subsection

86b oblique subsection

86 b' oblique subsection

88a straight section

88 a' straight section

88b straight section

88 b' straight section

89a introduction of subsegments

89b introduction of subsegment

BV2 impedance curve

BV4 impedance curve

BS impedance curve

D1 first distance

D1' first distance

D2 second distance

D3 third distance

D4 fourth distance

D5 fifth distance

A fifth distance D5

IL2 differential insertion loss curve

IL4 differential insertion loss curve

L1 contact line

L1' connection point

L2 bond pad connection

L2' bonding pad connection line

MC2 insertion loss curve for mode conversion

MC4 insertion loss curve for mode conversion

RL2 differential reflection loss Curve

RL4 differential reflection loss Curve

TDR2 differential time domain reflection curve

TDR4 differential time domain reflection curve

Angle theta

Angle of theta

Claims

1. A ball grid array package, comprising:

a chip including two chip contacts; and

a substrate, comprising:

two board contacts, one of which is a contact connection line, the two chip contacts are electrically connected with the two board contacts;

two solder ball pads, one of the two solder ball pads is a solder pad connection line, the contact connection line is not substantially parallel to the solder pad connection line;

two through holes, which are substantially symmetrical to the bonding pad connection line and are respectively electrically connected with the two ball pads; and

two signal lines, each signal line includes a wiring section, a proximity section and a branch section which are connected in sequence, the two wiring sections are respectively and electrically connected with the two board contacts and are arranged in parallel, the two proximity sections are arranged in parallel and are symmetrical to the welding pad connecting line, and the branch section is symmetrical to the welding pad connecting line and is respectively and electrically connected with the two communicating holes.

2. The ball grid array package of claim 1, wherein said bifurcated segments are substantially the same length.

3. The BGA package of claim 1, wherein each of said plurality of branches comprises a ramp section, a straight section and a lead-in section, said ramp section electrically connecting said two adjacent sections, said straight section being substantially parallel to said ball pad connection, said lead-in section electrically connecting said two via holes.

4. The BGA package of claim 3, wherein a junction of each of said diverging sections and said proximate section is spaced from said ball pad by a distance of 100 to 250 microns, an angle between each of said oblique sections and said ball pad is between 35 and 55 degrees, each of said oblique sections is spaced from said adjacent ball pad by 50 to 150 microns, each of said straight sections is spaced from said adjacent ball pad by 50 to 150 microns, and an outer diameter of each of said ball pads is 300 to 600 microns.

5. The BGA package of any one of claims 1-4, wherein the two solder pads are adjacent to a side of the substrate, the solder pad connection is substantially perpendicular to the side.

6. A package substrate, comprising:

two board contacts, one of the two board contacts is a contact connection;

two solder ball pads, one of the two solder ball pads is a solder pad connection line, and the contact connection line is not substantially parallel to the solder pad connection line;

two signal lines, each signal line includes a wiring section, a proximity section and a branch section which are connected in sequence, the two wiring sections are respectively electrically connected with the two board contacts and are arranged in parallel, the two proximity sections are arranged in parallel and are symmetrical to the bonding pad connecting line, and the branch section is symmetrical to the bonding pad connecting line and is respectively electrically connected with the two communicating holes.

7. The package substrate as claimed in claim 6, wherein the lengths of the bifurcated segments are substantially the same.

8. The package substrate as claimed in claim 6, wherein each of the branch sections sequentially comprises an oblique section, a straight section and a lead-in section, the two oblique sections are electrically connected to the two adjacent sections respectively, the two straight sections are substantially parallel to the bonding pad connection line, and the two lead-in sections are electrically connected to the two via holes respectively.

9. The package substrate as claimed in claim 8, wherein a junction between each of the branch sections and the adjacent section is spaced from the solder ball pad by a distance of 100 microns to 250 microns, an included angle between each of the oblique sections and the solder pad line is 35 degrees to 55 degrees, each of the oblique sections is spaced from the adjacent solder ball pad by 50 microns to 150 microns, each of the straight sections is spaced from the adjacent solder ball pad by 50 microns to 150 microns, and an outer diameter of each of the solder ball pads is 300 microns to 600 microns.

10. The package substrate according to any of claims 6 to 9, wherein the two solder ball pads are close to a side of the substrate, and the solder pad connection line is substantially perpendicular to the side.