CN114492286A - Method and device for controlling chip - Google Patents
Method and device for controlling chip Download PDFInfo
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Abstract
The application discloses a method and equipment for controlling a chip, wherein the method comprises the following steps: reading a first process parameter from a chip, wherein the first process parameter is used for indicating the process of the chip; determining a first driving strength of a pad driver of the chip according to the first process parameter; configuring the driving strength of the pad driver to the first driving strength so that the output impedance of the pad driver is matched with the trace impedance of the circuit board carrying the chip. The drive strength of the pad driver of the chip can be determined according to the chip process, so that the output impedance of the pad driver is matched with the wiring impedance of a circuit board carrying the chip, and the problem of impedance mismatching caused by chip process fluctuation is avoided.
Description
Technical Field
The present application relates to the field of chips, and in particular, to a method and an apparatus for controlling a chip.
Background
When designing a chip, the output impedance of the pad driver should be matched to the trace impedance of the circuit board carrying the chip to meet the requirement of signal integrity. However, chip process fluctuation affects the output impedance of the pad driver, so that the output impedance of the pad driver and the trace impedance of the circuit board have impedance mismatch.
Disclosure of Invention
In view of the above, the present application provides a method and an apparatus for controlling a chip to solve the problem of impedance mismatch caused by chip process fluctuation.
A first aspect provides a method of controlling a chip, the method comprising reading a first process parameter from a chip, the first process parameter being indicative of a process of the chip; determining a first driving strength of a pad driver of the chip according to the first process parameter; configuring the driving strength of the pad driver to the first driving strength so that the output impedance of the pad driver is matched with the trace impedance of the circuit board carrying the chip.
Optionally, the determining a first driving strength of a pad driver of the chip according to the first process parameter includes: determining a first driving strength of the pad driver according to the first process parameter and a second driving strength of the pad driver, wherein the second driving strength is determined based on the trace impedance of the circuit board.
Optionally, the determining the first driving strength of the pad driver according to the first process parameter and the second driving strength of the pad driver includes: and determining the first driving strength by inquiring prestored mapping relation information according to the first process parameter and the second driving strength of the pad driver, wherein the mapping relation information comprises the mapping relation among the first process parameter, the first driving strength and the second driving strength.
Optionally, the configuring the driving strength of the pad driver to the first driving strength includes: and programming the value of the first driving strength into a register of a port control circuit of the chip.
Optionally, the first process parameter is read from a fuse module of the chip.
Optionally, the first process parameter indicates a process corner of the first chip.
Optionally, the chip is a baseband chip.
A second aspect provides an apparatus for controlling a chip, the apparatus comprising: a memory to store instructions;
a processor to execute the instructions to perform operations comprising: reading a first process parameter from a chip, wherein the first process parameter is used for indicating the process of the chip; determining a first driving strength of a pad driver of the chip according to the first process parameter; configuring the driving strength of the pad driver to the first driving strength so that the output impedance of the pad driver is matched with the trace impedance of the circuit board carrying the chip.
Optionally, the determining a first driving strength of a pad driver of the chip according to the first process parameter includes: determining a first driving strength of the pad driver according to the first process parameter and a second driving strength of the pad driver, wherein the second driving strength is determined based on the trace impedance of the circuit board.
Optionally, the determining the first driving strength of the pad driver according to the first process parameter and the second driving strength of the pad driver includes: and determining the first driving strength by inquiring prestored mapping relation information according to the first process parameter and the second driving strength of the pad driver, wherein the mapping relation information comprises the mapping relation among the first process parameter, the first driving strength and the second driving strength.
Optionally, the configuring the driving strength of the pad driver to the first driving strength includes: and programming the value of the first driving strength into a register of a port control circuit of the chip.
Optionally, the first process parameter is read from a fuse module of the chip.
Optionally, the first process parameter indicates a process corner of the first chip.
Optionally, the chip is a baseband chip.
In a third aspect, there is provided a computer readable storage medium having stored thereon executable code which, when executed, is capable of implementing the method of the first aspect.
In a fourth aspect, there is provided a computer program product comprising executable code which, when executed, is capable of implementing the method of the first aspect.
The technical scheme provided by the embodiment of the application can determine the driving strength of the pad driver of the chip according to the chip process, so that the output impedance of the pad driver is matched with the wiring impedance of the circuit board bearing the chip, and impedance mismatching caused by chip process fluctuation is avoided, and the performance of the chip is influenced.
Drawings
Fig. 1 is a schematic diagram of an I/O circuit of a chip according to an embodiment of the present disclosure.
Fig. 2 is a flowchart illustrating a method for controlling a chip according to an embodiment of the present disclosure.
Fig. 3 is a schematic diagram of a method for controlling a chip according to an embodiment of the present disclosure.
Fig. 4 is a schematic flowchart of another method for controlling a chip according to an embodiment of the present disclosure.
Fig. 5 is a schematic diagram of another method for controlling a chip according to an embodiment of the present disclosure.
Fig. 6 is a schematic structural diagram of an apparatus for controlling a chip according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
An Integrated Circuit (IC) may be a micro electronic device or component, and may be manufactured by interconnecting transistors, diodes, resistors, capacitors, inductors, and other elements and wires required in the circuit together on a dielectric substrate and packaged in a package to form a micro structure with the required circuit function. With the improvement of IC design level and industrial manufacturing process capability, System On Chip (SOC) becomes the mainstream of IC design. The SOC may be an application specific IC that integrates all of the functional modules of the system, which may include, for example, a CPU processor, a channel encoder, a digital signal processor, a modem, and an interface module, on a single semiconductor chip. The baseband chip may be a highly integrated system on a chip.
The interface module of the chip may include an interface circuit, which may include an Input/Output (I/O) circuit of the chip, and specific terms in the I/O circuit and the I/O circuit of the chip are described below with reference to fig. 1. The left side of fig. 1 is a schematic circuit diagram of the chip I/O, and it can be seen that the chip I/O circuit may include a pad driver, an output resistor, and an I/O pad, and the pad driver, the output resistor, and the pad may form an I/O circuit in a serial connection manner. I/O PADs (I/O PADs), which may be General Purpose I/O ports (GPIOs).
In some embodiments, the I/O circuitry may further include Port Control Logic (PCL) that may logically control the chip I/O PAD, the PCL may map different hardware functions on the I/O PAD, for example, the PCL may coordinate various situations in which the same PAD is used by different interface modules and program configuration data into PCL registers to enable the PCL to logically control the chip I/O PAD. In some embodiments, the PCL may also define some additional appliance attributes, such as pull-up/pull-down. In other embodiments, the PCL may also control the physical state of the I/O PAD such that the I/O PAD is one of activated, deactivated, and asleep.
Shown in the middle of fig. 1 is the routing of a Circuit Board (PCB) carrying the chip. In some embodiments, the chip I/opad may be connected to the pins of the chip through wires, and the pins of the chip may be soldered to the PCB carrying the chip, so as to transmit the chip signals. On the right of fig. 1 is a schematic diagram of the chip I/O interface. That is, the chip can realize signal transmission with the interface through the chip I/O and the PCB. The chip I/O Interface may be a receiver of the chip I/O output signals, for example, the chip I/O Interface may be a System Power Management Interface (SPMI), and in some embodiments, the type of the chip I/O PAD may be defined in terms of the type of the chip I/O Interface, e.g., an I/O PAD connected to a SPMI may be referred to as a SPMI PAD.
The output impedance of the pad driver may be a resistance value measured at the driver output terminal, and in some embodiments, the output impedance of the pad driver may be an output impedance of a pad connected to the pad driver. The pad driver may be a PCL driver, such that the PCL controls the output impedance of the pad through the PCL driver.
The driving capability of the chip can be understood as the capability of the chip to drive a load, in the chip I/O circuit, the driving strength of the pad driver is linearly related to the output impedance of the pad driver, in some cases, the smaller the output impedance of the pad driver is, the larger the output current of the chip I/O circuit is, the stronger the pad driver is, in other cases, the larger the output impedance of the pad driver is, the larger the output voltage of the chip I/O circuit is, the stronger the pad driver is.
The appropriate driving strength needs to be designed for the I/O pad driver at the chip design stage, so that the output impedance of the pad driver is matched with the PCB wiring impedance under the driving strength, the performance requirement of signals is met, and the problems of signal reflection, signal distortion and the like caused by impedance mismatching are avoided. The Signal property may be, for example, Signal Integrity (SI).
The designed chip can be produced and manufactured by a chip manufacturer, and the chip manufacturing process can comprise the steps of wafer manufacturing, chip packaging, chip testing and the like.
When a chip is manufactured in a factory, the performance of the chip is somewhat deviated due to influences of a processing process, a processing environment, material characteristics, and the like. The process parameters of the chip, such as the resistance of the chip, the voltage of the chip, the current of the chip, and the process parameters during the manufacturing process, such as the manufacturing temperature, can be used to indicate the process of the chip. The process of the chip may include a process corner of the chip, and the process corner of the chip may be, for example, a 3 process corner model, and may also be, for example, a 5 process corner model, and it should be understood that the number of process corners of the process corner model is not limited in this application. In the 3-process corner model, the chip can be classified into three types, TT, SS, FF. The TT angle chip can be used for indicating a typical process angle of an N-type field effect transistor and a typical process angle of a P-type field effect transistor; the SS corner chip can be used to indicate the N-type field effect transistor and the P-type field effect transistor slow process corners; the FF corner chip may be used to indicate the N-type and P-type field effect transistor fast process corners. In some embodiments, the fast and slow rates of carrier mobility in transistors in chips of different process corners are different, e.g., faster carrier mobility in transistors in FF chips.
Before the chip leaves a factory, the parameters of the chip can be measured by a testing method, and test data can be written into a memory of the chip, wherein the test data can be used for indicating different chip processes. As an example, the chip is tested at an Automatic test station (ATE) in a chip manufacturing plant, and the test parameter may be, for example, a voltage value of the chip operating circuit, for example, a frequency value of the chip operating circuit, for example, a resistance value of the chip. And carrying out data processing on the test value to obtain the numerical deviation of the test value and the reference value, and indicating different chip processes according to the numerical deviation. The reference value may be a design standard value or an average value of the test data.
As an example, the deviation of the chip resistance value from the design value is obtained for the resistance value of the test chip in the factory, and different chip processes can be determined according to the deviation value of the resistance value. The chip with the test resistance value consistent with the designed resistance value can be a normal chip, and the normal chip can be a TT process corner chip; the chip with the test value higher than the upper limit can be an SS process corner chip; the chip with the lower limit of the test value can be an FF process corner chip. The test data may be stored in a fuse module (IC fuse) of the chip, and the required test data may be acquired by reading data from the fuse module of the chip. In some embodiments, the IC fuse also stores chip ID, date of manufacture, process parameters, and other related data.
As mentioned above, the driving strength of the chip pad driver is linear to the output impedance of the driver, and the driving strengths of different driving capability chips are not consistent based on the same output impedance, for example, when the output impedance of the chip pad is 36.5, if the TT corner process chip is used, the driving strength of the pad driver of the chip can be designed to be 5, if the FF corner process chip is used, the driving capability of the FF corner process chip is strong, and therefore, the driving strength needs to be re-matched for the FF, for example, the driving strength of the FF corner process chip is configured to be 3, and at this driving strength, the driving strength of the FF corner process chip matches the output impedance value of 36.5.
In the existing chip design technology, the chip pad driver is matched with proper driving strength according to the output impedance of a chip I/O circuit, so that the output impedance of the chip pad driver is matched with the PCB wiring impedance under the driving strength. However, in the prior art, no consideration is given to the design stage, the driving strength of the chip pad driver cannot be adjusted according to the chip process due to the change of the chip process fluctuation to the driving strength of the chip, and the problem that the impedance mismatching caused by the process fluctuation affects the performance of chip signals exists.
As an example, in the chip design phase, design values are set for the driving strength of the I/O PAD driver. Under the design value of the driving strength, the output impedance of the pad driver is matched with the PCB wiring impedance, so that the performance of signals can be ensured. If the actually used chip is influenced by the process, the driving capability of the pad driver is weak, the actual output impedance is larger than the designed value of the output impedance under the same designed value of the driving strength, and the output circuit is too small, so that the signal is incomplete; if the chip used in practice is influenced by the process, the driving capability is strong, the driving capability is too strong under the same driving strength design value, the actual output impedance is smaller than the output impedance design value, the output current is too large, the power consumption is increased, and the signal degradation is caused.
Therefore, the method and the device for controlling the chip are provided, the driving strength of the pad driver is determined through the process of identifying the chip and according to the chip process, the output impedance of the pad driver is matched with the PCB wiring impedance, and the phenomenon that the performance of the chip is affected due to impedance mismatching caused by chip process fluctuation is avoided.
Fig. 3 is a flowchart illustrating a method for controlling a chip according to an embodiment of the present disclosure, where the method may be executed by a processor module, for example, a Central Processing Unit (CPU), and the processor module may be a processor inside the chip or a processor outside the chip, where the chip may be the aforementioned baseband chip.
In step S210, a first process parameter is read, where the first process parameter is used to indicate a process of a chip.
The first process parameter may be any process parameter of the chip, and the first process parameter may be used to indicate a process of the chip. The first process parameter may be read from the chip, for example, the first process parameter may be obtained from chip parameter data stored in the chip, the parameter data may be pre-stored in a memory of the chip, and in some embodiments, the first process parameter may be read from a fuse module in the chip.
The first process parameter may be, for example, a voltage of the chip circuit, for example, a current of the chip circuit, and for example, a chip resistance value. It should be understood that the application is not limited to the type of first process parameter.
In step S220, a first driving strength of a pad driver of the chip is determined according to the first process parameter.
In some embodiments, the process of the chip can be determined according to the first process parameter, the driving strength of the chip pad driver can be determined, and the matching design of the PCB trace impedance can be performed based on the driving strength. The pad driver driving strength design may be performed according to a comparison between the pad driving strength and the output impedance, which may be shown in table 1, for example.
As can be seen from table 1, the driving strength of the PAD driver can be divided into 8 steps according to the resistance value of the output impedance of the SPMI PAD, and each step of driving strength can correspond to the resistance value range of the output impedance of the PAD.
As a possible implementation manner, the chip pad output impedance is 55.0, the chip process may be determined according to the first process parameter, and if the chip process parameter indicates that the chip is a TT angle process chip, the driving strength of the chip pad driver may be designed to be 2; if the chip process parameters indicate that the chip is an FF corner process chip and the driving capability of the FF corner chip is strong, the driving strength of the FF corner chip can be designed to be 1; if the chip process parameters indicate that the chip is the TT angle process chip, the driving capability of the TT angle process chip is weak, and the driving strength of the TT angle process chip can be designed to be 3.
In step S230, the driving strength of the pad driver is configured to be a first driving strength, so that the output impedance of the pad driver is matched with the trace impedance of the circuit board carrying the chip.
In some embodiments, the driver driving strength of the pad may be configured by a processor, which may be, for example, a CPU within the chip, and may also be, for example, a processing module external to the chip. The processor may configure the driving strength of the pad driver by configuring bit (bits) of the pad driver, for example, the driving strength of the pad driver may be configured to 011 from 100.
In some embodiments, the processor may program a value of the first drive strength of the pad driver into a register of a port control circuit of the chip, e.g., may program the first drive strength into a PCL register. In this way, the processor can quickly read the first drive strength and perform the configuration of the drive strength.
Therefore, the method for controlling the chip provided by the embodiment of the application can identify the technology of the chip, adjust the driving strength of the pad driver according to the technology of the chip, and enable the output impedance of the pad driver to be matched with the PCB wiring impedance, so as to avoid the influence of the fluctuation of the technology of the chip on the transmission signal of the chip.
In some embodiments, a first driving strength of a pad driver of a chip may be determined according to a PCB trace impedance and a first process parameter. Therefore, the driving strength of the chip can be matched according to the preset PCB wiring impedance, the chip is adapted to different PCB hardware design schemes, the change of the PCB design is avoided, and the design process of the chip is accelerated. Continuing with the example of table 1, as an example, to match a PCB trace impedance of 36 ohms, if the first process parameter of the chip indicates that the chip is a TT-corner chip, the driving strength of the chip pad may be designed to be 5, where the output impedance of the pad driver is 36.5, and the output impedance of the pad driver is a value matching the PCB trace impedance. If the first process parameter of a chip indicates that the chip is an FF corner chip, the driving strength of the chip pad may be designed to be 3, at which the output impedance of the pad driver, which is a value matching the PCB trace impedance, is 35.4. It should be understood that the matching between the pad output impedance and the PCB trace impedance may be a perfect equal resistance value, or an unequal resistance value, within a certain difference range.
As a simple implementation manner, when the first driving strength of the chip bonding pad is determined according to the chip process parameter, the first driving strength of the chip bonding pad may be determined according to the chip process parameter and the second driving strength of the chip bonding pad, where the second driving strength of the bonding pad is determined according to the PCB trace impedance. In other words, in the hardware design stage, the second driving strength of the pad driver may be determined according to the PCB trace impedance, and then the first driving strength of the pad driver may be determined according to the chip process and the second driving strength of the chip pad, where the output impedance of the pad driver and the PCB trace impedance are matched under the first driving strength. In some embodiments, the first driving strength of the pad driver may be queried by pre-stored chip first process parameter, first driving strength and second driving strength relational mapping information, which may be, for example, a relational mapping table, such as the relational mapping table shown in table 2.
The mapping table shown in table 2 may include a chip process parameter table and a chip pad driving strength conversion table, where the driving strength conversion table includes the number of the target driver and the second driving strength of the target driver. The target drivers of 4 different second driving strengths are provided in the chip PAD driving strength conversion table because the driving strengths required for the PADs are different for the same type of PAD due to the difference of hardware design on the PCB. For example, when the same interface is close to the chip, the required chip driving strength is low, and when the same interface is far from the chip, the required chip driving strength is high.
The method for controlling the chip provided in the embodiment of the present application is described below with reference to table 2. As an example, the resistance parameter of the chip is read from the fuse module of the chip as 1600, and the process parameter of the chip is identified as 7 according to the process parameter table of table 2. The second driving strength 011 is read from the driving strength conversion table in table 2, that is, the second driving strength of the target driver No. 2 is read, and then the first driving strength 010 is read from the driving strength conversion table according to the chip process parameter identifier 7 and the second driving strength 011. Then, the drive strength of target driver No. 2 is configured from 011 to 010.
Fig. 3 is a schematic diagram of a method for controlling a chip according to an embodiment of the present disclosure, fig. 4 is a schematic diagram of a flow of a method for controlling a chip according to an embodiment of the present disclosure, and the method for controlling a chip according to an embodiment of the present disclosure is described below with reference to fig. 3 and fig. 4.
In step S410, a second driving strength of the pad driver is determined.
The second driving strength may be a target driving strength determined according to impedance of the PCB trace, and the target driving strength may be determined through hardware testing, hardware simulation, and PCB parameter feature extraction according to physical characteristics of the PCB trace. The physical characteristics of the PCB trace may include the type of interface connected to the chip pad and the wiring pattern on the PCB.
In step S420, the process parameters of the chip are read.
The process parameters of the chip can be read from the fuses inside the chip,
in step S430, in the pad driving strength conversion table, a first driving strength is determined according to a second driving strength of the pad driver and the chip process parameter.
The pad driving strength conversion table may be, for example, a relational mapping table shown in table 2, and in the relational mapping table shown in table 2, the actual driving strength of the chip pad driver is determined according to the process parameters of the chip and the target driving strength of the pad driver.
In some embodiments, the target driving strength may also be obtained from the hardware configuration information of the chip before performing this step. The Hardware configuration information may be, for example, a Pad Allocation Table (PAT), or may also be, for example, a Hardware ID (Hardware ID, HWID), or may also be, for example, a target driving strength read from a non-Volatile Memory (NVM), or may also be, for example, a target driving strength read from a chip fuse, a manner of reading the second driving strength is not limited in the present application, and in an actual application process, an appropriate reading manner may be selected according to needs.
In step S440, the driving strength of the pad driver is configured to a first driving strength.
Fig. 5 is a schematic diagram illustrating another method for controlling a chip according to an embodiment of the present disclosure, and as shown in fig. 5, during initialization of a chip pad driver, a driver of the pad driver, for example, a driver of a PCL driver, may read a default driving strength of the pad driver from a PAT table corresponding to an operation mode. In the CR1 PCB compensation portion, the target driving strength may be retrieved from the PCB HWID and HWID table, i.e., the target driving strength is determined according to the PCB hardware characteristics. In the CR2 chip process compensation part, a System Control Unit (SCU) can read the process parameters of the chip from the chip fuse and determine the final driving strength of the pad driver according to the process parameters of the chip and the target driving strength in the pad driving strength conversion table.
Therefore, the method for controlling the chip provided by the embodiment of the application can detect the process of the chip, can obtain the parameters of the chip from the fuse of the chip, indicate the process of the chip through different chip parameters, and adjust the driving strength of the pad driver according to the process of the chip, so that the output impedance of the chip is matched with the PCB wiring impedance. The good impedance matching can save the reliability and power consumption of the chip, simultaneously, the yield of the chip in a chip manufacturing factory is improved to the maximum extent, as many corner chips as possible can be configured into useful chips, and huge cost is saved.
Method embodiments of the present application are described in detail above with reference to fig. 1-5, and apparatus embodiments of the present application are described in detail below with reference to fig. 6. It is to be understood that the description of the method embodiments corresponds to the description of the apparatus embodiments, and therefore reference may be made to the preceding method embodiments for parts not described in detail.
Fig. 6 is a schematic structural diagram of an apparatus for controlling a chip according to an embodiment of the present application. The control device 600 shown in fig. 6 may include a memory 610 and a processor 620, where the memory 610 may be configured to store instructions and the processor 620 may be configured to execute the instructions to perform the following operations: reading a first process parameter from a chip, wherein the first process parameter is used for indicating the process of the chip; determining a first driving strength of a pad driver of the chip according to the first process parameter; and configuring the driving strength of the pad driver to the first driving strength so that the output impedance of the pad driver is matched with the wiring impedance of a circuit board bearing the chip.
Optionally, the determining a first driving strength of a pad driver of the chip according to the first process parameter includes: determining a first driving strength of the pad driver according to the first process parameter and a second driving strength of the pad driver, wherein the second driving strength is determined based on the trace impedance of the circuit board.
Optionally, determining the first driving strength of the pad driver according to the first process parameter and the second driving strength of the pad driver includes: and inquiring prestored mapping relation information according to the first process parameter and the second driving strength of the pad driver, and determining the first driving strength, wherein the mapping relation information comprises the mapping relation among the first process parameter, the first driving strength and the second driving strength.
Optionally, configuring the driving strength of the pad driver to the first driving strength includes: and programming the value of the first driving strength into a register of a port control circuit of the chip.
Optionally, the first process parameter is read from a fuse module of the chip.
Optionally, the first process parameter indicates a process corner of the first chip.
Optionally, the chip is a baseband chip.
In the above embodiments, all or part of the implementation may be realized by software, hardware, firmware or any other combination. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the application to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored on a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, from one website, computer, server, or data center to another website, computer, server, or data center via wire (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that incorporates one or more of the available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., Digital Video Disk (DVD)), or a semiconductor medium (e.g., Solid State Disk (SSD)), among others.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (14)
1. A method of controlling a chip, the method comprising:
reading a first process parameter from a chip, wherein the first process parameter is used for indicating the process of the chip;
determining a first driving strength of a pad driver of the chip according to the first process parameter;
configuring the driving strength of the pad driver to the first driving strength so that the output impedance of the pad driver is matched with the trace impedance of the circuit board carrying the chip.
2. The method of claim 1, wherein determining a first driving strength of a pad driver of the chip according to the first process parameter comprises:
determining a first driving strength of the pad driver according to the first process parameter and a second driving strength of the pad driver, wherein the second driving strength is determined based on the trace impedance of the circuit board.
3. The method of claim 2, wherein determining a first drive strength of the pad driver based on the first process parameter and a second drive strength of the pad driver comprises:
and determining the first driving strength by inquiring prestored mapping relation information according to the first process parameter and the second driving strength of the pad driver, wherein the mapping relation information comprises the mapping relation among the first process parameter, the first driving strength and the second driving strength.
4. The method of claim 1, wherein the configuring the drive strength of the pad driver to the first drive strength comprises:
and programming the value of the first driving strength into a register of a port control circuit of the chip.
5. The method of claim 1, wherein the first process parameter is read from a fuse module of the chip.
6. The method of claim 1, wherein the first process parameter indicates a process corner of the first chip.
7. The method of claim 1, wherein the chip is a baseband chip.
8. An apparatus for controlling a chip, the apparatus comprising:
a memory to store instructions;
a processor to execute the instructions to perform operations comprising:
reading a first process parameter from a chip, wherein the first process parameter is used for indicating the process of the chip;
determining a first driving strength of a pad driver of the chip according to the first process parameter;
configuring the driving strength of the pad driver to the first driving strength so that the output impedance of the pad driver is matched with the trace impedance of the circuit board carrying the chip.
9. The apparatus of claim 8, wherein determining a first driving strength of a pad driver of the chip according to the first process parameter comprises:
determining a first driving strength of the pad driver according to the first process parameter and a second driving strength of the pad driver, wherein the second driving strength is determined based on the trace impedance of the circuit board.
10. The apparatus of claim 9, wherein determining a first drive strength of the pad driver based on the first process parameter and a second drive strength of the pad driver comprises:
and determining the first driving strength by inquiring prestored mapping relation information according to the first process parameter and the second driving strength of the pad driver, wherein the mapping relation information comprises the mapping relation among the first process parameter, the first driving strength and the second driving strength.
11. The apparatus of claim 8, wherein the configuring the drive strength of the pad driver to the first drive strength comprises:
and programming the value of the first driving strength into a register of a port control circuit of the chip.
12. The apparatus of claim 8, wherein the first process parameter is read from a fuse module of the chip.
13. The apparatus of claim 8, wherein the first process parameter indicates a process corner of the first chip.
14. The apparatus of claim 8, wherein the chip is a baseband chip.
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| CN202210055651.5A CN114492286A (en) | 2022-01-18 | 2022-01-18 | Method and device for controlling chip |
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| CN202210055651.5A CN114492286A (en) | 2022-01-18 | 2022-01-18 | Method and device for controlling chip |
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| US20070152712A1 (en) * | 2005-12-30 | 2007-07-05 | Dongbu Electronics Co., Ltd. | I/O cell capable of finely controlling drive strength related application |
| CN101470770A (en) * | 2007-10-29 | 2009-07-01 | 技领半导体(上海)有限公司 | Interconnect layer of a modularly designed analog integrated circuit |
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