CN114490468B - Data writing method, medium and electronic equipment - Google Patents
Data writing method, medium and electronic equipment Download PDFInfo
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- CN114490468B CN114490468B CN202210137524.XA CN202210137524A CN114490468B CN 114490468 B CN114490468 B CN 114490468B CN 202210137524 A CN202210137524 A CN 202210137524A CN 114490468 B CN114490468 B CN 114490468B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
- G06F3/064—Management of blocks
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention provides a data writing method, a medium and electronic equipment. The data writing method comprises the following steps: acquiring a data packet, wherein the data packet comprises a control section and a data section, the control section comprises one or more control blocks, the data section comprises one or more data blocks, and each control block corresponds to one or more data blocks; and writing the control block in the data packet and the corresponding data block into target equipment through a first cycle by using a main cycle channel of DMA. The data writing method is beneficial to reducing the memory usage in the data writing process.
Description
Technical Field
The present invention relates to the field of data reading and writing, and in particular, to a data writing method, a medium, and an electronic device.
Background
A liquid crystal display (Liquid Crystal Display, LCD) is one of flat panel displays, and is commonly used for screen display of electronic devices such as televisions and computers. In recent years, liquid crystal displays have been widely used in the market because of their low power consumption, small size, low radiation, and the like. In the existing embedded video screen system, in order to realize the dynamic surface changing function, RGB data of all pixels need to be cached for each frame of picture, which causes memory overhead and increase of CPU operation pressure.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a data writing method, a medium and an electronic device for implementing data writing of devices such as LCD displays.
To achieve the above and other related objects, a first aspect of the present invention provides a data writing method, including: acquiring a data packet, wherein the data packet comprises a control section and a data section, the control section comprises one or more control blocks, the data section comprises one or more data blocks, and each control block corresponds to one or more data blocks; writing the control block in the data packet and the corresponding data block into target equipment through a first cycle by using a main cycle channel of DMA; wherein any one of the first cycles comprises: writing control parameters in a target control block into a first memory of target equipment by using a memory configuration channel of a DMA (direct memory access), and triggering a data writing channel of the DMA after each control parameter in the target control block is written, wherein the target control block is one control block in the data packet; responding to the triggering of the data writing channel, writing the data block corresponding to the target control block into a second memory of the target device by using the data writing channel, and triggering a block circulation channel of a DMA after the writing of each data block corresponding to the target control block is completed; and responding to the triggering of the block circulation channel, judging whether a first circulation termination condition is met by using the block circulation channel, if so, terminating the first circulation, otherwise, taking the next control block of the target control block as a new target control block, and executing the next circulation.
In an embodiment of the first aspect, writing control parameters in a target control block to a first memory of the target device using a memory configuration channel of a DMA includes: writing each of the control parameters in the target control block to the first memory by a second cycle; wherein any one of the second cycles comprises: acquiring a first destination address of a target control parameter by using the main circulation channel, wherein the target control parameter is one control parameter in the target control block, and the first destination address is positioned in the first memory; writing the target control parameter to its first destination address using the memory configuration channel; and if all the control parameters in the target control block are written into the first memory, terminating the second cycle, otherwise, taking the next control parameter of the target control parameters as a new target control parameter, and executing the next cycle.
In an embodiment of the first aspect, writing, by the data writing channel, a data block corresponding to the target control block into the second memory of the target device includes: acquiring a third cycle parameter, wherein the third cycle parameter comprises a source address and a second destination address of a target data block, the maximum cycle number of the third cycle and whether the target data block is a compressed data stream, the target data block is a data block corresponding to the target control block, and the second destination address is located in the second memory; writing the target data block to the second memory through the third cycle; wherein any one of the third cycles comprises: acquiring a data block corresponding to the source address from the data packet as a data block to be written; writing the data block to be written into the second destination address through the data writing channel; if the data block to be written is a compressed data stream, keeping the source address unchanged and updating the second destination address, otherwise, updating the source address and the second destination address; and if the current cycle number of the third cycle reaches the maximum cycle number of the third cycle, terminating the third cycle, otherwise, executing the next cycle.
In an embodiment of the first aspect, obtaining the cycle parameters of the third cycle includes: and acquiring the source address, the second destination address, the maximum cycle number of the third cycle and/or whether the target data block is a compressed data stream or not according to the control parameters in the target control block by utilizing the memory configuration channel.
In an embodiment of the first aspect, the data packet further includes a data segment length and a control segment length, and the data writing method further includes: and acquiring the starting address of the data segment and/or the control segment according to the length of the data segment and/or the length of the control segment.
In an embodiment of the first aspect, the data writing method further includes: and splitting the data packet when the length of the data packet is greater than the maximum processing length of the DMA.
In an embodiment of the first aspect, 1. The splitting the data packet into two or more sub-data packets, writing each control block and its corresponding data block in the data packet into a target device through a first cycle using a main cycle channel of a DMA includes: and writing the control block and the corresponding data block in each sub-data packet into the target equipment sequentially through two or more rounds of the first loops by using the main loop channel, wherein each round of the first loops corresponds to one sub-data packet.
In an embodiment of the first aspect, the target device is an LCD display.
A second aspect of the present invention provides a computer readable storage medium having stored thereon a computer program which when executed by a processor implements a data writing method according to any of the first aspects of the present invention.
A third aspect of the present invention provides an electronic apparatus comprising: a memory having a computer program stored thereon; and the processor is in communication connection with the memory and executes the data writing method according to any one of the first aspect of the invention when the computer program is called.
As described above, the data writing method according to one or more embodiments of the present invention has the following advantageous effects:
the data writing method realizes the data writing of the target equipment by using a main circulation channel, a memory configuration channel, a data writing channel and a block circulation channel of DMA (Direct Memory Access) and is beneficial to reducing the memory usage in the data writing process and reducing the operating pressure of a CPU (Central processing Unit) on the target equipment.
Drawings
FIG. 1A is a flow chart of a data writing method according to an embodiment of the invention.
FIG. 1B is a detailed flowchart of step S12 in an embodiment of the data writing method according to the present invention.
FIG. 2 is a flow chart showing a second cycle of the data writing method according to an embodiment of the invention.
FIG. 3A is a flow chart illustrating a method for writing a target data block according to an embodiment of the present invention.
FIG. 3B is a detailed flowchart of the data writing method according to an embodiment of the invention in step S32.
Fig. 4A is a schematic diagram of a data packet according to an embodiment of the data writing method of the present invention.
FIG. 4B is a flowchart illustrating a data writing method according to an embodiment of the invention.
Fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the invention.
Description of element reference numerals
500. Electronic equipment
510. Memory device
520. Processor and method for controlling the same
530. Display device
S11 to S12 steps
S121 to S123 steps
S31 to S32 steps
S321 to S323 steps
S401 to S414 steps
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.
It should be noted that the illustrations provided in the following embodiments merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the illustrations, not according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex. Moreover, relational terms such as "first," "second," and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
In an embodiment of the invention, a data writing method is provided. Specifically, referring to fig. 1A, a flowchart of the data writing method in this embodiment is shown. As shown in fig. 1A, the data writing method in the present embodiment includes the following steps S11 and S12.
Step S11, a data packet is obtained, wherein the data packet comprises a control section and a data section, the control section comprises one or more control blocks, the data section comprises one or more data blocks, and each control block corresponds to one or more data blocks. Specifically, for any one of the control blocks, the control block includes one or more control parameters, where the control parameters in the control block are used to specify a writing manner of the data block corresponding to the control block.
Step S12, the control block in the data packet and the corresponding data block are written into the target device through the first cycle by utilizing the main cycle channel of the DMA. The target device is, for example, an LCD display, but the present invention is not limited thereto.
Specifically, referring to fig. 1B, a flowchart of any one of the first cycles in the present embodiment is shown. As shown in fig. 1B, any one of the first cycles in the present embodiment includes the following steps S121 to S124.
Step S121, writing control parameters in a target control block into a first memory of the target device by using a memory configuration channel of the DMA, and triggering a data writing channel of the DMA after each control parameter in the target control block is written. The first memory includes, for example, a control register in the target device. The target control block is one of the control blocks in the data packet.
Alternatively, in the initialization phase of the first cycle, the target control block may be initialized to the first of the control blocks in the data packet, after which the target control block may be updated by step S123.
Step S122, in response to the triggering of the data writing channel, writing the data block corresponding to the target control block into the second memory of the target device by using the data writing channel, and triggering the block circulation channel of the DMA after the writing of each data block corresponding to the target control block is completed. The second memory includes, for example, a data register and/or a memory in the target device, but the invention is not limited thereto.
Step S123, in response to the triggering of the block circulation channel, determining whether a first circulation termination condition is satisfied by using the block circulation channel, if so, terminating the first circulation, otherwise, taking the next control block of the target control block in the data packet as a new target control block, and jumping to step S121 to execute the next circulation.
Alternatively, the maximum number of cycles of the first cycle may be configured in the initialization stage of the first cycle, for example, the maximum number of cycles of the first cycle may be configured as the number of the control blocks included in the data packet. The first cycle termination condition may be that the current cycle number of the first cycle is greater than or equal to the maximum cycle number of the first cycle, but the present invention is not limited thereto.
As can be seen from the above description, the data writing method according to the present embodiment automatically writes all or part of the data in the data packet into the target device through four DMA channels. The method is beneficial to reducing the memory usage in the data writing process and reducing the operating pressure of the CPU on the target equipment. In particular, when the target device is an LCD display, a reduction in memory usage and CPU operating pressure may ensure that the LCD display has a higher picture refresh rate.
In one embodiment of the present invention, writing control parameters in a target control block to a first memory of the target device using a memory configuration channel of a DMA includes: and writing each control parameter in the target control block into the first memory through a second cycle. Fig. 2 shows a flow chart of any one of the second cycles according to the present embodiment. As shown in fig. 2, any one of the second cycles described in the present embodiment includes the following steps S21 to S23.
Step S21, the main circulation channel is utilized to acquire a first destination address of a target control parameter. The target control parameter is one of the control parameters in the target control block. The first destination address is located in the first memory.
Optionally, the control parameter in each control block includes two parts, wherein a first part represents a target write address of the control parameter, i.e. the first destination address, and a second part represents a parameter value of the control parameter, i.e. a value to be written to the first destination address.
Alternatively, in the initialization phase of the second cycle, the target control parameter may be initialized to the first one of the control parameters in the target control block, after which the target control parameter may be updated by step S23.
Step S22, writing the target control parameter to the first destination address by using the memory configuration channel.
Step S23, if each control parameter in the target control block is written into the first memory, the second cycle is terminated, otherwise, the next control parameter of the target control parameter is taken as a new target control parameter, and step S21 is skipped to execute the next cycle.
Referring to fig. 3A, in an embodiment of the present invention, writing a data block corresponding to the target control block into a second memory of the target device by using the data writing channel includes:
s31, acquiring a third cycle parameter, wherein the third cycle parameter comprises a source address and a second destination address of a target data block, the maximum cycle number of the third cycle and whether the target data block is a compressed data stream, the target data block is a data block corresponding to the target control block, and the second destination address is located in the second memory. The maximum cycle number of the third cycle may be, for example, the number of the data blocks corresponding to the target control block.
S32, writing the target data block into the second memory through the third cycle.
Fig. 3B is a detailed flowchart of step S32 in the present embodiment. As shown in fig. 3B, step S32 in the present embodiment includes the following steps S321 to S323.
Step S321, obtaining a data block corresponding to the source address from the data packet as a data block to be written.
Step S322, if the data block to be written is a compressed data stream, the source address is kept unchanged and the second destination address is updated, otherwise, the source address and the second destination address are updated.
Specifically, when the data block to be written is a compressed data stream, the data block to be written needs to be written to a plurality of addresses in the second memory, and thus, the source address is maintained unchanged and only the second destination address is updated in step S322. When the data block to be written is a normal data stream, the data to be written only needs to be written into one address in the second memory, so that the source address and the second destination address are updated at the same time in step S322. The method for updating the source address is as follows: the source address is increased by an offset such that the source address corresponds to the next data block of the data block to be written. The method for updating the second destination address is, for example: and adding 1 to the second destination address.
Step S323, if the current cycle number of the third cycle reaches the maximum cycle number of the third cycle, terminating the third cycle, otherwise, jumping to step S321 to execute the next cycle.
Optionally, acquiring the cycle parameters of the third cycle includes: and acquiring the source address, the second destination address, the maximum cycle number of the third cycle and/or whether the target data block is a compressed data stream or not according to the control parameters in the target control block by utilizing the memory configuration channel.
In an embodiment of the present invention, the data packet further includes a data segment length and a control segment length. In this embodiment, the data writing method further includes: and acquiring the starting address of the data segment and/or the control segment according to the length of the data segment and/or the length of the control segment, wherein the starting address of the data segment and/or the control segment is used for initializing the first cycle, the second cycle and/or the third cycle.
In an embodiment of the present invention, the data writing method further includes: and splitting the data packet when the length of the data packet is greater than the maximum processing length of the DMA. The maximum processing length of the DMA may be obtained according to the maximum number of cycles of the first cycle and the amount of data that can be written in each cycle of the first cycle.
Optionally, when the data packet is split into two or more sub-data packets, writing each control block and its corresponding data block in the data packet into the target device through the first cycle by using the main cycle channel of the DMA includes: and writing the control blocks in the sub data packets and the corresponding data blocks into the target equipment through two or more rounds of the first circulation by using the main circulation channel. Wherein each round of the first cycle corresponds to one of the sub-packets, i.e. each round of the first cycle is used to write the control block in one of the sub-packets and its corresponding data block to the target device. Taking splitting the data packet into a sub-data packet a and a sub-data packet B as an example, firstly initializing a cycle parameter of the first cycle according to the sub-data packet a, and writing the control block in the sub-data packet a and the corresponding data block in the target device through a round of the first cycle by using the main cycle channel. And initializing the cycle parameters of the first cycle according to the sub-data packet B, and using the main cycle channel to pass through the control block in the sub-data packet B through another round of the first cycle. The cycle parameters of the first cycle are, for example, the maximum cycle number of the first cycle, the start addresses of the control block and the database in the data packet, and the like.
In one embodiment of the present invention, the data writing method is used for writing data packets into an LCD display. Referring to fig. 4A, the data packet in this embodiment includes: the control segment comprises N control blocks CB1, CB2, …, CBn and 1 end block N1, and the data segment comprises N data blocks D1, D2, … and Dn, wherein N is a positive integer. In this embodiment, each control block includes k+1 control parameters P0, P1, …, pk, where k is a positive integer. Each control parameter includes two parts, a parameter command and a parameter value, and the parameter command and the parameter value are, for example, two bytes in length. The first parameter in each control block is the block length ble of the control block, and the block length of the end block N1 is 0. In this embodiment, the data block in the data segment is data that is finally written into the LCD display, and the data may be an LCD control instruction or RGB data. When data is transmitted to the LCD display, each of the control blocks corresponds to a data stream transmission process, and each of the control blocks is used to control the amount of data transmitted in the corresponding data stream transmission process and whether or not to retransmit a data block after the data block is transmitted. And if the data block is transmitted, the next data block is not transmitted but the data block is repeatedly transmitted, and the data block is indicated to be a compressed data stream.
In this embodiment, the writing of the data packet is implemented by using four DMA channels, where the four DMA channels include a main circulation channel, a memory configuration channel, a data writing channel, and a block circulation channel. Referring to fig. 4B, in the present embodiment, the data writing method includes the following steps S401 to S414.
In step S401, a target data packet is acquired, and the structure of the target data packet is shown in fig. 4A, for example. The target data packet may be an original data packet obtained by the MCU, or may be any sub-data packet obtained by splitting the original data packet.
Step S402, initializing a cycle parameter according to the target data packet, where the cycle parameter includes a maximum cycle number of the first cycle, a start address of a control block in the target data packet, a start address of a data block in the target data packet, and a cycle number of the second cycle. In this embodiment, the maximum number of cycles of the first cycle may be the number of control blocks included in the target data packet, and the number of cycles of the second cycle may be the number of control parameters included in each control block.
Step S403, acquiring a first control block in the target data packet as a target control block.
Step S404, acquiring a first control parameter of the target control block as a target control parameter.
Step S405, acquiring a first destination address of the target control parameter by using a main loop channel of the DMA, and configuring the first destination address to a memory configuration channel of the DMA. The first destination address is located in a first memory of the LCD display, for example, a control register of the LCD display.
Step S406, writing the target control parameter to the first destination address by using the memory configuration channel.
Step S407, if each control parameter in the target control block has been written into the first memory, executing step S408, otherwise, taking the next control parameter of the target control parameter as a new target control parameter, and jumping to step S405.
In step S408, the first data block corresponding to the target control block is obtained as the data block to be written by using the memory configuration channel.
Step S409, initializing the third cycle parameter by using the memory configuration channel, and configuring the third cycle parameter to the DMA data writing channel. The cycle parameters of the third cycle include the source address and the second destination address of the data block to be written, the maximum cycle number of the third cycle, whether the data block to be written is a compressed data stream, and the like. The second destination address is located in a second memory of the LCD display, for example, a display register and/or a memory of the LCD display.
Step S410, writing the data to be written into the second destination address by using the data writing channel.
Step S411, if all the data blocks corresponding to the target control block are written, the process jumps to step S414, otherwise, step S412 is executed.
Step S412, if the data to be written is a compressed data stream, the source address is kept unchanged and the second destination address is updated, otherwise, the source address and the second destination address are updated.
Step S413, obtaining the data block corresponding to the source address as a new data block to be written, and jumping to step S410.
Step S414, determining whether each control block in the target data block is written into the target device by using the DMA block circulation channel, if yes, terminating the writing flow of the target data block, otherwise, taking the next control block of the target control block as a new target control block, and jumping to step S404.
As can be seen from the above description, any of the target data blocks can be written into the LCD display in the above steps S411 to S414. In particular, when the size of the original data block acquired by the MCU exceeds the maximum processing capability of the DMA, the original data block is split into a plurality of sub-data blocks, each of the sub-data blocks is sequentially used as the target data block, and all control blocks and data blocks in the original data block can be written into the LCD display by adopting the steps S411 to S414.
Based on the above description of the data writing method, the present invention also provides a computer-readable storage medium having a computer program stored thereon. The computer program, when executed by a processor, implements the data writing method described in one or more embodiments of the invention.
Based on the description of the data writing method, the invention further provides electronic equipment. In particular, referring to fig. 5, in an embodiment of the invention, an electronic device 500 includes a memory 510 and a processor 520. The memory 510 is configured to store a computer program, and the processor 520 is communicatively coupled to the memory 510 and configured to implement the data writing method described in one or more embodiments of the present invention when the computer program is invoked.
Optionally, the electronic device 500 may further comprise a display 530, the display 530 being communicatively connected to the memory 510 and the processor 520 for displaying the relevant GUI interaction interface for the data writing method.
The protection scope of the data writing method of the present invention is not limited to the execution sequence of the steps listed in the present embodiment, and all the schemes implemented by adding or removing steps and replacing steps according to the prior art made by the principles of the present invention are included in the protection scope of the present invention.
In summary, according to the data writing method in one or more embodiments of the present invention, the main circulation channel, the memory configuration channel, the data writing channel and the block circulation channel of the DMA are used to implement data writing to the target device, and this data writing method is beneficial to reducing the memory usage in the data writing process and reducing the operating pressure of the CPU to the target device.
In addition, in some embodiments, a data packet model supporting compression is provided, and the data packet model can effectively reduce the total data amount of a picture, and fully utilize the memory efficiency of the CPU. Meanwhile, for such a packet structure, the CPU can utilize a DMA direct memory read-write mechanism, thereby realizing fast writing of video data with minimal intervention.
Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (9)
1. A data writing method, characterized in that the data writing method comprises:
acquiring a data packet, wherein the data packet comprises a control section and a data section, the control section comprises one or more control blocks, the data section comprises one or more data blocks, and each control block corresponds to one or more data blocks;
writing the control block in the data packet and the corresponding data block into target equipment through a first cycle by using a main cycle channel of DMA;
wherein any one of the first cycles comprises:
writing control parameters in a target control block into a first memory of target equipment by using a memory configuration channel of a DMA (direct memory access), and triggering a data writing channel of the DMA after each control parameter in the target control block is written, wherein the target control block is one control block in the data packet;
responding to the triggering of the data writing channel, writing the data block corresponding to the target control block into a second memory of the target device by using the data writing channel, and triggering a block circulation channel of a DMA after the writing of each data block corresponding to the target control block is completed;
responding to the triggering of the block circulation channel, judging whether a first circulation termination condition is met by utilizing the block circulation channel, if so, terminating the first circulation, otherwise, taking the next control block of the target control block as a new target control block, and executing the next circulation;
writing control parameters in a target control block to a first memory of the target device using a memory configuration channel of a DMA includes:
writing each of the control parameters in the target control block to the first memory by a second cycle;
wherein any one of the second cycles comprises:
acquiring a first destination address of a target control parameter by using the main circulation channel, wherein the target control parameter is one control parameter in the target control block, and the first destination address is positioned in the first memory;
writing the target control parameter to its first destination address using the memory configuration channel;
and if all the control parameters in the target control block are written into the first memory, terminating the second cycle, otherwise, taking the next control parameter of the target control parameters as a new target control parameter, and executing the next cycle.
2. The data writing method according to claim 1, wherein writing the data block corresponding to the target control block to the second memory of the target device using the data writing channel comprises:
acquiring a third cycle parameter, wherein the third cycle parameter comprises a source address and a second destination address of a target data block, the maximum cycle number of the third cycle and whether the target data block is a compressed data stream, the target data block is a data block corresponding to the target control block, and the second destination address is located in the second memory;
writing the target data block to the second memory through the third cycle;
wherein any one of the third cycles comprises:
acquiring a data block corresponding to the source address from the data packet as a data block to be written;
writing the data block to be written into the second destination address through the data writing channel;
if the data block to be written is a compressed data stream, keeping the source address unchanged and updating the second destination address, otherwise, updating the source address and the second destination address;
and if the current cycle number of the third cycle reaches the maximum cycle number of the third cycle, terminating the third cycle, otherwise, executing the next cycle.
3. The data writing method according to claim 2, wherein acquiring the cycle parameters of the third cycle comprises: and acquiring the source address, the second destination address, the maximum cycle number of the third cycle and/or whether the target data block is a compressed data stream or not according to the control parameters in the target control block by utilizing the memory configuration channel.
4. The data writing method of claim 1, wherein the data packet further comprises a data segment length and a control segment length, the data writing method further comprising: and acquiring the starting address of the data segment and/or the control segment according to the length of the data segment and/or the length of the control segment.
5. The data writing method according to claim 1, characterized in that the data writing method further comprises: and splitting the data packet when the length of the data packet is greater than the maximum processing length of the DMA.
6. The method according to claim 5, wherein the data packet is split into two or more sub-packets, and writing each control block and its corresponding data block in the data packet to a target device through a first cycle by using a main cycle channel of a DMA includes:
and writing the control block and the corresponding data block in each sub-data packet into the target equipment sequentially through two or more rounds of the first loops by using the main loop channel, wherein each round of the first loops corresponds to one sub-data packet.
7. The data writing method according to any one of claims 1 to 6, wherein: the target device is an LCD display.
8. A computer-readable storage medium having stored thereon a computer program, characterized by: the computer program, when executed by a processor, implements the data writing method of any of claims 1-7.
9. An electronic device, the electronic device comprising:
a memory storing a computer program;
a processor in communication with the memory, which when invoked performs the data writing method of any of claims 1-7.
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| CN109815176A (en) * | 2019-01-14 | 2019-05-28 | 中国科学院上海高等研究院 | Specific DMA data sending method, method of reseptance, system and medium |
| CN112040601A (en) * | 2020-09-03 | 2020-12-04 | 广州彩熠灯光股份有限公司 | Lamp dot matrix control device and method and LED stage lamp |
| CN113986533A (en) * | 2021-10-15 | 2022-01-28 | 山东云海国创云计算装备产业创新中心有限公司 | Data transmission method, DMA controller and computer readable storage medium |
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| US8595413B2 (en) * | 2008-02-20 | 2013-11-26 | Sony Corporation | Memory control method and device, memory access control method, computer program, and recording medium |
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| CN112040601A (en) * | 2020-09-03 | 2020-12-04 | 广州彩熠灯光股份有限公司 | Lamp dot matrix control device and method and LED stage lamp |
| CN113986533A (en) * | 2021-10-15 | 2022-01-28 | 山东云海国创云计算装备产业创新中心有限公司 | Data transmission method, DMA controller and computer readable storage medium |
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