CN114489493B

CN114489493B - Implementation method for simulating use of high-capacity Flash storage by Mifare class card

Info

Publication number: CN114489493B
Application number: CN202210016410.XA
Authority: CN
Inventors: 何军; 王亮; 颜昕明; 董文强
Original assignee: Guangzhou Wise Security Technology Co Ltd
Current assignee: Guangzhou Wise Security Technology Co Ltd
Priority date: 2022-01-07
Filing date: 2022-01-07
Publication date: 2023-08-15
Anticipated expiration: 2042-01-07
Also published as: CN114489493A

Abstract

The invention provides a method for realizing the simulation of a Mifare class card to use a large-capacity Flash memory, wherein the Mifare1K card memory has 16 x 4 = 64 blocks and 64 x 16 = 1024B; when the method is suitable, a target Flash Page is erased to write new data next time, two 1K Flash spaces are used, data information is alternately written in a unit of a Flash Page, each Flash writing operation command of the Mifare1K card is written in a Flash Page in advance according to the data quantity of 16B+4B, power failure is prevented, and data loss is avoided. The advantages are that: the storage requirement and the performance requirement of the Mifare class card are realized on the large-capacity Flash, flash hardware of an EEPROM or a small-capacity small page is not required to be additionally added on the SIM card, and the factory cost of the SIM card simulation application is greatly reduced.

Description

Implementation method for simulating use of high-capacity Flash storage by Mifare class card

Technical Field

The invention relates to the technical field of storage application of SWP-SIM cards, in particular to a method for realizing simulation of using a large-capacity Flash storage by an NFC-SWP-SIM card based on a SWP-HCI protocol stack Mifare class card.

Background

In order to realize NFC access to a mobile phone, the technical scheme adopted at present is that a CLF (Contactless Frontend, non-contact front end) is embedded inside the mobile phone, and based on the SWP standard of ETSI (european telecommunications standards institute), an NFC-SIM chip is adopted to integrate a SWP controller on a SIM card. The NFC-SIM chip comprises a system control module, a SWP interface module, an SCI7816 serial interface module, a reset signal generation module and a wake-up signal generation circuit, wherein the system control module, the SWP interface module, the SCI7816 serial interface module, the reset signal generation module and the wake-up signal generation circuit are provided with 8 pins, the pin definition accords with the integrated circuit card specification of ISO7816 with contacts, and the contact interface definition in the SIM card is C1 (working voltage VCC), C2 (reset RST), C3 (clock CLK), C5 (ground GND), C6 (programmable voltage), C7 (SCI 7816 serial interface module input and output) and C4/C8 (IC-USB high-speed interface).

The NFC-SIM chip is connected with SWIO of the CLF by taking C6 as SWIO (Single Wire Protocol Input/Output, SWP input/Output), is connected with working voltage VCC of the CLF through C1 and is connected with ground of the CLF through C5, the system control module simultaneously supports an SWP protocol stack and an ISO7816 protocol stack, and communication between the CLF and one end of the mobile phone is an SCI7816 interface of the SIM card. The SWP interface module realizes communication control according to an SWP-HCI protocol stack of the ETSI102613/622, and realizes single-wire data interaction with the external plug-in non-contact front end through the SWIO contact; and the bus communication interface module is used for communication control of the SWP interface module and an external bus of the near field communication terminal equipment, and data interaction of the SWP controller and a main controller of the near field communication terminal equipment is realized.

The structure of the SWP-HCI protocol stack is specifically seen in fig. 1. The SWP belongs to a lower layer in a protocol stack, realizes connection of a physical layer and a data link layer, transmits information through current-voltage variation of an SWP interface, and realizes functions of data link establishment, data transmission, flow control management, error detection, data retransmission after errors and the like. The HCI protocol is a host control interface protocol, which is a protocol applied to the upper layer of SWP protocol, and in the protocol stack, is a protocol of the upper and lower layers of SWP. The HCI protocol has three layers: the HCP routing layer, the HCP message layer and the instruction interaction (application layer) between gates are responsible for establishing logical addresses and pipelines and ports, and do not pay attention to the physical connection characteristics of the bottom layer.

NFC (Near Field Communication ) is a short-range contactless wireless communication technology based on RFID (radio frequency identification), proposed by NXP corporation and sony corporation, and works in the 13.56MHZ band, so that two NFC-compatible devices can communicate intuitively, conveniently and safely. The NFC is mainly applied to mobile micropayment and can also be applied to the fields of access control, public transportation and the like.

The technical standard adopted by the China Mobile and packet (NFC) service is mainly an NFC-SWP scheme which accords with the international standard: the NFC mobile phone and the NFC-SIM card are realized in a mode of machine card cooperation, a security chip for bearing the application is packaged in the NFC-SIM card, and a 13.56M radio frequency chip is integrated in the NFC mobile phone. Completely compatible with GP standard, dividing SIM card space into several security domains, each security domain having firewall for partition; each security domain is a logically independent region. By downloading the card application, personalization is completed, and non-contact transaction is realized; the mobile wallet client management is incorporated uniformly by downloading the application client; by updating Access Control (AC) rules, the client is enabled to access the card application.

For a 13.56M radio frequency chip, the short-distance standard (< 10 cm) and the products comprise ISO 14443 Type A, 14443 Type B and Felica, and the application scenes are similar, so that the radio frequency chip can be applied to the fields of buses, banks and enterprise all-purpose cards; ISO 14443 Type A is the most widely applied non-contact technology in China and is widely applied to public transportation, banks and business all-purpose card scenes. ISO 14443 Type B is used in public buses and banking systems in europe and the united states, and only few applications such as identity cards exist in China.

A typical card emulation composition includes two parts of hardware, namely a CLF and UICC. The CLF is a non-contact front end, one end of the CLF controls the antenna to exchange data with the card reader, and the other end of the CLF communicates with the UICC through the SWP interface. And the UICC internally installs the Mifare card simulation application to complete the card simulation of Mifare in cooperation with the CLF. The structure of the Mifare analog card module is shown in FIG. 2; it can be seen in connection with fig. 2 that the communication process inside the Mifare analog card is:

1. the CLF communicates with the UICC via SWP, which is a full duplex single bus communication interface that complies with the ETSI TS 102613 specification.

2. After the CLF enters the magnetic field of the card reader, the CLF is matched with the card reader to complete the anti-collision and card selection. The process is mainly completed by the card reader and the CLF.

3. After the CLF detects the magnetic field entering the card reader, communication with the UICC is started, and the main steps of communication are as follows: activating an SWP interface; establishing an SHDLC session of the SWP interface; session initialization of the SWP interface; mifare application data interactions.

Referring to FIG. 3, the NXP company Mifare1K MF1S50yX/V1 chip uses a 1KB EEPROM for storage of Mifare data. A NXP MIFARE Classic EV1 1K instruction flow diagram is shown in fig. 4. From fig. 4 it can be seen that the Mifare class card application is time-critical for the implementation of the respective instructions (WriteBlock 5.5ms, transfer 4.5 ms).

There are two schemes for realizing time limit requirements for the storage of the Mifare class card known at present, one is to use EEPROM, and the other is to use Flash with small capacity and small pages. However, both of these would add additional cost to the chip. On the storage of the Mifare class card, compared with Flash with large capacity: under the same capacity, EEPROM is used, so that the cost is high and the EEPROM is more reliable; the Flash with small capacity and small page is used, the cost is low, and the Flash is unreliable. Both schemes are hardware modules specially added for the Mifare class card application, that is, the factory cost of the SIM card is increased.

Disclosure of Invention

The invention aims to provide a method for realizing the simulation of using a large-capacity Flash storage by a Mifare class card, thereby solving the problems in the prior art.

In order to achieve the above purpose, the technical scheme adopted by the invention is as follows:

the implementation method for simulating and using the large-capacity Flash memory by the Mifare class card comprises the steps of storing 16×4=64 blocks and 64×16=1024B in Mifare1K card; when the method is suitable, a target Flash Page is erased to write new data next time, two 1K Flash spaces are used, data information is alternately written in a unit of a Flash Page, each Flash writing operation command of the Mifare1K card is written in a Flash Page according to the data quantity of 16B+4B first, power failure is prevented, and the data is prevented from being lost; a total of 7 Flash pages were used for the Mifare1K application, 7 Flash pages respectively,

Mifare 1K Space Application 0x89000//Page1

Mifare 1K Space Application 0x89200//Page2

Mifare 1K Space Application 0x89400//Page3

Mifare 1K Space Application 0x89600//Page4

Flash Page Version Ctrl PAD0 0x89800//Page5

Mifare Cmd Wrt PAD1 0x89A00//Page6

Mifare Cmd Wrt PAD2 0x89C00//Page7

the implementation method specifically comprises the following steps,

s1, powering on, selecting the latest Flash Block Page from the Flash of Page1, page2, page3 or Page4 according to Page5, copying Mifare Data into a memory mirror Mi_Mem, checking the Flash Page of Page6 and Page7, writing the latest Data into Mi_Mem, and reconstructing the latest Mifare Flash 1K Data content in the memory mirror Mi_Mem;

the first field in the Page5 records the Flash Page in which the latest Mifare Flash write command operation is located in the Mifare1K space, the front 512B space; the second field records the Flash page where the latest Mifare Flash write command is operated in the Mifare1K space and the back 512B space;

page6 is used for storing data in the Flash Page in the Mifare Flash write command operation in the front 512B space;

page7 is used for storing data in the Flash Page first by Mifare Flash write command operation in the rear 512B space;

s2, writing the write data 16B in the business process into a memory mirror image Mi_Mem at the first time, and then writing 16B+4B in Mi_Mem into Page6 or Page7;4B is the Block Addr information of the Mifare instruction, and after the power is turned off, the power is turned on to position and generate a Block X;

s3, when the Mifare Write is detected to be full of Page6 or Page7 at the Part2 time point of Dec/Inc+value or the Part1 time point of the Write Block instruction, ack is returned to the SWP main, namely the CLF end, and then a 512B data Flash Page is selected for early erasure according to Page5, the name PageC is temporarily set, and WritePage=1 is set;

s4, writing 16B+4B into the Page6 or Page7 when the Mifare Write receives data at the Transfer instruction or at the Part2 time point of the Write Block instruction; if WritePage=1, writing front or back 512B of Mi_Mem into PageC, updating Page5 version control information, and finally returning Ack to SWP master, namely CLF end; after the writing is successful, the Flash Page Erase of Page6 or Page7 returns to the step S2;

s5, if power failure occurs in the process, returning to the step S1;

part1 is Mifare Write Part, and the specific process is that a Mifare card in a SIM card simulates firmware to check Addr, when a target Flash Page needs to be erased, the Flash Page comprises a 1K version control Page5, a configuration register, an Erase of the Flash Page is started, and then the firmware continues to process and return to ACk; page Erase works at the end of Part 1;

part2 is Mifare Write Part, and the specific process is that the received 16B data is processed, then written to a target Flash Page by using a CPU, and then the firmware continues to process the work of returning ACk; the target Flash Page is Page6 or Page7 or one of Page1-4, if one of Page1-4, version control information of 4B needs to be written into Page5; if Page6 or Page7 or Flash Page is full, page Erase works at the end of Part 2;

the process carries out parallelization processing on the erasing of the Flash Page and the Part1 stage of the Mifare Write instruction, prejudges the storage state of the Flash Page, and carries out the operation of erasing the Page in the Part1 stage of the instruction under the state that Page1/2/3/4/5 is full, thereby shortening the time of card simulation for storing data in the Flash; writing 16B+4B byte data into Page6/7 in the stage of Part2 of the instruction, and writing 512B in the memory mirror Mi_Mem into a certain Flash Page of Page1/3 or Page2/4 if Page6/7 is in a full state; returning to Ack, if Page6/7 is full, then Erasing Page6/7 is started.

Preferably, the program in Flash is moved to IRAM to run, so as to improve the execution speed of the program; after the SIM card chip is reset, in order to improve the simulation application performance of the Mifare class card, a Remap remapping function is needed to be used: firstly, using DMA operation to move a program to be accelerated into an IRAM instruction memory, configuring the length, the starting address and the destination address of the Remap by using software, and starting a remapping function to realize program acceleration; IRAM is 16KB, supporting a maximum remapping length of 16KB.

Preferably, SWP ISR and Mifare Cmd processing analysis firmware run in IRAM instruction space through Remap, mifare data received from SWP interface are stored in DRAM data memory space; the Mifare data alternately writes and stores data by using two 1K spaces, when the power is on each time, the latest Flash content is selected from the Mifare data and is written into the memory mirror image, the received data is firstly stored into the memory, and then the received data is written into the corresponding Flash page when the data is needed.

Preferably, after a user selects a Mifare1K Card App through a SWP_HCI Card management module in an NFC protocol stack, initializing a Mifare1K Card application storage function, establishing Mifare Flash 1K data in a memory mirror image Mi_Mem, using the data of the memory mirror image Mi_Mem for subsequent firmware operation, and returning corresponding data in the Mifare Read instruction; the process of initializing the Mifare1K card application memory function is as follows:

s11, reading the latest version control word from the Page5 in a word mode to obtain a latest Page index I of the front 512B and a latest Page index J of the rear 512B; page5 write pointer assignment;

s12, positioning the position according to the index I and the index J, and respectively copying Mifare Flash 1K data content to the corresponding position in the memory mirror Mi_Mem by the front 512B data and the rear 512B data in the Flash Page;

s13, reading the latest data of the Block of the front 512B of the 1K space from the Page6, and copying the latest data into a memory mirror Mi_Mem; page6 write pointer assignment;

s14, reading the latest data of the Block of the 1K space 512B from the Page7, and copying the latest data into a memory mirror Mi_Mem; page7 write pointer assignment.

Preferably, the flow of the Write Block command processing specifically includes the following steps:

a1, judging whether the Write Block is in the range of the front 512B according to the Addr, and if so, executing A2-A7 sequentially; if not, sequentially executing the steps A8-A13;

a2, when the Page6 write pointer is one item worse than the Page6 write pointer, detecting that if the Page5 write pointer is one item worse than the Page, erasing the Page5, writing version information, and assigning values to the Page5 write pointer; starting Ack encryption;

a3, when the Page6 write pointer is full of one Page, selecting a Page to be erased from the Page1 or the Page3, and assigning the Page to Eraseflash_Adr and Wrtflash_1K_Adr1;

a4, detecting that the Ack encryption is completed, and returning to an Ack state; at this point, the Part1 flow of the Mifare Write instruction has been completed; if the EraseF_Adr is nonzero, the configuration register erases a Flash Page where the EraseF_Adr is positioned, and the EraseF_Adr is cleared;

a5, receiving 16B data by Part2 of the Mifare Write instruction, and starting decryption 16B; the Page6 write pointer adds an item, waits for the completion of decrypting the 16B Data, writes the 16B Data into a Block corresponding to the memory mirror Mi_Mem, and starts Ack encryption; writing addr+Data co-4B+16B Data into Page 6;

a6, when WrtFlash_1K_Adr1 is non-zero, writing the front 512B of the memory mirror image Mi_Mem into Flash Page1 or Page 3; updating the Page control information of 512B before Flash, and clearing WrtFlash_1K_Adr1; page6 is assigned to Eraseflash_Adr; writing the Page control information of the front 512B into the Page5 so as to obtain the latest data of the front 512B by powering up;

a7, detecting that the Ack encryption is completed, and returning to an Ack state; at this point, the Part2 flow of the Mifare Write instruction has been completed; if the EraseF_Adr is nonzero, the Flash Page where the EraseF_Adr is positioned is erased by the configuration register, and then the EraseF_Adr is cleared;

a8, when the Page7 write pointer is one item worse than the Page7 write pointer, detecting that if the Page5 write pointer is one item worse than the Page, erasing the Page5, writing version information, and assigning values to the Page5 write pointer; starting Ack encryption;

a9, when the Page7 write pointer is full of one Page, selecting a Page to be erased from the Page2 or the Page4, and assigning the Page to Eraseflash_Adr and Wrtflash_1K_Adr1;

a10, detecting that the Ack encryption is completed, and returning to an Ack state; at this point, the Part1 flow of the Mifare Write instruction has been completed; if the EraseF_Adr is nonzero, the configuration register erases a Flash Page where the EraseF_Adr is positioned, and the EraseF_Adr is cleared;

part2 of the Mifare Write instruction receives the 16B data and starts decryption 16B; the Page7 write pointer is added with an item, the completion of decrypting the 16B Data is waited, the 16B Data is written into a Block corresponding to the memory mirror Mi_Mem, and Ack encryption is started; writing addr+Data co-4B+16B Data into Page7;

a12, when WrtFlash_1K_Adr1 is non-zero, writing the back 512B of the memory mirror Mi_Mem into Flash Page2 or Page 4; after updating Flash, 512B locates Page control information, wrtFlash_1K_Adr1 is cleared; page7 is assigned to Eraseflash_Adr; writing the Page control information of the back 512B into the Page5 so as to obtain the latest data of the back 512B after power-up;

a13, detecting that the Ack encryption is completed, and returning to an Ack state; at this point, the Part2 flow of the Mifare Write instruction has been completed; if the EraseF_Adr is nonzero, the configuration register erases the Flash Page where the EraseF_Adr is located, and then the EraseF_Adr is cleared.

The beneficial effects of the invention are as follows: the storage requirement and the performance requirement of the Mifare class card are realized on the large-capacity Flash, flash hardware of an EEPROM or a small-capacity small page is not required to be additionally added on the SIM card, and the factory cost of the SIM card simulation application is greatly reduced.

Drawings

FIG. 1 is a schematic diagram of the structure of a conventional SWP-HCI protocol stack;

FIG. 2 is a schematic diagram of a prior art Mifare analog card module;

FIG. 3 is a MIFARE Classic EV1 1K functional block diagram of the NXP company;

FIG. 4 is a MIFARE Classic EV1 1K instruction flow diagram of the NXP company;

FIG. 5 is a schematic diagram of an implementation method of the NFC-SWP-SIM card simulating the use of a large-capacity Flash storage based on a SWP-HCI protocol stack Mifare class card in an embodiment of the present invention;

FIG. 6 is a schematic diagram of a Mifare card module according to an embodiment of the invention;

FIG. 7 is a schematic diagram of Mifare Write Part1 in an embodiment of the invention;

fig. 8 is a schematic diagram of Mifare Write Part2 in an embodiment of the invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the detailed description is presented by way of example only and is not intended to limit the invention.

In this embodiment, the path module necessary for the SWP-HCI card simulation application is CLF, SWP, HCI, "Mifare CRYPTO1 algorithm encryption and decryption module". Therefore, the performance requirements for implementing the Mifare class card storage function on 512B (Page) Flash are high. The technical scheme of the invention is provided for simulating Mifare class card application on SWP-SIM. The invention mainly comprises the following main contents:

1. and the firmware and the ISR are put into a memory to run, so that the processing speed of the firmware is improved.

IRAM region: single port SRAM,16KB, instruction RAM, can be used for code remapping.

The flash has slower reading and writing speed; but the speed of the read RAM is up to CPU speed. Therefore, the program in Flash can be moved to IRAM to run so as to improve the execution speed of the program. After the SIM card chip is reset, in order to improve the simulation application performance of the Mifare class card, a Remap remapping function is needed to be used: the DMA operation is firstly used to move the program to be accelerated into the IRAM instruction memory, then software configures the length of Remap, the starting address and the destination address, and the remapping function is started, thus the program acceleration can be realized. Since IRAM is 16KB, the maximum remapping length is 16KB supported.

The Remap mechanism is to put the code which is critical and needs to be processed quickly into the memory to run. The Mifare class card simulates the communication data package encryption and decryption of the application and the code execution parallelization, carries out the erasing pre-judgment of Flash Page, and completes the process under the idle period time during the communication.

In SWP-HCI card simulation application, a Remap mechanism is used, so that the execution speed of program instructions is improved, meanwhile, the Flash is convenient to perform erasing operation on 512B Page of Flash in Ram faster, and Flash programming is supported in a word mode, namely the minimum programming unit is 4 bytes.

2. Flash storage content, memory mirroring and firmware using Mifare class card applications are mostly operated using the content of memory mirroring and written into Flash at necessary times.

SWP ISR and Mifare Cmd processing analysis firmware run in IRAM instruction memory space through Remap, mifare data received from SWP interface are stored in DRAM data memory space; the Mifare data alternately writes and stores data by using two 1K spaces, when the power is on each time, the latest Flash content is selected from the Mifare data and is written into the memory mirror image, the received data is firstly stored into the memory, and then the received data is written into the corresponding Flash page when the data is needed.

Through the content, encryption and decryption of Mifare data and parallelization processing of Flash control operation are realized, instruction processing time is shortened, and Mifare class card application performance is improved.

Referring to fig. 5, in this embodiment, the Mifare1K card stores 16×4=64 blocks, 64×16=1024B; erasing a Page of a target Flash Page in proper time so as to write new data next time, using two 1K Flash spaces, alternately writing data information by taking a Flash Page as a unit, writing each Flash operation command of the Mifare1K card into a Flash Page according to the data quantity of 16B+4B, preventing power failure and ensuring that the data is not lost; a total of 7 Flash pages were used for the Mifare1K application, 7 Flash pages respectively,

Mifare 1K Space Application 0x89000//Page1

Mifare 1K Space Application 0x89200//Page2

Mifare 1K Space Application 0x89400//Page3

Mifare 1K Space Application 0x89600//Page4

Flash Page Version Ctrl PAD0 0x89800//Page5

Mifare Cmd Wrt PAD1 0x89A00//Page6

Mifare Cmd Wrt PAD2 0x89C00//Page7

wherein: the first field in the Page5 records the Flash Page in which the latest Mifare Flash write command operation is located in the Mifare1K space, the front 512B space; the second field records the Flash page where the latest Mifare Flash write command is operated in the Mifare1K space and the back 512B space;

the erasures of these 7 pages do not overlap each other, and the longest time it takes about 4.3ms to update one Page in pages 1-4 when the firmware returns to the Ack to the CLF side.

The implementation method of the NFC-SWP-SIM card based on SWP-HCI protocol stack Mifare class card simulation using the large-capacity Flash storage comprises the following steps,

s5, if power failure occurs in the process, returning to the step S1.

As can be seen from the above flow, the data of each storage instruction is firstly stored in the memory mirror image mi_mem, and then stored in the Flash Page of the Wrt Pad1 or Wrt Pad2 according to Addr information (whether the Addr information falls on the front 512BFlash Page or the rear 512BFlash Page) of the instruction (the data is written in the Flash Page in a mode of 4-byte additional writing each time). When Flash pages of Wrt Pad1 or Wrt Pad2 are about to be fully written, a target Flash Page is selected to erase one Page in advance, and the next instruction is stored in advance. After receiving the data of the next storage instruction, writing the content of the memory mirror image into the selected Flash Page. In the invention, the erasing operation of the Flash Page and the operation of writing full Page data are respectively detached and put into two instructions for execution, thereby shortening the operation time of the Flash Page.

The Page programming of Flash uses a Page backup mechanism, namely alternate writing of pages, so that accidental power failure can be prevented, and the restorability and the correctness of data are ensured.

And reserving a Mifare class card memory area image in the SWP-SIM card memory, generating a Mifare class card data memory image according to the information reserved in the Flash control page during power-on initialization, using the Mifare class card memory image during card simulation operation, using data in the memory image in all Mifare read instructions, and writing the memory image data back into the Flash page at a key time point. The encryption and decryption processing of Mifare CRYPTO1 data and the operation of a CPU on Flash are parallelized processing operation modes, so that the encryption and decryption of a bit stream hardly consume time, the processing performance of Mifare class card simulation instructions is improved, and the time requirement of Mifare class technical manual on stored instructions can be well met.

See fig. 6 for a modular architecture for Mifare card simulation. After a user selects Mifare1K Card App1 through a SWP_HCI Card management module in an NFC protocol stack, initializing a Mifare1K Card application storage function, establishing Mifare Flash 1K data in a memory mirror Mi_Mem, using the data of the memory mirror Mi_Mem for subsequent firmware operation, and returning corresponding data in the Mifare Read instruction; the process of initializing the Mifare1K card application memory function is as follows:

Since the processing control logic of the Mifare Write instruction and the Mifare de-Increment, mifare Transfer instruction are substantially the same in the present invention, the Mifare Write instruction is taken as an example to illustrate the inventive design.

Mifare Write requires a block address to Write 16 bytes of data to address MIFARE Classic EV1 with 1K memory block; it requires two pairs of command responses, mifare Write Part and Mifare Write Part2, respectively.

Referring to the specific process of fig. 7,Mifare Write Part1, the Mifare card in the SIM card simulates firmware to check Addr, when a target Flash Page needs to be erased, including 1K version control Page5, configuring a register, starting the Erase of the Flash Page, and then continuing to process the firmware to return to the task of the ACk; page Erase works at the last do of part1 (i.e., the idle period after the Ack is returned last).

The specific process of fig. 8,Mifare Write Part2 is that the received 16B data is processed, then written to the target Flash Page by using the CPU, and then the firmware continues to process the work of returning to the ACk; the target Flash Page is Page6 or Page7 or one of Page1-4, if one of Page1-4, version control information of 4B needs to be written into Page5; if Page6 or Page7 or Flash Page is full, page Erase works at the last done of part2 (i.e. the idle period after the Ack is returned last).

Mifare Write command (command from Mifare Write) see the following table:

name of the name	Description of the invention	Length of
			Cmd	Writing a block (write one block)	1byte
Addr	MIFARE block or page address (MIFARE block or page address)	1byte
			CRC	Cyclic redundancy check	2bytes
Date	Data	16bytes
			NAK	Denial (Negative Acknowledge)	4bit
ACK	Confirmation (Acknowledges)	4bit

Mifare Write timing (Mifare Write time limit) see the following table:

	T _ACK min	T _ACK max	T _NAK min	T _NAK max	T _timeout
						Write Part1	n＝9	T _timeout	n＝9	T _timeout	5ms
Write Part2	n＝9	T _timeout	n＝9	T _timeout	10ms

the total time of WriteBlock can be completed within 5.5ms, which is within the time range required by the specification.

In this embodiment, the flow of the Write Block command processing specifically includes the following steps,

By adopting the technical scheme disclosed by the invention, the following beneficial effects are obtained:

the invention provides a method for realizing the simulation of the use of a large-capacity Flash storage by a Mifare class card, which realizes the storage requirement and the performance requirement of the Mifare class card on the large-capacity Flash without additionally adding EEPROM or Flash hardware of a small-capacity page on a SIM card, thereby greatly reducing the delivery cost of the simulation application of the SIM card.

The foregoing is merely a preferred embodiment of the present invention and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present invention, which is also intended to be covered by the present invention.

Claims

1. A method for realizing the simulation of using a large-capacity Flash storage by a Mifare class card is characterized by comprising the following steps: mifare1K card memory total 16×4=64 blocks, 64×16=1024B; when the method is suitable, a target Flash Page is erased to write new data next time, two 1K Flash spaces are used, data information is alternately written in a unit of a Flash Page, each Flash writing operation command of the Mifare1K card is written in a Flash Page according to the data quantity of 16B+4B first, power failure is prevented, and the data is prevented from being lost; a total of 7 Flash pages were used for the Mifare1K application, 7 Flash pages respectively,

Mifare 1K Space Application 0x89000//Page1

Mifare 1K Space Application 0x89200//Page2

Mifare 1K Space Application 0x89400//Page3

Mifare 1K Space Application 0x89600//Page4

Flash Page Version Ctrl PAD0 0x89800//Page5

Mifare Cmd Wrt PAD1 0x89A00//Page6

Mifare Cmd Wrt PAD2 0x89C00//Page7

the implementation method specifically comprises the following steps,

s5, if power failure occurs in the process, returning to the step S1;

2. The implementation method for simulating the use of the large-capacity Flash storage by the Mifare class card according to claim 1, wherein the implementation method is characterized in that: moving the program in Flash to IRAM to run so as to increase the execution speed of the program; after the SIM card chip is reset, in order to improve the simulation application performance of the Mifare class card, a Remap remapping function is needed to be used: firstly, using DMA operation to move a program to be accelerated into an IRAM instruction memory, configuring the length, the starting address and the destination address of the Remap by using software, and starting a remapping function to realize program acceleration; IRAM is 16KB, supporting a maximum remapping length of 16KB.

3. The implementation method for simulating the use of the large-capacity Flash storage by the Mifare class card according to claim 1, wherein the implementation method is characterized in that: SWP ISR and Mifare Cmd processing analysis firmware run in IRAM instruction space through Remap, mifare data received from SWP interface are stored in DRAM data memory space; the Mifare data alternately writes and stores data by using two 1K spaces, when the power is on each time, the latest Flash content is selected from the Mifare data and is written into the memory mirror image, the received data is firstly stored into the memory, and then the received data is written into the corresponding Flash page when the data is needed.

4. The implementation method for simulating the use of the large-capacity Flash storage by the Mifare class card according to claim 1, wherein the implementation method is characterized in that: after a user selects Mifare1K Card App through a SWP_HCI Card management module in an NFC protocol stack, initializing a Mifare1K Card application storage function, establishing Mifare Flash 1K data in a memory mirror image Mi_Mem, using the data of the memory mirror image Mi_Mem for subsequent firmware operation, and returning corresponding data in the Mifare Read instruction; the process of initializing the Mifare1K card application memory function is as follows:

5. The implementation method for simulating the use of the large-capacity Flash storage by the Mifare class card according to claim 1, wherein the implementation method is characterized in that: the process flow of the Write Block command processing specifically comprises the following steps: