CN114487531A - Digital correction and compensation circuit for oscilloscope - Google Patents

Abstract

The invention discloses a digital correction and compensation circuit for an oscilloscope, and belongs to the technical field of digital. The invention adopts a digital correction and compensation mode in the FPGA to replace the traditional analog device and software compensation and correction; the automatic calibration of the gain and the offset of the ADC of the data acquisition module can be realized, the calibration precision is high, the calibration speed is high, and the calibration accuracy and effectiveness are improved; amplitude compensation of the oscilloscope is realized in a digital mode, the bandwidth of the oscilloscope can be improved, the amplitude-frequency response optimization can be optimized, and the amplitude flatness can reach +/-1 dB; noise reduction and filtering can be realized in a digital mode, and six digital filtering gears of 20MHz, 250MHz, 500MHz, 1GHz, 1.5GHz, 2GHz and the like can be realized; waveform reconstruction is realized in a digital mode, the minimum time base of the oscilloscope can reach 5ps/div, and the maximum digital interpolation multiple is 2000 times; the invention can be expanded to be applied to oscilloscopes with higher bandwidth and higher sampling rate.

Description

Digital correction and compensation circuit for oscilloscope

Technical Field

The invention belongs to the technical field of numbers, and particularly relates to a digital correction and compensation circuit for an oscilloscope.

Background

In order to solve various errors generated by the limitation of hardware circuits of oscilloscopes, domestic oscilloscopes mainly realize a waveform reconstruction module in a CPU (central processing unit) end software mode, solve the problems that the number of sampling points is small and a display area cannot be filled due to insufficient sampling rate of a fast time base gear, adopt the CPU end software mode to realize a bandwidth and flatness optimization module, solve the problem of frequency response flatness of the oscilloscopes, adopt an analog noise reduction filtering module, and reduce the background noise of the oscilloscopes through a relay switch and an analog filter.

Aiming at the problem that a sampling point cannot fill a display area due to insufficient sampling rate of a fast time base gear, the prior art scheme is realized by adopting a mode of carrying out software interpolation on sampling data by CPU (central processing unit) end software. The oscilloscope stores the sampled original data in the memory, transmits the sampled data to the memory of the CPU under the control of the clock and the trigger signal, and the CPU calculates interpolation points through a software interpolation algorithm at the CPU end according to the screen display area and the number of the sampling points in the memory and then transmits the interpolation points to the screen for display.

Aiming at the problems that when the bandwidth limit of an oscilloscope is approached, the flatness of frequency response tends to deteriorate, the oscilloscope has amplitude attenuation on some frequency points and amplitude amplification on some frequency points, the prior art scheme adopts a mode of compensating sampling data by CPU end software. The oscilloscope stores the sampled original data in the memory, transmits the actual sampled data to the memory of the CPU under the control of the clock and the trigger signal, the CPU compares the data in the memory with the data output by the standard source, and calibrates the actual sampled data in the memory to the ideal value of the standard source in a compensation processing mode.

Aiming at the problem of large background noise of a broadband oscilloscope, when a signal with a low bandwidth or a signal with a relatively low edge rate is tested, the background noise is reduced by adopting a mode of combining a relay switch and analog filters with different bandwidths in the prior art, and the noise reduction technology of the prior analog filter generally has two gears of 20MHz and 200 MHz.

The existing correction circuit and method of the oscilloscope are mainly realized by adopting a mode of post-processing of an analog circuit and CPU (central processing unit) end software, and the existing technical scheme adopts more analog filters and relays for development, occupies larger circuit area, and has large power consumption and high cost; meanwhile, the adopted CPU end software post-processing mode needs that the sampling data of the oscilloscope is completely transmitted to the internal memory of the CPU end, and then the data can be compensated and corrected.

Disclosure of Invention

Aiming at the technical problems in the prior art, the invention provides the digital correction and compensation circuit for the oscilloscope, which has reasonable design, overcomes the defects of the prior art and has good effect.

In order to achieve the purpose, the invention adopts the following technical scheme:

a digital correction and compensation circuit for an oscilloscope comprises a calibration signal generation module, an analog front end conditioning module, a data acquisition module, a digital signal processing module and an embedded CPU module; wherein, the digital signal processing module is a core module;

the calibration signal generation module is configured to generate a fast edge and a sine signal required by oscilloscope calibration, the signal amplitude is 500mVpp, the fast edge signal frequency is fixed 1kHz, the sine wave frequency is 10 MHz-2.5 GHz, and the frequency adjustment step is 10 MHz;

the analog front-end conditioning module is configured to condition an input signal CH and a calibration signal for realizing an oscilloscope channel; the input frequency range of the analog front-end conditioning module is DC-2.5 GHz, the amplitude range is 4 mVpp-8 Vpp, the output frequency range is DC-2.5 GHz, and the amplitude range is 2.35 mV-600 mVpp;

the data acquisition module is configured to acquire a signal output by the analog front-end conditioning module;

a digital signal processing module configured to process the digital signal;

and the embedded CPU module is configured to communicate with a CPU interaction control unit interface of the digital signal processing module through a PCIe2.0 interface, so as to realize interaction and transmission of control commands and acquired data.

Preferably, the calibration signal generating module comprises a fast edge signal generating unit, a sinusoidal signal generating unit and a first switch selecting unit;

a fast edge signal generation unit configured to generate a fast edge signal required for gain and phase calibration of an ADC in the data acquisition module;

the sine signal generating unit is configured to generate 1/4 the maximum frequency of the sine wave signal required by the bandwidth and flatness optimizing unit in the digital signal processing module is the sampling rate of the ADC in the back-end data acquisition module;

a first switch selection unit configured to switch outputs of the fast edge signal and the sinusoidal signal, outputting a calibration signal JZ having an amplitude of 500 mVpp.

Preferably, the analog front-end conditioning module comprises a second switch selection unit, an attenuator unit and an amplifier unit;

the second switch selection unit is configured to select the oscilloscope channel input signal CH and the calibration signal ZJ generated by the calibration signal generation module; when the oscilloscope selects the calibration signal ZJ, the oscilloscope is in an automatic calibration mode, so that the self calibration of an ADC in the data acquisition module and the automatic generation of the coefficient of a correction filter in a bandwidth and flatness optimization unit in the digital signal processing module are realized, the ZJ signal comes from an internal calibration signal generation module of the oscilloscope, and the amplitude is 500 mVpp; when the oscilloscope selects the channel signal CH, the oscilloscope can realize normal measurement on the measured object, the amplitude of the CH signal is 4 mVpp-8 Vpp, and the signal frequency is the bandwidth of the oscilloscope, namely DC-2.5 GHz;

the attenuator unit is configured to attenuate the CH signal, if the amplitude of the input channel signal is 600 mVpp-8 Vpp, the input channel signal exceeds the full-scale range of the ADC in the data acquisition module, and the full-scale voltage of the ADC is 600mVpp, the attenuator module attenuates, and the attenuation multiple is CH/600 mV;

and the amplifier unit is configured to amplify the CH signal, and if the amplitude of the input channel signal is 4 mVpp-600 mVpp, the channel signal is lower than the full scale range of the ADC in the data acquisition module, and the full scale voltage of the ADC is 600mVpp, the amplifier unit amplifies the channel signal by the amplification factor of 600 mV/CH.

Preferably, the data acquisition module comprises a clock generation unit and an ADC unit;

a clock generation unit configured to generate a 5GHz clock to the ADC unit;

and the ADC unit is configured to convert the analog signal CH of the channel into a digital signal, and then send the digital signal to the digital signal processing unit at the back end for post-processing of data.

Preferably, the clock generation unit adopts a digital integrated phase-locked loop LMX2952 frequency synthesizer; the ADC unit adopts AAD08S010GA chip, which realizes the conversion of analog to digital signal with 10GSa/S sampling rate and 8bit vertical resolution, outputs 80Gbps data stream, and generates 2.5Gbps 32 low-speed data stream in the ADC for receiving by the back-end digital signal processing unit, when the ADC outputs, it adopts double-edge output mode, the output clock is 1.25GHz, the data stream bit is 32 bit wide D31: 0, and sends it to the back-end digital signal processing module.

Preferably, the digital signal processing module adopts an FPGA with the model number of XCKU060-2FFVA1517I, and comprises a data preprocessing unit, a bandwidth and frequency response optimizing unit, a noise reduction filtering unit, a data selector, a data storage control unit, a waveform reconstruction unit and a CPU interaction control unit;

a data preprocessing unit configured to process data;

the bandwidth and frequency response optimizing unit is configured to be used for improving the voltage characteristic of the waveform of the oscilloscope in the vertical direction, and a user can select to turn on or turn off the bandwidth and frequency response optimizing unit; when the switch-off is selected, the data preprocessing unit at the front end directly sends the 256-bit data stream DZ [255:0] of 312.5MHz to the back end for subsequent processing, and when the switch-on is selected, the data preprocessing unit at the front end directly sends the 256-bit data stream DZ [255:0] of 312.5MHz to the bandwidth and frequency response optimizing unit for processing;

the noise reduction filtering unit comprises a noise reduction filter coefficient RAM, a CIC decimation filter, an FIR filter and a CIC interpolation filter; the user can select to turn on or off the noise reduction filtering unit; when the selection is closed, the 256-bit data stream DZ [255:0] with the front end of 312.5MHz is directly sent to the back end for subsequent processing; when the selection is opened, the 256-bit data stream DZ [255:0] with the front end of 312.5MHz is sent to the noise reduction filter unit for processing; a user can select six-gear digital low-pass filters including 20MHz, 250MHz, 500MHz, 1GHz, 1.5GHz and 2GHz, and the six-gear digital filters are realized by adopting different CIC + FIR cascade combination and filter coefficient selection; when a user selects a larger bandwidth limit within the 1.5GHz or 2GHz pass band range, the oscilloscope performs delay processing on data according to CIC extraction, FIR filtering and CIC interpolation filter of a selected opening part so as to realize signal synchronization with a channel without opening the bandwidth limit; when a user selects a 20MHz or 250MHz lower pass band range, an oscilloscope starts a rear-end CIC extraction + FIR filtering + CIC interpolation cascade module, firstly extracts a sampling signal by a power of 2 to reduce the data stream rate to the acceptable working frequency of the FIR filter, the FIR filter performs multiply-add operation on an input signal and a preset filtering coefficient, and finally completes interpolation processing on the filtered signal by the interpolation CIC module to generate data with the same total bit width, namely 256-bit data stream DZ [255:0] of 312.5MHz passes through a noise reduction filtering unit and then outputs a new 256-bit data stream DJZ [255:0] of 312.5 MHz;

the waveform reconstruction unit is configured to improve the time characteristic of the oscilloscope waveform in the horizontal direction, and a user can select to turn on or turn off the waveform reconstruction unit; when the selection is closed, the noise reduction filtering unit at the front end directly stores the 256-bit data stream DJZ [255:0] of 312.5MHz into a RAM memory in the FPGA under the control of the data storage control unit; when the selection is opened, the noise reduction filtering unit at the front end directly sends the 256-bit data stream DJZ [255:0] of 312.5MHz to the waveform reconstruction unit for processing;

a data storage control unit configured to store the 256-bit data stream DCJ [255:0] of 312.5MHz output by the waveform reconstruction unit into a memory RAM inside the FPGA; the embedded CPU module sends the sampling data DCJ (255: 0) to a display screen for displaying through a CPU interface interaction control unit in the digital signal processing module;

a CPU interaction control unit configured for the embedded CPU module and the number.

Preferably, the data preprocessing unit comprises a data receiving unit, a speed reduction processing unit and a data recombining unit;

the data receiving unit is configured to be used for receiving the 1.25GHz double clock edges and the 32-bit data flow D [31:0] output by the data acquisition module, and converting the differential input signals into single-ended signals to be output, wherein the single-ended signals are converted into 64-bit data flow DY [63:0] of the 1.25GHz single clock edges;

the speed reduction processing unit is configured to convert the 64-bit data DY [63:0] of 1.25GHz into a 256-bit data DJ [255:0] of 312.5MHz with lower speed, and the clock requirement of FPGA internal data processing is met;

and the data recombination unit is configured to realize the recombination and arrangement of the 256-bit data stream DJ [255:0] of 312.5MHz, and the data recombination unit is arranged and recombined according to the sampling sequence of the sampling clock to form a new 256-bit data stream DZ [255:0] of 312.5 MHz.

Preferably, the bandwidth and frequency response optimizing unit comprises an amplitude correction filter coefficient RAM and an FIR filter unit;

the FIR filter unit comprises a multiplication and adder of MAC, a delayer and a lookup table; 256 bit data stream DZ [255:0] of 312.5MHz is multiplied by a correction coefficient in an amplitude correction filter coefficient RAM, added with the MAC of the previous stage and finally output to a lower-stage MAC structure, and then output corrected DYH [255:0] after multi-stage FIR filtering and then sent to the rear end for subsequent processing; the specific numerical value of the correction filter coefficient in the amplitude correction filter coefficient RAM is automatically generated by an amplitude correction filter coefficient calculation unit of the embedded CPU module.

Preferably, the waveform reconstruction unit comprises a waveform reconstruction filter coefficient RAM and an FIR interpolation filter unit;

the FIR interpolation filter unit comprises a multiplication and adder of MAC, a delayer and a lookup table; 256 bit data stream DJZ [255:0] of 312.5MHz is multiplied by a correction coefficient in a waveform reconstruction filter coefficient RAM, added with a previous-stage MAC and finally output to a lower-stage MAC structure, and DCJ [255:0] of waveform reconstruction is output after multi-stage FIR interpolation filtering and stored in an RAM memory in the FPGA under the control of a data storage control unit; the specific numerical value of the waveform reconstruction filter coefficient in the waveform reconstruction filter coefficient RAM is generated by a waveform reconstruction filter coefficient calculation unit of the embedded CPU module.

Preferably, the embedded CPU module includes an amplitude correction filter coefficient calculation unit, a noise reduction filter coefficient calculation unit, and a waveform reconstruction filter coefficient calculation unit;

the amplitude correction filter coefficient calculation unit is used for automatically generating a correction coefficient before the oscilloscope leaves a factory, and is configured to be used for realizing automatic compensation of the amplitude of the oscilloscope, so that the bandwidth is improved and the frequency response is optimized; because the hardware chips in the analog front-end conditioning module and the data acquisition module of the oscillograph are differentiated, the amplitude correction filter coefficient of each oscillograph is different, and therefore, each oscillograph needs to be automatically calculated before leaving a factory and is stored in a hard disk of the oscillograph;

the embedded CPU module controls the calibration signal generation module to output sine wave signals with 10MHz frequency and 500mVpp amplitude, and the sine wave signals are sent to the digital signal processing module for digital signal processing after passing through the analog front-end conditioning module and the data acquisition module; in the digital signal processing module, a data preprocessing unit works normally, a bandwidth and frequency response optimizing unit, a noise reduction filtering unit and a waveform reconstruction unit are all selected to be closed, and an oscilloscope stores the most original sampling data of a data acquisition module into a memory of a CPU; in the same way, a calibration signal is kept to output a sine wave signal of fixed 500mVpp, the frequency of 10MHz is stepped to 2.5GHz in sequence, the acquired original data is recorded and arranged into a curve Hy after multiple measurements, and the ideal frequency response curve of the oscilloscope is Hj, then the coefficient of the amplitude correction filter is Hj/Hy, the embedded CPU module stores the coefficient of the amplitude correction filter in the coefficient RAM of the amplitude correction filter of the digital signal processing module, and the bandwidth and frequency response optimization unit can realize that the amplitude flatness reaches +/-1 dB;

the noise reduction filter coefficient calculation unit is configured to be used for realizing the bandwidth limiting function of the oscilloscopes, and the noise reduction filter coefficient of each oscilloscope is fixed and only related to the digital low-pass filter of six gears of 20MHz, 250MHz, 500MHz, 1GHz, 1.5GHz and 2GHz selected by a user; the embedded CPU module stores the noise reduction filter coefficient calculated by the noise reduction filter coefficient calculating unit into a noise reduction filter coefficient RAM of the digital signal processing module; if the gear of the noise reduction filter is changed and is not 20MHz, 250MHz, 500MHz, 1GHz, 1.5GHz or 2GHz, the noise reduction filter coefficient calculation unit of the embedded CPU module needs to calculate once again and then stores the calculated value into the noise reduction filter coefficient RAM of the digital signal processing module;

the waveform reconstruction filter coefficient calculation unit is configured to be used for realizing the digital interpolation function of the oscilloscopes, and the waveform reconstruction filter coefficient of each oscilloscope is fixed and only related to the horizontal resolution and the time base gear of the liquid crystal screen of the oscilloscope; the embedded CPU module stores the waveform reconstruction filter coefficient calculated by the waveform reconstruction filter coefficient calculating unit into a waveform reconstruction filter coefficient RAM of the digital signal processing module; if the horizontal resolution or the time base gear of the liquid crystal screen of the oscilloscope changes, the waveform reconstruction filter coefficient calculation unit of the embedded CPU module needs to recalculate once and then store the waveform reconstruction filter coefficient into the waveform reconstruction filter coefficient RAM of the digital signal processing module.

The invention has the following beneficial technical effects:

1) the traditional analog device and software compensation and correction are replaced by a digital correction and compensation mode in the FPGA;

2) the automatic calibration of the gain and the offset of the ADC of the data acquisition module can be realized, the calibration precision is high, the calibration speed is high, and the calibration accuracy and effectiveness are improved;

3) amplitude compensation of the oscilloscope is realized in a digital mode, the bandwidth of the oscilloscope can be improved, the amplitude-frequency response optimization can be optimized, and the amplitude flatness can reach +/-1 dB;

4) noise reduction and filtering can be realized in a digital mode, and six digital filtering gears of 20MHz, 250MHz, 500MHz, 1GHz, 1.5GHz, 2GHz and the like can be realized;

5) waveform reconstruction is realized in a digital mode, the minimum time base of the oscilloscope can reach 5ps/div, and the maximum digital interpolation multiple is 2000 times;

6) the digital correction and compensation circuit and the method can be expanded and applied to oscilloscopes with higher bandwidths and higher sampling rates.

Drawings

FIG. 1 is a schematic block diagram of a digital correction and compensation circuit for an oscilloscope according to the present invention.

Detailed Description

The invention is described in further detail below with reference to the following figures and detailed description:

fig. 1 is a block diagram of a system composition of a digital correction and compensation circuit and method of an oscilloscope, the digital correction and compensation circuit comprises five parts of a calibration signal generation module, an analog front end conditioning module, a data acquisition module, a digital signal processing module, an embedded CPU module and the like, wherein the digital signal processing module comprises a data preprocessing unit, a bandwidth and frequency response optimization unit, a noise reduction filtering unit, a data storage control unit, a waveform reconstruction unit, a CPU control interaction unit and the like, and is a core module of the digital correction and compensation circuit.

1. Calibration signal generation module

In the scheme, the calibration signal production module mainly comprises a fast edge signal generation unit, a sine signal generation unit and a switch selection unit. The fast edge signal generating unit mainly generates a fast edge signal required by gain and phase calibration of an ADC (AAD08S010GA) in the data acquisition module, wherein the amplitude of the fast edge signal is generally 5/6 of the full scale of the rear-end ADC, and in the invention, the full scale of the ADC is 600mVpp, and the amplitude of the fast edge signal is 500 mVpp. The sine signal generating unit mainly generates a sine wave signal required by a bandwidth and flatness optimizing unit in the digital signal processing module, the maximum frequency of the sine wave signal is 1/4 of the sampling rate of an ADC (analog to digital converter) in the rear-end data acquisition module, the sampling rate of the ADC in the sine signal generating unit is 10GSa/s, the maximum frequency of the sine signal is 2.5GHz, and the frequency is stepped according to 1 kHz. The amplitude of the sinusoidal signal is typically 5/6 for the full scale of the back-end ADC, which in this invention is 600mVpp, and the amplitude of the sinusoidal signal is 500 mVpp. The switch selection is mainly used for switching the output of the fast edge signal and the sinusoidal signal, and the output amplitude is 500mVpp of the calibration signal JZ.

2. Analog front end conditioning module

In the scheme, the analog front-end conditioning module mainly comprises a switch selection unit, an attenuator unit and an amplifier unit. The switch selection unit mainly realizes the selection of the oscilloscope channel input signal CH and the calibration signal ZJ generated by the calibration signal generation module. When the oscilloscope selects the calibration signal ZJ, the oscilloscope is in an automatic calibration mode, so that the self calibration of the ADC in the data acquisition module and the automatic generation of the correction filter coefficient in the bandwidth and flatness optimization unit in the digital signal processing module are realized, in the scheme, the ZJ signal comes from the internal calibration signal generation module of the oscilloscope, and the amplitude is 500 mVpp. When the oscilloscope selects the channel signal CH, the oscilloscope can realize normal measurement on the measured object, the amplitude of the CH signal in the scheme is 4 mVpp-8 Vpp, and the signal frequency is the bandwidth of the oscilloscope, namely DC-2.5 GHz. The attenuator unit mainly attenuates the CH signal, if the amplitude of the input channel signal is 600 mVpp-8 Vpp, the full-scale range of the ADC in the data acquisition module is exceeded, in the scheme, the full-scale range of the ADC is 600mVpp, the attenuator module attenuates, and the attenuation multiple is CH/600 mV. The amplifier unit mainly amplifies the CH signal, if the amplitude of the input channel signal is 4 mVpp-600 mVpp, the amplitude is lower than the full scale range of the ADC in the data acquisition module, and in the scheme, the full scale range of the ADC is 600mVpp, the amplifier unit amplifies the channel signal, and the amplification factor is 600 mV/CH.

3. Data acquisition module

In the scheme, the data acquisition module mainly comprises a clock generation unit and an ADC unit. The clock generation unit mainly generates a 5GHz clock required by the rear-end ADC, and a digital integrated phase-locked loop LMX2952 frequency synthesizer is selected to realize the clock generation unit. The ADC unit is called an analog-to-digital converter, and mainly converts an analog signal CH of a channel into a digital signal, and then sends the digital signal to a digital signal processing unit at the back end to perform post-processing of data. In the scheme, an AAD08S010GA chip is adopted as an ADC unit, the chip realizes the conversion of analog to digital signals with 10GSa/S sampling rate and 8bit vertical resolution, and outputs a data stream of 80Gbps, the data stream generates a low-speed data stream of 2.5Gbps 32 in the ADC for realizing the receiving of a rear-end digital signal processing unit, and when the ADC outputs, a double-edge output mode is adopted, and the output clock is 1.25GHz, and the data stream bit is D [31:0] with 32 bit width, and the data stream is sent to a rear-end digital signal processing module.

4. Digital signal processing module

In the scheme, the digital signal processing module mainly comprises a data preprocessing unit, a bandwidth and frequency response optimizing unit, a noise reduction filtering unit, a data selector, a data storage control unit, a waveform reconstruction unit, a CPU interaction control unit and the like. The digital signal processing module is realized by adopting an FPGA (XCKU060-2FFVA 1517I).

The data preprocessing unit mainly comprises a data receiving unit, a speed reduction processing unit and a data recombination unit. In the scheme, the data receiving unit is mainly used for receiving a 1.25GHz double-clock edge and a 32-bit data stream D [31:0] output by the data acquisition module, converting a differential input signal into a single-ended signal and outputting the single-ended signal, and converting the single-ended signal into a 64-bit data stream DY [63:0] of the 1.25GHz single-clock edge. The speed reduction processing unit mainly converts the 64-bit data DY [63:0] of 1.25GHz into a 256-bit data DJ [255:0] of 312.5MHz with lower speed, and the clock requirement of FPGA internal data processing is met. The data recombination unit mainly realizes the recombination and arrangement of the 256-bit data stream DJ [255:0] of 312.5MHz, and the 256-bit data stream DJ [255:0] is arranged and recombined according to the sampling sequence of the sampling clock to form a new 256-bit data stream DZ [255:0] of 312.5 MHz.

The bandwidth and frequency response are composed of an optimization unit, a main amplitude correction filter coefficient RAM and an FIR filter unit. In the scheme, the bandwidth and frequency response optimizing unit is a software function of the oscilloscope, the voltage characteristic of the waveform of the oscilloscope in the vertical direction is mainly improved, and a user can select to turn on or turn off the bandwidth and frequency response optimizing unit. When the selection is closed, the data preprocessing unit at the front end directly sends the 256-bit data stream DZ [255:0] of 312.5MHz to the rear end for subsequent processing, when the selection is opened, the data preprocessing unit at the front end directly sends the 256-bit data stream DZ [255:0] of 312.5MHz to the bandwidth and frequency response optimizing unit for processing, the unit is mainly realized by a digital filter of FIR, and the FIR filter mainly comprises a multiplication and adder of MAC, a delay timer, a lookup table and the like. After multiplying 256 bit data stream DZ [255:0] of 312.5MHz with the correction coefficient in the coefficient RAM of the amplitude correction filter, the data stream is added with the MAC of the previous stage and finally output to the next stage MAC structure, and after multi-stage FIR filtering, the corrected DYH [255:0] is output and sent to the back end for subsequent processing. The specific numerical value of the correction filter coefficient in the amplitude correction filter coefficient RAM is automatically generated by an amplitude correction filter coefficient calculation unit of the embedded CPU module.

The noise reduction filtering unit mainly comprises a noise reduction filter coefficient RAM, a CIC decimation filter, an FIR filter, a CIC interpolation filter and the like. In the scheme, the noise reduction filtering unit is a software function of the oscilloscope, and a user can select to turn on or turn off the noise reduction filtering unit. When the switch-off is selected, the 256-bit data stream DZ [255:0] of the front end 312.5MHz is sent directly to the back end for subsequent processing. When the digital filter is selected to be opened, 256-bit data flow DZ [255:0] of the front end 312.5MHz is sent to a noise reduction filtering unit for processing, the noise reduction filtering unit is a software function, a user can select digital low-pass filters with six gears of 20MHz, 250MHz, 500MHz, 1GHz, 1.5GHz, 2GHz and the like, and the digital filters with the six gears are realized by adopting different CIC + FIR cascade combinations and filter coefficient selection. When a user selects the bandwidth limitation with larger pass band ranges such as 1.5GHz and 2GHz, the oscilloscope performs delay processing on data according to the CIC extraction, FIR filtering and CIC interpolation filter of the selective opening part so as to realize signal synchronization with the channel without the bandwidth limitation. When a user selects a lower pass band range of 20MHz, 250MHz and the like, the scheme starts a rear-end CIC extraction + FIR filtering + CIC interpolation cascade module, firstly extracts a sampling signal by power of 2 to reduce the data stream rate to the acceptable working frequency of the FIR filter, the FIR filter carries out multiply-add operation on an input signal and a preset filtering coefficient, and finally completes interpolation processing on the filtered signal by the interpolation CIC module to generate data with the same total bit width, namely 256-bit data stream DZ [255:0] of 312.5MHz passes through a noise reduction filtering unit and then outputs a new 256-bit data stream DJZ [255:0] of 312.5 MHz. The specific numerical value of the noise reduction filter coefficient in the noise reduction filter coefficient RAM is automatically generated by the noise reduction filter coefficient calculation unit of the embedded CPU module.

The waveform reconstruction unit mainly comprises a waveform reconstruction filter coefficient RAM and an FIR interpolation filter unit. In the scheme, the waveform reconstruction unit is a software function of the oscilloscope, the time characteristic of the waveform of the oscilloscope in the horizontal direction is mainly improved, and a user can select to turn on or turn off the waveform reconstruction unit. When the selection is closed, the front noise reduction filter unit directly stores the 256-bit data stream DJZ [255:0] of 312.5MHz in the RAM memory inside the FPGA under the control of the data storage control unit, when the selection is opened, the front noise reduction filter unit directly sends the 256-bit data stream DJZ [255:0] of 312.5MHz to the waveform reconstruction unit for processing, the unit is mainly realized by an FIR interpolation filter, and the FIR interpolation filter mainly comprises a MAC multiplication and adder, a time delay, a lookup table and the like. 256 bit data stream DJZ [255:0] of 312.5MHz is multiplied by a correction coefficient in a waveform reconstruction filter coefficient RAM, added with the MAC of the previous stage and finally output to a lower-level MAC structure, and DCJ [255:0] of waveform reconstruction is output after multi-stage FIR interpolation filtering and stored in a RAM memory in the FPGA under the control of a data storage control unit. The specific numerical value of the waveform reconstruction filter coefficient in the waveform reconstruction filter coefficient RAM is generated by a waveform reconstruction filter coefficient calculation unit of the embedded CPU module.

The data storage control unit mainly stores the 256-bit data stream DCJ [255:0] of 312.5MHz output by the waveform reconstruction unit into a memory RAM inside the FPGA. The embedded CPU module sends the sampling data DCJ (255: 0) to the display screen for displaying through a CPU interface interaction control unit in the digital signal processing module.

The CPU interaction control unit is mainly an interface for interaction between the embedded CPU module and the digital signal processing module, and data interaction, command interaction and the like between the two modules are realized through the interface.

5. Embedded CPU module

In the scheme, the embedded CPU module is a main controller of the oscilloscope and is also a human-computer interface for interaction between the oscilloscope and a user. In the invention of the digital correction and compensation circuit and method of the oscilloscope, an embedded CPU module mainly comprises an amplitude correction filter coefficient calculating unit, a noise reduction filter coefficient calculating unit, a waveform reconstruction filter coefficient calculating unit and the like. The embedded CPU module communicates with a CPU interaction control unit interface of the digital signal processing module through a PCIe2.0 interface, and realizes interaction and transmission of control commands and acquired data.

The amplitude correction filter coefficient calculation unit needs to automatically generate a correction coefficient before the oscilloscope leaves a factory, so that the automatic compensation of the amplitude of the oscilloscope is realized, and the bandwidth is improved and the frequency response is optimized. Because the difference between hardware chips in the analog front-end conditioning module and the data acquisition module of the oscillograph causes the difference between the amplitude correction filter coefficients of each oscillograph, each oscillograph has to be automatically calculated before leaving the factory and stored in a hard disk of the oscillograph. The embedded CPU module controls the calibration signal generation module to output sine wave signals with 10MHz frequency and 500mVpp amplitude, and the sine wave signals are sent to the digital signal processing module for digital signal processing after passing through the analog front-end conditioning module and the data acquisition module. In the digital signal processing module, the data preprocessing unit works normally, the bandwidth and frequency response optimizing unit, the noise reduction filtering unit and the waveform reconstruction unit are all selected to be closed, and the oscilloscope stores the most original sampling data of the data acquisition module into the memory of the CPU. In the same way, a sine wave signal with fixed 500mVpp is output by a calibration signal, the frequency is stepped to 2.5GHz in sequence by 10MHz, the acquired original data is recorded and arranged into a curve Hy after multiple measurements, the ideal frequency response curve of the oscilloscope is Hj, the coefficient of the amplitude correction filter is Hj/Hy, the coefficient of the amplitude correction filter is stored in an amplitude correction filter coefficient RAM of the digital signal processing module by the embedded CPU module, and the flatness of the amplitude can reach +/-1 dB by the bandwidth and frequency response optimization unit.

The noise reduction filter coefficient calculation unit mainly realizes the bandwidth limiting function of the oscilloscope, is a standard function of the oscilloscope, and the noise reduction filter coefficient of each oscilloscope is fixed and is only related to the digital low-pass filters with six gears, such as 20MHz, 250MHz, 500MHz, 1GHz, 1.5GHz and 2GHz, selected by a user. And the embedded CPU module stores the noise reduction filter coefficient calculated by the noise reduction filter coefficient calculating unit into a noise reduction filter coefficient RAM of the digital signal processing module. If the gear of the noise reduction filter is changed and is not 20MHz, 250MHz, 500MHz, 1GHz, 1.5GHz or 2GHz, the noise reduction filter coefficient calculation unit of the embedded CPU module needs to recalculate once and then store the recalculated noise reduction filter coefficient into the noise reduction filter coefficient RAM of the digital signal processing module.

The waveform reconstruction filter coefficient calculating unit mainly realizes the digital interpolation function of the oscillograph, which is a standard function of the oscillograph, the waveform reconstruction filter coefficient of each oscillograph is fixed and is only related to the horizontal resolution of a liquid crystal screen and a time base gear of the oscillograph, the horizontal resolution of the liquid crystal screen is 1000 points, and the time base gear is 5 ps/div-1000 s/div. And the embedded CPU module stores the waveform reconstruction filter coefficient calculated by the waveform reconstruction filter coefficient calculating unit into a waveform reconstruction filter coefficient RAM of the digital signal processing module. If the horizontal resolution or the time base gear of the liquid crystal screen of the oscilloscope changes, the waveform reconstruction filter coefficient calculation unit of the embedded CPU module needs to recalculate once and then store the waveform reconstruction filter coefficient in the waveform reconstruction filter coefficient RAM of the digital signal processing module. The minimum time base gear of the invention is 5ps, the maximum interpolation multiple of the waveform reconstruction filter is 2000 times.

The invention is realized in FPGA by adopting digital signal processing mode; a mathematical operation point is inserted between two real sampling points by a waveform reconstruction module by utilizing a linear interpolation or SINC interpolation algorithm, so that the measurement resolution, the measurement precision and the display quality of the oscilloscope are improved, and the waveform is reconstructed more accurately; the bandwidth of the oscilloscope is expanded through the bandwidth and flatness optimizing module, and the flatness of the frequency response of the oscilloscope is improved; the background noise of the oscilloscope is reduced through the noise reduction and filtering module, and the precision of amplitude measurement and time measurement is enhanced; because the digital signal processing mode is adopted in the FPGA for digital correction and compensation, each module adopts a parallel framework, the processing speed is high, the efficiency is high, the waveform display quality and the measurement precision of the oscilloscope are improved, the waveform refreshing rate of the oscilloscope is increased, and the instantaneity of the oscilloscope is improved.

It is to be understood that the above description is not intended to limit the present invention, and the present invention is not limited to the above examples, and those skilled in the art may make modifications, alterations, additions or substitutions within the spirit and scope of the present invention.

Claims (10)

1. A digital correction and compensation circuit for an oscilloscope, comprising: the device comprises a calibration signal generation module, an analog front end conditioning module, a data acquisition module, a digital signal processing module and an embedded CPU module; wherein, the digital signal processing module is a core module;

the calibration signal generation module is configured to generate a fast edge and a sine signal required by oscilloscope calibration, the signal amplitude is 500mVpp, the fast edge signal frequency is fixed 1kHz, the sine wave frequency is 10 MHz-2.5 GHz, and the frequency adjustment step is 10 MHz;

the analog front-end conditioning module is configured to condition an input signal CH and a calibration signal for realizing an oscilloscope channel; the input frequency range of the analog front-end conditioning module is DC-2.5 GHz, the amplitude range is 4 mVpp-8 Vpp, the output frequency range is DC-2.5 GHz, and the amplitude range is 2.35 mV-600 mVpp;

the data acquisition module is configured to acquire a signal output by the analog front-end conditioning module;

a digital signal processing module configured to process the digital signal;

and the embedded CPU module is configured to communicate with a CPU interaction control unit interface of the digital signal processing module through a PCIe2.0 interface, so as to realize interaction and transmission of control commands and acquired data.

2. The digital correction and compensation circuit for an oscilloscope of claim 1, wherein: the calibration signal generation module comprises a fast edge signal generation unit, a sine signal generation unit and a first switch selection unit;

a fast edge signal generation unit configured to generate a fast edge signal required for gain and phase calibration of an ADC in the data acquisition module;

the sine signal generating unit is configured to generate 1/4 the maximum frequency of the sine wave signal required by the bandwidth and flatness optimizing unit in the digital signal processing module is the sampling rate of the ADC in the back-end data acquisition module;

a first switch selection unit configured to switch outputs of the fast edge signal and the sinusoidal signal, outputting a calibration signal JZ having an amplitude of 500 mVpp.

3. The digital correction and compensation circuit for an oscilloscope of claim 1, wherein: the analog front-end conditioning module comprises a second switch selection unit, an attenuator unit and an amplifier unit;

the second switch selection unit is configured to select the oscilloscope channel input signal CH and the calibration signal ZJ generated by the calibration signal generation module; when the oscilloscope selects the calibration signal ZJ, the oscilloscope is in an automatic calibration mode, so that the self calibration of an ADC in the data acquisition module and the automatic generation of the coefficient of a correction filter in a bandwidth and flatness optimization unit in the digital signal processing module are realized, the ZJ signal comes from an internal calibration signal generation module of the oscilloscope, and the amplitude is 500 mVpp; when the oscilloscope selects the channel signal CH, the oscilloscope can realize normal measurement on the measured object, the amplitude of the CH signal is 4 mVpp-8 Vpp, and the signal frequency is the bandwidth of the oscilloscope, namely DC-2.5 GHz;

the attenuator unit is configured to attenuate the CH signal, if the amplitude of the input channel signal is 600 mVpp-8 Vpp, the input channel signal exceeds the full-scale range of the ADC in the data acquisition module, and the full-scale voltage of the ADC is 600mVpp, the attenuator module attenuates, and the attenuation multiple is CH/600 mV;

and the amplifier unit is configured to amplify the CH signal, and if the amplitude of the input channel signal is 4 mVpp-600 mVpp, the channel signal is lower than the full scale range of the ADC in the data acquisition module, and the full scale voltage of the ADC is 600mVpp, the amplifier unit amplifies the channel signal by the amplification factor of 600 mV/CH.

4. The digital correction and compensation circuit for an oscilloscope of claim 1, wherein: the data acquisition module comprises a clock generation unit and an ADC unit;

a clock generation unit configured to generate a 5GHz clock to the ADC unit;

and the ADC unit is configured to convert the analog signal CH of the channel into a digital signal, and then send the digital signal to the digital signal processing unit at the back end for post-processing of data.

5. The digital correction and compensation circuit for an oscilloscope of claim 4, wherein: the clock generation unit selects a digital integrated phase-locked loop LMX2952 frequency synthesizer; the ADC unit adopts AAD08S010GA chip, which realizes the conversion of analog to digital signal with 10GSa/S sampling rate and 8bit vertical resolution, outputs 80Gbps data stream, and generates 2.5Gbps 32 low-speed data stream in the ADC for receiving by the back-end digital signal processing unit, when the ADC outputs, it adopts double-edge output mode, the output clock is 1.25GHz, the data stream bit is 32 bit wide D31: 0, and sends it to the back-end digital signal processing module.

6. The digital correction and compensation circuit for an oscilloscope of claim 1, wherein: the digital signal processing module adopts an FPGA with the model number of XCKU060-2FFVA1517I and comprises a data preprocessing unit, a bandwidth and frequency response optimizing unit, a noise reduction filtering unit, a data selector, a data storage control unit, a waveform rebuilding unit and a CPU interaction control unit;

a data preprocessing unit configured to process data;

the bandwidth and frequency response optimizing unit is configured to be used for improving the voltage characteristic of the waveform of the oscilloscope in the vertical direction, and a user can select to turn on or turn off the bandwidth and frequency response optimizing unit; when the switch-off is selected, the data preprocessing unit at the front end directly sends the 256-bit data stream DZ [255:0] of 312.5MHz to the back end for subsequent processing, and when the switch-on is selected, the data preprocessing unit at the front end directly sends the 256-bit data stream DZ [255:0] of 312.5MHz to the bandwidth and frequency response optimizing unit for processing;

the noise reduction filtering unit comprises a noise reduction filter coefficient RAM, a CIC decimation filter, an FIR filter and a CIC interpolation filter; the user can select to turn on or off the noise reduction filtering unit; when the selection is closed, the 256-bit data stream DZ [255:0] with the front end of 312.5MHz is directly sent to the back end for subsequent processing; when the selection is opened, the 256-bit data stream DZ [255:0] with the front end of 312.5MHz is sent to the noise reduction filter unit for processing; a user can select six-gear digital low-pass filters including 20MHz, 250MHz, 500MHz, 1GHz, 1.5GHz and 2GHz, and the six-gear digital filters are realized by adopting different CIC + FIR cascade combination and filter coefficient selection; when a user selects a larger bandwidth limit within the 1.5GHz or 2GHz pass band range, the oscilloscope performs delay processing on data according to CIC extraction, FIR filtering and CIC interpolation filter of a selected opening part so as to realize signal synchronization with a channel without opening the bandwidth limit; when a user selects a 20MHz or 250MHz lower pass band range, an oscilloscope starts a rear-end CIC extraction + FIR filtering + CIC interpolation cascade module, firstly extracts a sampling signal by a power of 2 to reduce the data stream rate to the acceptable working frequency of the FIR filter, the FIR filter performs multiply-add operation on an input signal and a preset filtering coefficient, and finally completes interpolation processing on the filtered signal by the interpolation CIC module to generate data with the same total bit width, namely 256-bit data stream DZ [255:0] of 312.5MHz passes through a noise reduction filtering unit and then outputs a new 256-bit data stream DJZ [255:0] of 312.5 MHz;

the waveform reconstruction unit is configured to improve the time characteristic of the oscilloscope waveform in the horizontal direction, and a user can select to turn on or turn off the waveform reconstruction unit; when the selection is closed, the noise reduction filtering unit at the front end directly stores the 256-bit data stream DJZ [255:0] of 312.5MHz into a RAM memory in the FPGA under the control of the data storage control unit; when the selection is opened, the noise reduction filtering unit at the front end directly sends the 256-bit data stream DJZ [255:0] of 312.5MHz to the waveform reconstruction unit for processing;

a data storage control unit configured to store the 256-bit data stream DCJ [255:0] of 312.5MHz output by the waveform reconstruction unit into a memory RAM inside the FPGA; the embedded CPU module sends the sampling data DCJ (255: 0) to a display screen for displaying through a CPU interface interaction control unit in the digital signal processing module;

a CPU interaction control unit configured for the embedded CPU module and the number.

7. The digital correction and compensation circuit for an oscilloscope of claim 6, wherein: the data preprocessing unit comprises a data receiving unit, a speed reduction processing unit and a data recombination unit;

the data receiving unit is configured to be used for receiving the 1.25GHz double clock edges and the 32-bit data flow D [31:0] output by the data acquisition module, and converting the differential input signals into single-ended signals to be output, wherein the single-ended signals are converted into 64-bit data flow DY [63:0] of the 1.25GHz single clock edges;

the speed reduction processing unit is configured to convert the 64-bit data DY [63:0] of 1.25GHz into a 256-bit data DJ [255:0] of 312.5MHz with lower speed, and the clock requirement of FPGA internal data processing is met;

and the data recombination unit is configured to realize the recombination and arrangement of the 256-bit data stream DJ [255:0] of 312.5MHz, and the data recombination unit is arranged and recombined according to the sampling sequence of the sampling clock to form a new 256-bit data stream DZ [255:0] of 312.5 MHz.

8. The digital correction and compensation circuit for an oscilloscope of claim 6, wherein: the bandwidth and frequency response optimizing unit comprises an amplitude correction filter coefficient RAM and an FIR filter unit;

the FIR filter unit comprises a multiplication and adder of MAC, a delayer and a lookup table; 256 bit data stream DZ [255:0] of 312.5MHz is multiplied by a correction coefficient in an amplitude correction filter coefficient RAM, added with the MAC of the previous stage and finally output to a lower-stage MAC structure, and then output corrected DYH [255:0] after multi-stage FIR filtering and then sent to the rear end for subsequent processing; the specific numerical value of the correction filter coefficient in the amplitude correction filter coefficient RAM is automatically generated by an amplitude correction filter coefficient calculation unit of the embedded CPU module.

9. The digital correction and compensation circuit for an oscilloscope of claim 6, wherein: the waveform reconstruction unit comprises a waveform reconstruction filter coefficient RAM and an FIR interpolation filter unit;

the FIR interpolation filter unit comprises a multiplication and adder of MAC, a delayer and a lookup table; 256 bit data stream DJZ [255:0] of 312.5MHz is multiplied by a correction coefficient in a waveform reconstruction filter coefficient RAM, added with a previous-stage MAC and finally output to a lower-stage MAC structure, and DCJ [255:0] of waveform reconstruction is output after multi-stage FIR interpolation filtering and stored in an RAM memory in the FPGA under the control of a data storage control unit; the specific numerical value of the waveform reconstruction filter coefficient in the waveform reconstruction filter coefficient RAM is generated by a waveform reconstruction filter coefficient calculation unit of the embedded CPU module.

10. The digital correction and compensation circuit for an oscilloscope of claim 1, wherein: the embedded CPU module comprises an amplitude correction filter coefficient calculating unit, a noise reduction filter coefficient calculating unit and a waveform reconstruction filter coefficient calculating unit;

the amplitude correction filter coefficient calculation unit is used for automatically generating a correction coefficient before the oscilloscope leaves a factory, and is configured to be used for realizing automatic compensation of the amplitude of the oscilloscope, so that the bandwidth is improved and the frequency response is optimized; because the hardware chips in the analog front-end conditioning module and the data acquisition module of the oscillograph are differentiated, the amplitude correction filter coefficient of each oscillograph is different, and therefore, each oscillograph needs to be automatically calculated before leaving a factory and is stored in a hard disk of the oscillograph;

the embedded CPU module controls the calibration signal generation module to output sine wave signals with 10MHz frequency and 500mVpp amplitude, and the sine wave signals are sent to the digital signal processing module for digital signal processing after passing through the analog front-end conditioning module and the data acquisition module; in the digital signal processing module, a data preprocessing unit works normally, a bandwidth and frequency response optimizing unit, a noise reduction filtering unit and a waveform reconstruction unit are all selected to be closed, and an oscilloscope stores the most original sampling data of a data acquisition module into a memory of a CPU; in the same way, a calibration signal is kept to output a sine wave signal of fixed 500mVpp, the frequency of 10MHz is stepped to 2.5GHz in sequence, the acquired original data is recorded and arranged into a curve Hy after multiple measurements, and the ideal frequency response curve of the oscilloscope is Hj, then the coefficient of the amplitude correction filter is Hj/Hy, the embedded CPU module stores the coefficient of the amplitude correction filter in the coefficient RAM of the amplitude correction filter of the digital signal processing module, and the bandwidth and frequency response optimization unit can realize that the amplitude flatness reaches +/-1 dB;

the noise reduction filter coefficient calculation unit is configured to be used for realizing the bandwidth limiting function of the oscilloscopes, and the noise reduction filter coefficient of each oscilloscope is fixed and only related to the digital low-pass filter of six gears of 20MHz, 250MHz, 500MHz, 1GHz, 1.5GHz and 2GHz selected by a user; the embedded CPU module stores the noise reduction filter coefficient calculated by the noise reduction filter coefficient calculating unit into a noise reduction filter coefficient RAM of the digital signal processing module; if the gear of the noise reduction filter is changed and is not 20MHz, 250MHz, 500MHz, 1GHz, 1.5GHz or 2GHz, the noise reduction filter coefficient calculation unit of the embedded CPU module needs to calculate once again and then stores the calculated value into the noise reduction filter coefficient RAM of the digital signal processing module;

the waveform reconstruction filter coefficient calculation unit is configured to be used for realizing the digital interpolation function of the oscilloscopes, and the waveform reconstruction filter coefficient of each oscilloscope is fixed and only related to the horizontal resolution and the time base gear of the liquid crystal screen of the oscilloscope; the embedded CPU module stores the waveform reconstruction filter coefficient calculated by the waveform reconstruction filter coefficient calculating unit into a waveform reconstruction filter coefficient RAM of the digital signal processing module; if the horizontal resolution or the time base gear of the liquid crystal screen of the oscilloscope changes, the waveform reconstruction filter coefficient calculation unit of the embedded CPU module needs to recalculate once and then store the waveform reconstruction filter coefficient into the waveform reconstruction filter coefficient RAM of the digital signal processing module.

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