CN114449057A

CN114449057A - Data transmission method and device

Info

Publication number: CN114449057A
Application number: CN202210107899.1A
Authority: CN
Inventors: 刘晓斌; 李辰; 高成超; 姚远
Original assignee: Beijing Weishi Rui Technology Co ltd
Current assignee: Beijing Weishi Rui Technology Co ltd
Priority date: 2022-01-28
Filing date: 2022-01-28
Publication date: 2022-05-06

Abstract

The application provides a data transmission method, which realizes data transmission based on UDP protocol by using FPGA. The method comprises the following steps: when a data receiving party receives a data segment based on a UDP protocol, updating the size of a receiving window, wherein the size of the receiving window refers to the size of data which can be received by the data receiving party at present; and controlling the data transfer amount of the data sending party according to the updated size of the receiving window so that the receiving queue of the data receiving party does not have the data overflow phenomenon, wherein the data transfer amount refers to the data transferred from the data buffer area of the data sending party to the sending queue. The method and the device realize the UDP/IP protocol stack on the basis of the FPGA programmable logic device, realize the high efficiency of data transmission by utilizing the UDP transmission rate, and increase the reliability of data transmission by controlling the data transfer amount of a data sender. The application also provides a data transmission device.

Description

Data transmission method and device

Technical Field

The present application relates to the field of communications technologies, and in particular, to a data transmission method and apparatus.

Background

With the rapid development of the internet, the ethernet has raised higher requirements for the transmission of high-performance, high-efficiency and large-capacity data, and in such applications with certain requirements for real-time performance and transmission rate, the processing capability of the network terminal for data transmission becomes an important factor restricting the development of such projects.

Currently, the I/O cannot meet the requirement of high-speed data processing, and the main reason is that the processing speed of the TCP/IP protocol is lower than that of the network. If the TCP/IP network protocol stack is processed at full speed, a large amount of CPU resources of the server are consumed, which becomes a network bottleneck.

Although the traditional User data packet Protocol (UDP) has high communication efficiency, it has poor reliability and is not suitable for an application environment with high reliability requirements. However, with the rapid development of network transmission, some application occasions need to improve the transmission reliability of both communication parties on the basis of ensuring high efficiency.

Disclosure of Invention

The application provides a data transmission method and device, which can ensure the high efficiency and reliability of data transmission.

In a first aspect, the present application provides a data transmission method, where the method is applied to a terminal device configured with a field programmable gate array FPGA, where the FPGA is used to implement data transmission based on a user datagram protocol UDP, and the method includes:

when a data receiving party receives a data segment based on a UDP protocol, updating the size of a receiving window, wherein the size of the receiving window refers to the size of data which can be received by the data receiving party at present;

and controlling the data transfer amount of a data sending party according to the updated size of the receiving window so that the receiving queue of the data receiving party does not have a data overflow phenomenon, wherein the data transfer amount refers to data transferred from the data buffer area of the data sending party to the sending queue.

Optionally, the controlling the data transfer amount of the data sender according to the updated size of the receiving window includes:

and controlling the data transfer amount of a data sending party to enable the unacknowledged data amount to be smaller than the size of the receiving window, wherein the unacknowledged data amount refers to the number of data segments which are sent out from the sending queue and are not acknowledged to be received.

determining the minimum data segment number in each data segment which is not received and confirmed in each data segment transmitted by the transmission queue as the minimum unconfirmed data number;

determining the data segment number of the next segment to be sent as the data number to be sent;

and controlling the data transfer amount of a data sender according to the size of the receiving window, the unconfirmed minimum data number and the number of the data to be sent.

Optionally, the controlling the data transfer amount of the data sender according to the size of the receive window, the unacknowledged minimum data number, and the data number to be sent includes:

the data transfer amount of a data sending party does not exceed a data amount threshold value;

wherein the data size threshold is the unacknowledged minimum data number + the receive window size-the data number to be transmitted.

Optionally, the method further includes:

for each data segment sequentially sent by the data sending party, judging whether a target data segment which is not received and confirmed exists, if so, enabling the data sending party to retransmit the target data segment;

the target data segment is any data segment which is not received and confirmed before the last data segment sent by the data sender.

Optionally, the causing the data sending side to retransmit the target data segment includes:

and enabling the data sending party to carry out packet loss retransmission or overtime retransmission on the target data segment.

Optionally, the FPGA is further configured to implement data transmission based on an IP layer and a MAC layer.

In a second aspect, the present application provides a data transmission apparatus, where the apparatus is applied to a terminal device configured with a field programmable gate array FPGA, where the FPGA is used to implement data transmission based on a user datagram protocol UDP, and the apparatus includes:

a window updating unit, configured to update a size of a receiving window after a data receiving side receives a data segment based on a UDP protocol, where the size of the receiving window refers to a size of data that the data receiving side can receive at present;

and the data transfer unit is used for controlling the data transfer amount of a data sending party according to the updated size of the receiving window so that the receiving queue of the data receiving party does not have the data overflow phenomenon, wherein the data transfer amount refers to the data transferred from the data buffer area of the data sending party to the sending queue.

Optionally, the data transfer unit is specifically configured to:

Optionally, the data transfer unit includes:

a first determining subunit, configured to determine, as an unconfirmed minimum data number, a minimum data segment number in each data segment that is not received and confirmed, among the data segments sent by the sending queue;

a second determining subunit, configured to determine a data segment number of a next segment to be sent, as a data number to be sent;

and the data transfer subunit is used for controlling the data transfer amount of a data sender according to the size of the receiving window, the unacknowledged minimum data number and the data number to be sent.

Optionally, the data transfer subunit is specifically configured to:

the data transfer amount of a data sending party does not exceed a data amount threshold value; wherein the data size threshold is the unacknowledged minimum data number + the receive window size-the data number to be transmitted.

Optionally, the apparatus further comprises:

a data retransmission unit, configured to determine, for each data segment sequentially sent by the data sending side, whether a target data segment that is not received and confirmed exists, and if yes, cause the data sending side to retransmit the target data segment; the target data segment is any data segment which is not received and confirmed before the last data segment sent by the data sender.

Optionally, when the data transmitting side retransmits the target data segment, the data retransmission unit is specifically configured to: and enabling the data sending party to carry out packet loss retransmission or overtime retransmission on the target data segment.

In the technical solution provided by the present application, the method is applied to a terminal device configured with a field programmable gate array FPGA, where the FPGA is used to implement data transmission based on a user datagram protocol UDP, and specifically, after a data receiving side receives a data segment based on a UDP protocol, a size of a receiving window is updated, where the size of the receiving window refers to a size of data that the data receiving side can receive at present; and controlling the data transfer amount of the data sending party according to the updated size of the receiving window so that the receiving queue of the data receiving party does not have the data overflow phenomenon, wherein the data transfer amount refers to the data transferred from the data buffer area of the data sending party to the sending queue. Therefore, the method and the device realize the UDP/IP protocol stack on the basis of the FPGA programmable logic device, can support gigabit/gigabit Ethernet, realize high efficiency of data transmission by utilizing the UDP transmission rate, and increase the reliability of data transmission by controlling the data transfer quantity of a data sender.

Drawings

Fig. 1 is a schematic diagram of a reliable UDP transport protocol processing architecture based on an FPGA programmable logic device according to the present application;

FIG. 2 is a logic block diagram of an FPGA shown in the present application;

fig. 3 is a schematic diagram of a UDP reliable transport mechanism shown in the present application;

FIG. 4 is a diagram illustrating a data segment format according to the present application;

fig. 5 is a schematic diagram illustrating flow control of data transmission and reception according to the present application;

fig. 6 is a schematic flow chart of a data transmission method according to the present application;

FIG. 7 is a diagram of a transmit queue shown in the present application;

fig. 8 is a schematic diagram of data retransmission shown in the present application;

fig. 9 is a schematic diagram of an acknowledgment packet receiving sequence shown in the present application;

FIG. 10 is a functional block diagram illustrating the overall hardware circuitry of the present application;

fig. 11 is a schematic diagram illustrating a data transmission apparatus according to the present application.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

It is to be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present application. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.

Before describing the embodiments of the present application, some technical terms related to the embodiments of the present application will be described.

An FPGA (Field-Programmable Gate Array), which is a product of further development based on Programmable devices such as PAL, GAL, CPLD, etc. The circuit is a semi-custom circuit in the field of Application Specific Integrated Circuits (ASIC), not only overcomes the defects of the custom circuit, but also overcomes the defect that the number of gate circuits of the original programmable device is limited.

Tcp (transmission Control protocol), a transmission Control protocol, is a connection-oriented, reliable transport layer communication protocol based on byte streams.

Udp (user data gram protocol), i.e. a user data packet protocol, mainly functions to form network data traffic into a data packet form, and provide a transaction-oriented simple information transfer service.

ARP (Address Resolution protocol), namely an address Resolution protocol, works in a data link layer to realize the function of converting an IP address into a network interface layer address. The communication between ethernet devices requires not only the IP address of the counterpart but also the physical address of the counterpart.

Icmp (Internet control message protocol), which is an Internet control message protocol, is a sub-protocol of the TCP/IP protocol family, and is used to transmit control information between an IP host and a router.

Phy (physical), i.e., port physical layer, is a common abbreviation for the physical layer of the OSI model. And ethernet is a device that operates the physical layer of the OSI model. An ethernet PHY is a chip that can send and receive ethernet data frames.

Mac (media Access control), i.e. a medium Access control layer protocol, which is located in the lower half of a data link layer in the OSI seven-layer protocol and is mainly responsible for controlling and connecting physical media of a physical layer.

The embodiment of the application provides a data transmission method, which is applied to a terminal device configured with a Field Programmable Gate Array (FPGA), wherein the FPGA can be used for realizing data transmission based on a UDP protocol. Further, the FPGA can also be used to implement data transmission based on an IP layer and a MAC layer.

Specifically, the embodiment of the application can adopt an FPGA chip to process a TCP/IP protocol stack, and transfer the management, verification, calculation and other operations originally performed in the network protocol stack to the FPGA, thereby greatly liberating CPU resources at the cost of a very small hardware circuit and greatly improving the capability of the terminal equipment for processing network data. Since the TCP/IP protocol is a protocol cluster, which includes many protocols, UDP is one of the protocols, embodiments of the present application provide a reliable UDP transmission mechanism based on an FPGA programmable logic device based on a traditional UDP protocol, which is an end-to-end control mechanism and aims to improve bandwidth and performance of data transmission, that is, to improve efficiency and reliability of data transmission.

Referring to fig. 1, a schematic diagram of a reliable UDP transport protocol processing architecture based on an FPGA programmable logic device provided in the embodiment of the present application is shown. The drawings are all hardware logic circuit modules and IP cores realized by Verilog language, which is a hardware description language, describes the structure and behavior of the digital system hardware in text form, and can be used for representing logic circuit diagrams and logic expressions and also representing the logic functions completed by the digital logic system.

In fig. 1, the Ethernet subsystem mainly includes an Ethernet subsystem (Ethernet subsystem) IP core, which may be a gigabit Ethernet subsystem IP core (10G Ethernet subsystem) of Xilinx (saint), and further includes a MAC layer packet sending module, an IP layer packet sending module, and a UDP layer packet sending module, and further relates to an ARP address resolution protocol and an ICMP protocol.

For a better understanding of the embodiments of the present application, the following description is made in further detail with reference to the FPGA logic block shown in fig. 2.

In fig. 2, the MAC layer and physical layer PHY protocols of Ethernet can be realized using Ethernet subsytem ip core. The MAC part mainly completes tasks such as frame delimitation, synchronization, addressing, error detection and the like; the physical layer PHY completes the functions of coding, decoding, serialization, string connection and the like of data; the ARP module receives the ARP request and generates an ARP response message; the Packet Detection message Detection module completes protocol identification and analysis of the data message; the IPv4 module completes the package and unpacking of an IP layer; the ICMP module identifies the ICMP echo request and outputs an echo response message; the UDP module completes the functions of packet packing and unpacking of a UDP protocol, and meanwhile, a packet loss error retransmission mechanism is added on the traditional UDP protocol, so that the reliable transmission of data is ensured; the ARBITRATION module realizes the multi-port ARBITRATION and output of the user data.

It should be noted that, in the embodiment of the present application, the protocol is implemented by using a layered design method, so that the layers of the protocol are mutually independent, and the standard interface between the layers facilitates engineering modularization, signaling simplification, and maintenance. The modular design allows for individual updates to a protocol.

Regarding the UDP part, a reliable transport mechanism is added to the conventional UDP protocol, and UDP is bidirectional and all entities have the same structure. Referring to the schematic diagram of the UDP reliable transmission mechanism shown in fig. 3, when data needs to be sent, the sent data is sent to a data queue of a Sender, and then the Sender encapsulates the data into a data segment format and sends the data segment format to an underlying UDP Channel (i.e., UDP Channel). The encapsulated data segment format may be the data segment format shown in fig. 4.

Therefore, in the embodiment of the application, based on the FPGA programmable logic device, a complete UDP/IP protocol stack is realized by using verilog language, and the gigabit/gigabit Ethernet is supported. In addition, the embodiment of the application also adds a reliable transmission mechanism on the traditional UDP protocol, and not only utilizes the UDP transmission rate, but also increases the reliability.

The data transmission method provided in the embodiment of the present application is specifically described below with reference to fig. 3 and 4, and the data transmit-receive flow control diagrams shown in fig. 5.

Referring to fig. 6, a schematic flow chart of a data transmission method provided in an embodiment of the present application is shown, where the method includes the following steps:

s601: and when the data receiving party receives a data segment based on the UDP protocol, updating the size of a receiving window, wherein the size of the receiving window refers to the size of the data which can be received by the data receiving party at present.

It should be noted that, in a normal situation, after the data sending side sends a certain message, the data receiving side receives an acknowledgement message (including an ACK acknowledgement number) for the message. The transmission or reception of the message data may be performed in the data segment format shown in fig. 4.

In the embodiment of the present application, after the data receiving side receives a data segment based on the UDP protocol, a sliding window manner similar to TCP may be adopted to perform flow control. Referring to fig. 3 and 5, when the Receiver receives a data segment, the Receiver updates the receiving window size rwnd, which represents the size of data that the Receiver can receive currently.

Wherein the receive window size rwnd may be located in a header of the received data segment, such as the 16-bit window size shown in fig. 4.

S602: and controlling the data transfer amount of the data sending party according to the updated size of the receiving window so that the receiving queue of the data receiving party does not have the data overflow phenomenon, wherein the data transfer amount refers to the data transferred from the data buffer area of the data sending party to the sending queue.

In the embodiment of the present application, referring to fig. 3, the sender moves the data in the data buffer sender buffer to the sender sending queue. However, the amount of data to be moved needs to be controlled, so as to ensure that the data sent by the sender does not overflow the receiving queue of the Receiver. The Receiver resolves the size rwnd of the receiving window in the receiving data segment every time and tells the sender how much data can be received, and the sender performs flow control according to the rwnd in the receiving data segment to ensure that the data sent by the sender is not more than the size of the data which can be received by the Receiver.

The Flow Control shown in fig. 5 is to send a Flow Control message according to the buffer status of the Receiver, so as to prevent the buffer of the Receiver from overflowing. The speed of the sender is matched to the speed of the received (processed) data. The sender is to suppress the sending rate of the data so that the Receiver receives and receives the data.

In an implementation manner of the embodiment of the present application, the "controlling the data transfer amount of the data sending side according to the updated size of the receiving window" in S602 may include: the data transfer amount of the data sending party is controlled to make the unacknowledged data amount smaller than the size of the receiving window, wherein the unacknowledged data amount refers to the number of data segments which are sent out from the sending queue and are not acknowledged to be received.

This implementation is illustrated with reference to the transmit queue diagram shown in fig. 7. Fig. 7 shows the snd _ buf transmission queue at a certain time, in the figure, the minimum number snd _ unack of unacknowledged data segments is 8, the number snd _ nxt of the next data segment to be transmitted is 11, and the receiving solved window size rwnd is 6. The 8, 9, 10 data segments in the figure are all data segments that are not acknowledged, and this part of the data segment may be being transmitted on the data link being sent and received. In order to avoid overflow of the receiving queue of the Receiver, the area of the part needs to be limited to be smaller than rwnd, namely, the unacknowledged data amount is limited to be smaller than rwnd.

In an implementation manner of the embodiment of the present application, the "controlling the data transfer amount of the data sending side according to the updated size of the receiving window" in S602 may include:

determining the minimum data segment number in each data segment which is not received and confirmed in each data segment transmitted by the transmission queue as the minimum unconfirmed data number; determining the data segment number of the next segment to be sent as the data number to be sent; and controlling the data transfer amount of the data sender according to the size of the receiving window, the unconfirmed minimum data number and the number of the data to be sent.

When the data transfer amount of the data sender is controlled according to the size of the receiving window, the unacknowledged minimum data number, and the data number to be sent, the data transfer amount of the data sender may not exceed a data amount threshold, where the data amount threshold is the unacknowledged minimum data number + the size of the receiving window-the data number to be sent. That is, the data transfer amount does not exceed the data amount threshold send _ unack + rwnd-snd _ nxt, and it is ensured that the transmitted data does not overflow the receiving queue of the receiving side, where send _ unack is the minimum unacknowledged data number, rwnd is the receiving window size, and snd _ nxt is the data number to be transmitted, for example, in fig. 7, send _ unack is 8, snd _ nxt is 11, and rwnd is 6.

In addition, on the other side of the connection, the Receiver obtains data from the bottom UDP Channel, forwards the data to the buffer of the Receiver, performs Reorder sorting on the data, determines whether the data message is lost, and updates the loss list LostList shown in fig. 3.

For data received by a Receiver, the data is unpacked and then placed into a buffer of the Receiver, and then transferred into a Reorder under appropriate conditions. The reason is that packet loss, disorder and the like may occur in the process of message transmission, and in order to ensure the sequence, the received message needs to be put into the buffer area Receiver buffer first, and only when the sequence of the message segments in the buffer area Receiver buffer is correct, the message segments can be moved into the buffer for the user to receive.

For example, referring to the data retransmission diagram shown in fig. 8,

messages

1, 2, 3, and 4 of the sender correspond to

messages

1, 2, 3, and 4 of the Receiver, respectively, that is, under normal conditions, since the Receiver can solve the ACK acknowledgment number in the data segment received, regarding the message 1 sent by the sender, the Receiver can receive the acknowledgment message corresponding to the message 1, regarding the message 2 sent by the sender, the Receiver can receive the acknowledgment message corresponding to the message 2, regarding the message 3 sent by the sender, the Receiver can receive the acknowledgment message corresponding to the message 3, regarding the message 4 sent by the sender, the Receiver can receive the acknowledgment message corresponding to the message 4. In fig. 8, a gray node in the Receiver buffer of the Receiver indicates that the Receiver receives a message that can be moved to the Reorder, but only after the number 2 acknowledgment message arrives, the

number

2, 3, and 4 acknowledgment messages can be moved to the Reorder, that is, the message can be moved to the Reorder only when the sequence of the message segments in the Receiver buffer is correct.

In the prior art, the UDP protocol belongs to a connectionless user data packet protocol, connection does not need to be established before data is transmitted, any confirmation does not need to be given after a UDP message is received, data transmission is unreliable, data packets are easily lost, and the method is suitable for small file transmission.

In order to solve the above packet loss problem, the implementation of the present application may further include: and for each data segment sequentially sent by the data sending party, judging whether a target data segment which is not received and confirmed exists, if so, retransmitting the target data segment by the data sending party, wherein the target data segment is any data segment which is not received and confirmed before the last data segment sent by the data sending party.

Specifically, taking fig. 8 as an example, for the acknowledgment messages of

numbers

1, 2, 3, and 4 received by the Receiver, if the Receiver has already received the acknowledgment messages of

numbers

1, 3, and 4, but has not received the acknowledgment message of number 2 at a later time, the message of number 2 sent by the sender is the target data segment that needs to be retransmitted, so the Loss List linked List shown in fig. 3 can be updated to make the sender resend the message of number 2.

In an implementation manner of the embodiment of the present application, when the data sending side retransmits the target data segment, the data sending side may specifically perform packet loss retransmission or timeout retransmission on the target data segment.

In this implementation manner, regarding packet loss retransmission, if the receiver does not receive the n number acknowledgment message but receives the n +1, n +2 … … n + m number acknowledgment messages, the larger m is, the more times of ACK out-of-sequence of the n number message sent by the data sender is represented, thereby representing that the packet loss probability of the n number message sent by the data sender is larger, so that an out-of-sequence number threshold may be preset, and when the number of times of out-of-sequence of the n number message is larger than the threshold, the data sender retransmits the n number message. Taking the data retransmission diagram shown in fig. 8 and the acknowledgement message receiving sequence diagram shown in fig. 9 as an example, where fig. 9 shows that

acknowledgement messages

1, 4, and 3 are received in sequence, and the out-of-sequence number threshold may be set to be 2, based on this, if the sender sends

messages

1, 2, 3, and 4 in sequence, and then the Receiver receives

acknowledgement messages

1, 3, and 4, when the

acknowledgement messages

3 and 4 are received, the Loss List shown in fig. 3 is updated, so that the sender sends the sender resends the message 2.

Regarding the overtime retransmission, if the n number confirmation message is not received but the n +1 number confirmation message is received, timing is started, whether a timing duration ts (timestamp) exceeds a preset time threshold or not is judged, and if the timing duration ts (timestamp) exceeds the preset time threshold, the Loss List is updated to perform the overtime retransmission on the n number message. As shown in fig. 8 and fig. 9, when receiving the acknowledgment packet # 3, it is determined whether the ts timestamp exceeds the predetermined time threshold, and if so, the Loss List shown in fig. 3 may be updated, so that the sender retransmits the packet # 2.

Referring to fig. 10, a general functional block diagram of a hardware circuit provided in the embodiment of the present application is shown, where an FPGA may implement the data transmission function introduced in the above description, that is, based on an FPGA programmable logic device, a complete UDP/IP protocol stack is implemented, a gigabit/gigabit ethernet is supported, and a reliable transmission mechanism is added to a conventional UDP protocol, so that a UDP transmission rate is utilized and reliability is also increased.

In the data transmission method provided in the embodiment of the present application, the method is applied to a terminal device configured with a field programmable gate array FPGA, where the FPGA is used to implement data transmission based on a user datagram protocol UDP, and specifically, when a data receiving side receives a data segment based on a UDP protocol, a size of a receiving window is updated, where the size of the receiving window refers to a size of data that the data receiving side can receive at present; and controlling the data transfer amount of the data sending party according to the updated size of the receiving window so that the receiving queue of the data receiving party does not have the data overflow phenomenon, wherein the data transfer amount refers to the data transferred from the data buffer area of the data sending party to the sending queue. Therefore, the embodiment of the application is based on the FPGA programmable logic device, realizes a UDP/IP protocol stack, can support gigabit/gigabit Ethernet, realizes high efficiency of data transmission by utilizing the UDP transmission rate, and increases the reliability of data transmission by controlling the data transfer amount of a data sender.

Referring to fig. 11, a schematic composition diagram of a data transmission device provided in an embodiment of the present application is a terminal device configured with a field programmable gate array FPGA, where the FPGA is configured to implement data transmission based on a user datagram protocol UDP, and the device includes:

a window updating unit 1101, configured to update a size of a receiving window after a data receiving side receives a data segment based on a UDP protocol, where the size of the receiving window refers to a size of data that the data receiving side can receive at present;

a data transfer unit 1102, configured to control a data transfer amount of a data sending side according to the updated size of the receive window, so that a receive queue of the data receiving side does not overflow data, where the data transfer amount refers to data transferred from a data buffer of the data sending side to a send queue.

In an implementation manner of the embodiment of the present application, the data transfer unit 1102 is specifically configured to:

In one implementation manner of the embodiment of the present application, the data transfer unit 1102 includes:

In an implementation manner of the embodiment of the present application, the data transfer subunit is specifically configured to:

In an implementation manner of the embodiment of the present application, the apparatus further includes:

In an implementation manner of the embodiment of the present application, when the data retransmission unit enables the data sending side to retransmit the target data segment, the data retransmission unit is specifically configured to:

In an implementation manner of the embodiment of the present application, the FPGA is further configured to implement data transmission based on an IP layer and an MAC layer.

The implementation process of the functions and actions of each unit in the above device is specifically described in the implementation process of the corresponding step in the above method, and is not described herein again.

For the device embodiment, since it basically corresponds to the method embodiment, reference may be made to the partial description of the method embodiment for relevant points. The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one position, or may be distributed on multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the scheme of the application. One of ordinary skill in the art can understand and implement without inventive effort.

The above description is only a preferred embodiment of the present application and should not be taken as limiting the present application, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A data transmission method is applied to a terminal device configured with a Field Programmable Gate Array (FPGA), wherein the FPGA is used for realizing data transmission based on a User Datagram Protocol (UDP), and the method comprises the following steps:

2. The method of claim 1, wherein the controlling the data transfer amount of the data sender according to the updated size of the receiving window comprises:

3. The method of claim 1, wherein the controlling the data transfer amount of the data sender according to the updated size of the receiving window comprises:

4. The method of claim 3, wherein the controlling the data transfer amount of the data transmitting side according to the receiving window size, the unacknowledged minimum data number, and the data number to be transmitted comprises:

5. The method of claim 1, further comprising:

6. The method of claim 5, wherein the causing the data sender to retransmit the target data segment comprises:

7. The method according to any of claims 1-6, wherein the FPGA is further configured to implement data transmission based on an IP layer and a MAC layer.

8. A data transmission apparatus, wherein the apparatus is applied to a terminal device configured with a field programmable gate array FPGA, the FPGA being configured to implement data transmission based on a user datagram protocol UDP, the apparatus comprising:

9. The apparatus according to claim 8, wherein the data transfer unit is specifically configured to:

and controlling the data transfer amount of the data sending party to enable the unacknowledged data amount to be smaller than the size of the receiving window, wherein the unacknowledged data amount refers to the number of data segments which are sent out from the sending queue and are not acknowledged to be received.

10. The apparatus of claim 8 or 9, further comprising: