CN114446994A - Semiconductor substrate and manufacturing method thereof, and semiconductor device structure and manufacturing method thereof - Google Patents
Semiconductor substrate and manufacturing method thereof, and semiconductor device structure and manufacturing method thereof Download PDFInfo
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- CN114446994A CN114446994A CN202011195900.8A CN202011195900A CN114446994A CN 114446994 A CN114446994 A CN 114446994A CN 202011195900 A CN202011195900 A CN 202011195900A CN 114446994 A CN114446994 A CN 114446994A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
Abstract
The invention provides a semiconductor substrate and a manufacturing method thereof, and a semiconductor device structure and a manufacturing method thereof, wherein the semiconductor substrate comprises the following components from bottom to top: a substrate layer, an insulating layer and a semiconductor layer which are stacked; the electrostatic body penetrates through the semiconductor layer and the insulating layer, the bottom of the electrostatic body extends to the substrate layer, the semiconductor substrate comprises a device area and a non-device area, and the electrostatic body is arranged in the non-device area. According to the semiconductor substrate, the electrostatic body is formed in the non-device area, and the electrostatic charge generated in the semiconductor layer in the subsequent etching process can enter the substrate layer through the electrostatic body, so that point discharge is prevented.
Description
Technical Field
The present invention relates to the field of semiconductor device manufacturing, and in particular, to a semiconductor substrate and a manufacturing method thereof, and a semiconductor device structure and a manufacturing method thereof.
Background
Semiconductor devices are used in various electronic applications such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing layers of insulating or dielectric, conductive, and semiconductor materials over a semiconductor substrate, and then patterning the various material layers using photolithography to form circuit components and elements thereon.
Silicon-on-insulator (SOI) materials have the following advantages over conventional bulk silicon: 1. the dielectric isolation of elements in the integrated circuit can be realized, and the parasitic latch-up effect in a bulk silicon CMOS circuit is thoroughly eliminated. 2. The method also has the advantages of small parasitic capacitance, high integration density, high speed, simple process, small short channel effect, particular suitability for low-voltage and low-power consumption circuits and the like. However, due to the existence of the intermediate insulating layer, electrostatic charges generated in the etching process of the SOI material cannot be conducted away through bulk silicon, and a point discharge phenomenon (called as arcing) is easily generated, so that devices are scrapped, and the yield of a production line is seriously affected.
Disclosure of Invention
The invention discloses a semiconductor substrate and a manufacturing method thereof, and a semiconductor device structure and a manufacturing method thereof, which can solve the problem of point discharge caused by the fact that static charges generated in the etching process cannot be led out from a substrate layer due to the fact that an insulating layer exists above the substrate layer.
In order to solve the above technical problem, the present invention provides a semiconductor substrate, which includes, from bottom to top:
a substrate layer, an insulating layer and a semiconductor layer which are stacked;
the electrostatic body penetrates through the semiconductor layer and the insulating layer, the bottom of the electrostatic body extends to the substrate layer, the semiconductor substrate comprises a device area and a non-device area, and the electrostatic body is arranged in the non-device area.
The present invention also provides a semiconductor device structure using the above semiconductor substrate, the semiconductor device structure comprising:
a micro device formed in the semiconductor layer;
the dielectric layer is positioned on the semiconductor layer and covers the micro device;
and the conductive structure is arranged in the dielectric layer and is connected with the electrostatic body.
The invention also provides a manufacturing method of the semiconductor substrate, which comprises the following steps:
providing a first substrate, wherein the first substrate comprises a substrate layer, an insulating layer and a semiconductor layer which are sequentially stacked from bottom to top;
the semiconductor substrate comprises a device area and a non-device area, a plurality of grooves penetrating through the semiconductor layer and the insulating layer are formed in the non-device area, and the bottom surfaces of the grooves extend to the substrate layer;
an electrostatic body is formed in the trench.
The invention also provides a manufacturing method of the semiconductor device structure, which comprises the following steps:
forming a semiconductor substrate using the above-described method for manufacturing a semiconductor substrate;
forming a micro device on the semiconductor layer;
forming a dielectric layer covering the micro device and the semiconductor layer;
and forming a conductive structure in the dielectric layer to connect the electrostatic body.
The invention has the beneficial effects that:
according to the semiconductor substrate, the electrostatic body is formed in the non-device area, and the electrostatic charge generated in the semiconductor layer in the subsequent etching process can enter the substrate layer through the electrostatic body, so that point discharge is prevented.
Furthermore, the material of the electrostatic body is polysilicon, and the electrostatic body can be formed through a deposition process, so that the manufacturing is convenient.
The semiconductor device structure, the conductive structure and the static body are connected to lead out static charges generated in the dielectric layer in the manufacturing process.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent by describing in more detail exemplary embodiments thereof with reference to the attached drawings, in which like reference numerals generally represent like parts.
Fig. 1 shows a schematic structural view of a semiconductor substrate of embodiment 1.
Fig. 2 shows a schematic view of a structure of a semiconductor device in embodiment 2.
Fig. 3 to 8 are schematic structural diagrams corresponding to different steps of a method for manufacturing a semiconductor substrate according to embodiment 3.
Description of reference numerals:
10-a substrate layer; 11-an insulating layer; 12-a semiconductor layer; 13-a sacrificial layer; 14-a dielectric layer; 15-a conductive structure; 16-a micro device; 20-an electrostatic body; 21-layer of electrostatic bulk material.
Detailed Description
The invention is described in further detail below with reference to the figures and the specific embodiments. The advantages and features of the present invention will become more apparent from the following description and drawings, it being understood, however, that the concepts of the present invention may be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein. The drawings are in simplified form and are not to scale, but are provided for convenience and clarity in describing embodiments of the invention.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
If the method herein comprises a series of steps, the order in which these steps are presented herein is not necessarily the only order in which these steps may be performed, and some steps may be omitted and/or some other steps not described herein may be added to the method. Although elements in one drawing may be readily identified as such in other drawings, the present disclosure does not identify each element as being identical to each other in every drawing for clarity of description.
Example 1
An embodiment 1 of the present invention provides a semiconductor substrate, fig. 1 shows a schematic structural diagram of the semiconductor substrate of embodiment 1, and referring to fig. 1, the semiconductor substrate includes, from bottom to top:
a substrate layer 10, an insulating layer 11, and a semiconductor layer 12 stacked;
and the electrostatic body 20 penetrates through the semiconductor layer 12 and the insulating layer 11, the bottom of the electrostatic body 20 extends to the substrate layer 10, the semiconductor substrate comprises a device region and a non-device region, and the electrostatic body 20 is arranged in the non-device region.
Specifically, in the present embodiment, the substrate layer 10, the insulating layer 11 and the semiconductor layer 12 form a silicon-on-insulator (SOI), that is, the material of the substrate layer 10 is a semiconductor material, such as silicon, the material of the insulating layer is silicon dioxide, and the material of the semiconductor layer 12 is silicon. The semiconductor substrate of the present invention is used for manufacturing a plurality of micro devices thereon, wherein the region where the micro devices are formed is planned to be a device region, and the region where the micro devices are not formed is planned to be a non-device region. Typically, the non-device region includes a region where a scribe line (scribe line) of the semiconductor substrate is located and a region where a Seal ring (Seal ring) of the semiconductor substrate is located.
In this embodiment, the electrostatic body 20 is a plurality of isolated pillar structures, and the size of the electrostatic body 20 is nano-scale or micro-scale, such as 10 nm to 5 μm, such as 100 nm, 1 μm, and so on. The distance between two adjacent static bodies 20 is also in the nanometer or micrometer range, and in the alternative, the distance between two static bodies 20 is similar to the diameter of the static bodies. The scribe line (scribe line) of the semiconductor substrate is in a matrix form with alternate horizontal and vertical directions, and the plurality of electrostatic bodies 20 located in the scribe line (scribe line) region also form a matrix form. The region of the semiconductor substrate where the Seal ring (Seal ring) is located is an annular region, and the plurality of electrostatic bodies 20 located in the region where the Seal ring (Seal ring) is located are also formed in an annular form.
In this embodiment, the bottom of the electrostatic body 20 is connected to the upper surface of the substrate layer 10, and in another embodiment, the bottom of the electrostatic ring 20 extends at least to a partial thickness of the substrate layer 10, i.e. the lower portion of the electrostatic ring 20 is inserted into the substrate layer 10 or penetrates through the substrate layer 10.
The material of the electrostatic body 20 may be metal or polysilicon, alternatively doped polysilicon, which has a lower resistance and facilitates the introduction of electrostatic charges into the substrate layer 10.
In the semiconductor substrate of the embodiment, the electrostatic body is arranged in the non-device region, and the electrostatic charge generated in the semiconductor layer in the subsequent etching process can enter the substrate layer through the electrostatic body, so that the point discharge is prevented.
Example 2
Embodiment 2 provides a semiconductor device architecture, fig. 1 shows a schematic view of a semiconductor device structure of embodiment 2, please refer to fig. 2, the semiconductor device structure includes the semiconductor substrate of embodiment 1, and further includes:
a micro device 16 formed in the device region in the semiconductor layer 12;
a conductive structure 15 connected to the electrostatic body 20;
a dielectric layer 14 on the semiconductor layer 12 covering the micro device 16 and the conductive structure 15.
The micro device 16 may be a transistor such as a diode, a triode, or a MOS transistor. In this embodiment, the micro device 16 is a MOS transistor, wherein the source and drain of the MOS transistor are formed in the semiconductor layer 12, and the gate of the MOS transistor is formed in the dielectric layer 14. The dielectric layer 16 also has formed therein interconnects that electrically connect the micro devices 16 and conductive structures 15 that are connected to an electrostatic body. The height difference between the interconnect line and the conductive structure is not limited, and in the alternative, the top surfaces of the interconnect line and the conductive structure are flush. In this embodiment, the conductive structure 15 is formed on the upper surface of the electrostatic body 20 and has a columnar shape. The upper surfaces of all the electrostatic bodies 20 may be provided with the conductive structures 15, and the conductive structures 15 may be provided only on the upper surfaces of some of the electrostatic bodies 20. The material of the interconnection line includes metal, the material of the conductive structure includes metal, such as copper, aluminum, gold, tungsten, or the like, and the material of the electrostatic body 20 may be polysilicon. When an electrostatic charge is generated in the dielectric layer 14 due to an etching process or other processes, the electrostatic charge is introduced into the electrostatic body 20 through the conductive structure 15 and thus into the substrate layer 10, preventing a tip discharge.
Example 3
Embodiment 3 provides a method for manufacturing a semiconductor substrate, including the steps of:
s01: providing a first substrate, wherein the first substrate comprises a substrate layer, an insulating layer and a semiconductor layer which are sequentially stacked from bottom to top;
s02: the semiconductor substrate comprises a device area and a non-device area, a plurality of grooves penetrating through the semiconductor layer and the insulating layer are formed in the non-device area, and the bottom surfaces of the grooves extend to the substrate layer;
s03: an electrostatic body is formed in the trench.
It should be noted that S0N in this specification does not represent the sequence of the manufacturing process.
Fig. 3 to 7 are schematic structural diagrams corresponding to different steps of a method for manufacturing a semiconductor substrate according to embodiment 3. Please refer to fig. 3 to fig. 7, which illustrate the steps in detail.
Referring to fig. 3, a first substrate is provided, which includes a substrate layer 10, an insulating layer 11 and a semiconductor layer 12 stacked in this order from bottom to top. In this embodiment, the first substrate is of an SOI structure, that is, the substrate layer 10 is made of a semiconductor material, such as silicon, the insulating layer is made of silicon dioxide, and the semiconductor layer 12 is made of silicon.
Referring to fig. 4, in the present embodiment, a sacrificial layer 13 is formed on the upper surface of the semiconductor layer 12, the material of the sacrificial layer 13 includes silicon dioxide, silicon nitride or carbon, and the sacrificial layer 13 may be formed by a deposition process. The sacrificial layer 13 serves as an etching stop layer in a later process to prevent the upper surface of the semiconductor layer 12 from being damaged by over-etching. In another embodiment, the sacrificial layer 13 may not be formed, which simplifies the process flow, but easily damages the upper surface of the semiconductor layer 12 when the electrostatic material is removed in a later process.
Referring to fig. 5, a plurality of mutually isolated trenches 22 are formed in the non-device region of the first substrate by an etching process, wherein the bottom surfaces of the trenches 22 are flush with the top surface of the substrate layer 10; or the bottom surface of the trench 22 extends into the substrate layer 10. In the embodiment, the grooves 22 have a circular hole-shaped cross section, the size of the grooves 22 is on the nanometer scale or on the micrometer scale, such as 10 nm to 5 μm, such as 100 nm, 1 μm, etc., and the distance between two adjacent grooves 22 is also on the nanometer scale or on the micrometer scale. The minimum dimension of the trench 22 is determined by the ability to fill with electrostatic material in a later process. In the alternative, the distance between two adjacent grooves 22 is of similar size to the diameter of the grooves 22. In other embodiments, the cross-section of the trenches 22 may also be a stripe or other structure that facilitates the introduction of electrostatic charges into the substrate layer 10.
The semiconductor substrate of the present invention is used for manufacturing a plurality of micro devices thereon, wherein the region where the micro devices are planned to be formed is a device region, and the region where the micro devices are not formed is a non-device region. Typically, the non-device region includes a region where a scribe line (scribe line) of the semiconductor substrate is located and a region where a Seal ring (Seal ring) of the semiconductor substrate is located. In this embodiment, the scribe line (scribe line) of the semiconductor substrate is formed in a matrix shape with a vertical and horizontal interval, and the plurality of grooves 22 located in the scribe line region also form a matrix shape. The region of the semiconductor substrate where the Seal ring (Seal ring) is located is an annular region, and the plurality of grooves 22 located in the region of the Seal ring (Seal ring) are also formed in an annular form.
Referring to fig. 6, an electrostatic material layer 21 is formed over the surface of the sacrificial layer 13, and the electrostatic material layer is also filled into the trench. The material of the electrostatic material layer comprises metal or polysilicon, and is formed by a physical vapor deposition process when the material of the electrostatic material layer is metal, and is formed by a chemical vapor deposition process when the material of the electrostatic material layer is polysilicon.
Referring to fig. 7, the electrostatic material above the sacrificial layer 13 is removed by a wet etching process, the electrostatic material in the middle of the sacrificial layer is removed by an etching process, and the electrostatic material remaining in the semiconductor layer 12 constitutes an electrostatic body. The sacrificial layer 13 is removed by a wet etching process.
Referring to fig. 8, the sacrificial layer is removed to form a desired semiconductor substrate, and when the material of the sacrificial layer is silicon dioxide, it is removed by a wet etching process.
According to the semiconductor substrate manufactured by the method, static charges generated in the semiconductor layer in the subsequent etching process can enter the substrate layer through the static body, and point discharge is prevented. The material of the electrostatic body is polysilicon, and the electrostatic body can be formed through a deposition process and is convenient to manufacture.
Example 4
Embodiment 4 of the present invention provides a method for manufacturing a semiconductor device structure, including the steps of:
s01: forming a semiconductor substrate using the manufacturing method of embodiment 3;
s02: forming a micro device on the device region on the semiconductor layer;
s03: forming a dielectric layer covering the micro device and the semiconductor layer;
s04: and forming a conductive structure in the dielectric layer to connect the electrostatic body.
Fig. 2 shows a schematic view of a semiconductor device structure formed by the method of this embodiment, the semiconductor substrate includes a substrate layer 10, an insulating layer 11, a semiconductor layer 12, and an electrostatic body 20, the specific structure and materials of the semiconductor substrate refer to embodiment 1, and the manufacturing method of the semiconductor substrate refers to embodiment 3, which is not described herein again. The micro device in this embodiment includes a transistor, such as a diode, a triode, or a MOS transistor, for example, the source and drain of the MOS transistor are formed in the semiconductor layer 12, the gate is formed in the dielectric layer 14 above the semiconductor layer 12, and the dielectric layer 14 further has an interconnect line formed therein for connecting the micro device 16 and a conductive structure 15 formed therein for connecting the electrostatic body 20. The forming method of the conductive structure 15 may be: after the dielectric layer is formed, forming a through hole penetrating through the dielectric layer in the dielectric layer above the electrostatic body, wherein the bottom of the through hole is exposed out of the upper surface of the electrostatic body or extends into the electrostatic body; a conductive material is formed in the via to form the conductive structure 15. The material of the conductive structure 15 includes a metal such as copper, aluminum, gold, or tungsten. The shape and the position of the conductive structure 15 are referred to in embodiment 2, and will not be described in detail here.
The semiconductor device structure manufactured by the method of the present embodiment, the conductive structure and the electrostatic body are connected to derive electrostatic charges generated in the dielectric layer during the manufacturing process.
It should be noted that, in the present specification, all the embodiments are described in a related manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, as for the method embodiment, since it is basically similar to the structure embodiment, the description is simple, and the relevant points can be referred to the partial description of the method embodiment.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (25)
1. A semiconductor substrate, comprising, from bottom to top:
a substrate layer, an insulating layer and a semiconductor layer which are stacked;
the electrostatic body penetrates through the semiconductor layer and the insulating layer, the bottom of the electrostatic body extends to the substrate layer, the semiconductor substrate comprises a device area and a non-device area, and the electrostatic body is arranged in the non-device area.
2. The semiconductor substrate according to claim 1, wherein the non-device region comprises a region where a dicing groove of the semiconductor substrate is located and a region where the semiconductor substrate sealing ring is located.
3. The semiconductor substrate according to claim 1, wherein the electrostatic body is a plurality of pillar structures isolated from each other, or an interrupted or continuous ring structure.
4. The semiconductor substrate according to claim, wherein the electrostatic body in a region where the semiconductor substrate sealing ring is located forms an interrupted ring shape.
5. The semiconductor substrate according to claim 1, wherein the width of the electrostatic body is 10 nm to 5 μm.
6. The semiconductor substrate of claim 1, wherein a bottom of the electrostatic body is contiguous with a surface of the substrate layer or a bottom of the electrostatic ring extends at least a portion of a thickness of the substrate layer.
7. The semiconductor substrate of claim 1, wherein the material of the electrostatic body comprises a metal or polysilicon, or a combination thereof.
8. The semiconductor substrate of claim 7, wherein the polysilicon is doped polysilicon.
9. A semiconductor device structure using the semiconductor substrate according to any one of claims 1 to 8, comprising:
a micro device formed in the device region in the semiconductor layer;
and the conductive structure is connected with the electrostatic body.
And the dielectric layer is positioned on the semiconductor layer and covers the micro device and the conductive structure.
10. The semiconductor device structure of claim 9, wherein the conductive structure is a pillar disposed on an upper surface of the electrostatic body.
11. The semiconductor device structure of claim 9, wherein the material of the conductive structure comprises a metal and the material of the electrostatic body comprises polysilicon.
12. The semiconductor device structure of claim 9, wherein the micro device comprises a transistor.
13. The semiconductor device structure of claim 9, further comprising an interconnect line in the dielectric layer electrically connecting the micro device, a top surface of the interconnect line being flush with a top surface of the conductive structure.
14. The semiconductor device structure of claim 9, wherein the material of the interconnect line comprises a metal and the material of the conductive structure comprises polysilicon or a metal.
15. A method for manufacturing a semiconductor substrate, comprising:
providing a first substrate, wherein the first substrate comprises a substrate layer, an insulating layer and a semiconductor layer which are sequentially stacked from bottom to top;
the semiconductor substrate comprises a device area and a non-device area, a plurality of grooves penetrating through the semiconductor layer and the insulating layer are formed in the non-device area, and the bottom surfaces of the grooves extend to the substrate layer;
an electrostatic body is formed in the trench.
16. The method for manufacturing a semiconductor substrate according to claim 15, wherein the forming the trench comprises:
forming a plurality of mutually isolated grooves by an etching process, wherein the bottom surfaces of the grooves are flush with the top surface of the substrate layer; or the bottom surface of the trench extends into the substrate layer.
17. The method of manufacturing a semiconductor substrate according to claim 15, further comprising, before forming the trench: forming a sacrificial layer on the semiconductor layer; when the groove is formed, the groove penetrates through the sacrificial layer; after forming the electrostatic body, removing the sacrificial layer.
18. The method for manufacturing a semiconductor substrate according to claim 17, wherein the forming the electrostatic body comprises:
after the groove is formed, forming an electrostatic material layer at the groove and above the surface of the sacrificial layer, and removing the electrostatic material layer above the sacrificial layer and in the sacrificial layer, wherein the electrostatic body comprises the electrostatic material layer above the groove area.
19. The method of manufacturing a semiconductor substrate according to claim 15, wherein a width of the trench is 10 nm to 5 μm.
20. The method for manufacturing a semiconductor substrate according to claim 15, wherein a material of the electrostatic body comprises a metal or polysilicon.
21. The method of manufacturing a semiconductor substrate according to claim 20, wherein the polysilicon is doped polysilicon.
22. The method for manufacturing a semiconductor substrate according to claim 15, wherein a distance between adjacent ones of the static bodies is 10 nm to 5 μm.
23. The method for manufacturing a semiconductor substrate according to claim 15, wherein the non-device region comprises: the area of the scribing groove of the semiconductor substrate and/or the area of the sealing ring of the semiconductor substrate.
24. A method of fabricating a semiconductor device structure, comprising:
forming a semiconductor substrate using the method of any one of claims 15 to 24;
forming a micro device in the device region on the semiconductor layer;
forming a dielectric layer covering the micro device and the semiconductor layer;
and forming a conductive structure in the dielectric layer to connect the electrostatic body.
25. The method of claim 24, wherein forming a conductive structure comprises:
after the dielectric layer is formed, forming a through hole penetrating through the dielectric layer in the dielectric layer above the electrostatic body, wherein the bottom of the through hole is exposed out of the upper surface of the electrostatic body or extends into the electrostatic body;
forming a conductive material in the via to form the conductive structure.
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| CN202011195900.8A CN114446994A (en) | 2020-10-30 | 2020-10-30 | Semiconductor substrate and manufacturing method thereof, and semiconductor device structure and manufacturing method thereof |
| PCT/CN2021/127859 WO2022089632A1 (en) | 2020-10-30 | 2021-11-01 | Semiconductor substrate and manufacturing method therefor, and semiconductor device structure and manufacturing method therefor |
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| CN202011195900.8A CN114446994A (en) | 2020-10-30 | 2020-10-30 | Semiconductor substrate and manufacturing method thereof, and semiconductor device structure and manufacturing method thereof |
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| CN100468704C (en) * | 2006-12-04 | 2009-03-11 | 中芯国际集成电路制造(上海)有限公司 | Production method of SONOS flash memory |
| US7638376B2 (en) * | 2007-01-12 | 2009-12-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming SOI device |
| CN102044523B (en) * | 2009-10-14 | 2012-08-22 | 无锡华润上华半导体有限公司 | Semiconductor device structure and manufacturing method thereof |
| US9799557B2 (en) * | 2014-01-22 | 2017-10-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device structure with metal ring on silicon-on-insulator (SOI) substrate |
| CN107346729A (en) * | 2016-05-04 | 2017-11-14 | 北大方正集团有限公司 | Substrate of semiconductor devices and preparation method thereof and semiconductor devices |
| CN110739265B (en) * | 2018-07-18 | 2022-07-15 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor structure and forming method thereof |
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2020
- 2020-10-30 CN CN202011195900.8A patent/CN114446994A/en active Pending
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2021
- 2021-11-01 WO PCT/CN2021/127859 patent/WO2022089632A1/en active Application Filing
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