CN114446779A - Deep silicon etching method and semiconductor process equipment - Google Patents

Deep silicon etching method and semiconductor process equipment Download PDF

Info

Publication number
CN114446779A
CN114446779A CN202111662968.7A CN202111662968A CN114446779A CN 114446779 A CN114446779 A CN 114446779A CN 202111662968 A CN202111662968 A CN 202111662968A CN 114446779 A CN114446779 A CN 114446779A
Authority
CN
China
Prior art keywords
etching
parameter
curve
deposition
process parameters
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202111662968.7A
Other languages
Chinese (zh)
Other versions
CN114446779B (en
Inventor
林源为
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xi'an North Huachuang Microelectronic Equipment Co ltd
Beijing Naura Microelectronics Equipment Co Ltd
Original Assignee
Xi'an North Huachuang Microelectronic Equipment Co ltd
Beijing Naura Microelectronics Equipment Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xi'an North Huachuang Microelectronic Equipment Co ltd, Beijing Naura Microelectronics Equipment Co Ltd filed Critical Xi'an North Huachuang Microelectronic Equipment Co ltd
Priority to CN202111662968.7A priority Critical patent/CN114446779B/en
Priority claimed from CN202111662968.7A external-priority patent/CN114446779B/en
Publication of CN114446779A publication Critical patent/CN114446779A/en
Application granted granted Critical
Publication of CN114446779B publication Critical patent/CN114446779B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065Plasma etching; Reactive-ion etching
    • H01L21/30655Plasma etching; Reactive-ion etching comprising alternated and repeated etching and passivation steps, e.g. Bosch process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67017Apparatus for fluid treatment
    • H01L21/67063Apparatus for fluid treatment for etching
    • H01L21/67069Apparatus for fluid treatment for etching for drying etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

The embodiment of the invention provides a deep silicon etching method and semiconductor process equipment, which are applied to the technical field of semiconductor equipment, and the method comprises the following steps: the method comprises the steps of obtaining an initial parameter value and a final parameter value of a target process parameter and real-time parameter values of other process parameters, determining the real-time parameter value of the target process parameter corresponding to the etching times of an etching area, carrying out deposition passivation by using the real-time parameter value of the deposition process parameter, carrying out etching by using the real-time parameter value of the etching process parameter, repeating the step of determining the real-time parameter value of the target process parameter, and carrying out deposition passivation and etching on the etching area until the etching times reach the total etching times. The parameter values of the process parameters change according to an S-shaped curve along with the increase of the etching times, so that the etching strength in the early stage and the later stage of etching and the etching strength in the middle stage of etching are different, and the size difference between the middle part and the lower part of the deep silicon structure can be reduced.

Description

Deep silicon etching method and semiconductor process equipment
Technical Field
The invention relates to the technical field of semiconductor equipment, in particular to a deep silicon etching method and semiconductor process equipment.
Background
Deep Silicon etching is an important process in the field of microelectronics, and deep Silicon structures such as Through Silicon Vias (TSV) and trench gates formed by etching by the process can obviously improve the performance of devices and reduce the power consumption and the volume of the devices.
At present, a dry etching process is mainly adopted for deep silicon etching, and in the dry etching process, a deposition step and an etching step are alternately carried out for deep silicon etching. In the deposition step, deposition gas is introduced into a process chamber in the semiconductor processing equipment, and a polymer layer (also called as a passivation layer) is formed on the side wall and the bottom of the deep silicon structure to protect the side wall of the deep silicon structure. And in the etching step, introducing etching gas into the process chamber, etching the polymer layer and part of the substrate layer at the bottom of the deep silicon structure by the etching gas in a longitudinal direction, and etching the side wall of the deep silicon structure by the transverse etching. And alternately carrying out the deposition step and the etching step, and forming the deep silicon structure through multiple times of cyclic etching. In the deep silicon etching process, along with the increase of the etching depth, the etching efficiency of etching gas and the deposition efficiency of deposition gas are changed differently, so that the size difference between the middle part and the lower part of a deep silicon structure formed by etching is larger.
Disclosure of Invention
The technical problem to be solved by the embodiment of the invention is that the size difference between the middle part and the lower part of the deep silicon structure is large.
In order to solve the above problems, an embodiment of the present invention discloses a deep silicon etching method, including: acquiring initial parameter values and final parameter values of target process parameters in a plurality of process parameters and real-time parameter values of other process parameters except the target process parameters; the target process parameters comprise deposition process parameters and/or etching process parameters in the multiple process parameters;
determining real-time parameter values of the target process parameters corresponding to the etching times of the etching area; the real-time parameter value of the target process parameter is changed along with the increase of the etching times from the initial parameter value to the final parameter value according to an S-shaped curve, so that the etching strength of the etching area is increased along with the increase of the etching times;
controlling a process chamber to carry out deposition passivation on the etching region by adopting the real-time parameter value of the deposition process parameter in the plurality of process parameters, and controlling the process chamber to etch the etching region by adopting the real-time parameter value of the etching process parameter in the plurality of process parameters;
updating the etching times after etching the etching area each time;
and under the condition that the updated etching times do not reach the total etching times, repeating the steps of determining the real-time parameter values of the target process parameters and the steps of depositing, passivating and etching the etching area until the etching times reach the total etching times.
The embodiment of the invention discloses semiconductor process equipment which comprises a controller, wherein the controller is configured to execute the deep silicon etching method.
Compared with the background art, the invention has the following advantages: acquiring initial parameter values and final parameter values of target process parameters in the multiple process parameters and real-time parameter values of other process parameters except the target process parameters, determining the real-time parameter values of the target process parameters corresponding to the etching times of the etching area, controlling the process chamber to perform deposition passivation on the etching area by adopting the real-time parameter values of the deposition process parameters in the multiple process parameters, and the real-time parameter value of the etching process parameter in the multiple process parameters is adopted to control the process chamber to etch the etching area, after the etching area is etched each time, updating the etching times, repeating the step of determining the real-time parameter value of the target process parameter under the condition that the etching times do not reach the total etching times, and depositing, passivating and etching the etching area until the etching times reach the total etching times. In the deep silicon etching process, parameter values of process parameters change according to an S-shaped curve along with the increase of the etching times, so that the horizontal etching strength of the deep silicon structure at the initial stage and the later stage of etching and the horizontal etching strength of the deep silicon structure at the middle stage of etching can be different, and the size difference between the middle part and the lower part of the deep silicon structure can be reduced.
Drawings
Fig. 1 shows a cross-sectional view of a through-silicon via of the prior art;
FIG. 2 shows a schematic diagram of a scallop structure in the through-silicon via of FIG. 1;
FIG. 3 shows a cross-sectional view of another through-silicon-via of the prior art;
FIG. 4 shows a partial schematic view of the through silicon via of FIG. 3;
FIG. 5 is a flowchart illustrating steps of a deep silicon etching method according to an embodiment;
FIG. 6 shows a plot of a function of equation three;
fig. 7 is a cross-sectional view of a through-silicon via provided in the present embodiment;
FIG. 8 shows another plot of the function of equation three;
FIG. 9 is a graph of a function of equation four;
fig. 10 is a cross-sectional view showing another through-silicon via provided by the present embodiment;
FIG. 11 shows a schematic diagram of a scallop structure in the through-silicon via of FIG. 10;
FIG. 12 shows another plot of the function of equation four;
FIG. 13 is a schematic flow chart illustrating a deep silicon etching method according to the present embodiment;
fig. 14 is a cross-sectional view showing another through-silicon-via in the prior art;
FIG. 15 is a graph showing a function corresponding to equation thirteen;
fig. 16 shows a function graph corresponding to equation thirteen.
Detailed Description
In order to facilitate understanding of the present invention, a deep silicon etching process is briefly described by taking a through silicon via as an example. As shown in fig. 1 and fig. 2, fig. 1 shows a cross-sectional view of a through-silicon via in the prior art, fig. 2 shows a schematic view of a fan-shell structure in the through-silicon via in fig. 1, and deep silicon etching is mainly performed by a dry etching process, also called Bosch (Bosch) process, by a method of alternately and cyclically performing deposition steps and etching steps to form the through-silicon via 101 shown in fig. 1. In the etching process, the etching gas can transversely etch the side wall of the through silicon via to form a scallop structure on the side wall, the difficulty of the etching gas and the deposition gas entering the through silicon via is gradually increased along with the increase of the etching depth, but the etching efficiency of the etching gas and the deposition efficiency of the deposition gas can be changed differently along with the increase of the etching depth because the etching gas and the deposition gas are two gases with different properties. In some cases, in the early stage of etching, that is, when etching the upper portion of the tsv, the deposition efficiency of the deposition gas is low at each deposition, the etching efficiency of the etching gas is high at each etching, the lateral etching strength on the sidewall is high, and a scallop structure with a large size is formed, and the scallop structure in the rectangular frame 1011 is the scallop structure on the upper portion of the tsv 101, and the size is about 40 nanometers (nm). In the middle stage of etching, when the middle part of the through silicon via is etched immediately, the etching efficiency of the etching gas is low, the deposition efficiency of the deposition gas is high, the lateral etching strength of the side wall is low, a scallop structure with a small size is formed, and the scallop structure in the rectangular frame 1012 is the scallop structure in the middle part of the through silicon via 101, and the size is about 10 nm. In the later stage of etching, when the lower part of the through silicon via is etched immediately, the etching efficiency of the etching gas is increased again, the deposition efficiency of the deposition gas is reduced again, the lateral etching effect on the side wall is enhanced, the size of the scallop structure is increased again, and the scallop structure in the rectangular frame 1013 is the scallop structure at the lower part of the through silicon via 101 and the size is about 28 nm. In the through silicon via formed by deep silicon etching, the size of the scallop structure at the upper part is the largest, the size of the scallop structure at the middle part is the smallest, the size of the scallop structure at the lower part is positioned between the upper part and the lower part, and the size difference between the scallop structures at the upper part, the middle part and the lower part is larger.
As shown in fig. 3 and 4, fig. 3 shows a cross-sectional view of another through silicon via in the prior art, fig. 4 shows a partial schematic view of the through silicon via in fig. 3, and in some cases, at the initial stage of etching, the deposition gas has high efficiency per deposition, the etching gas has low etching efficiency per etching, the lateral etching strength to the sidewall is small, and the size of the formed through silicon via 301 is small, and a first straight line 401 in fig. 4 is a schematic representation of the size of the upper portion of the through silicon via 301, and the size of the upper portion of the through silicon via is about 3 micrometers (μm). In the middle stage of etching, the etching efficiency of the etching gas is high, the deposition efficiency of the deposition gas is low, the lateral etching strength of the side wall is high, and the size of the through silicon via is increased, wherein the second straight line 402 is a size indication of the middle part of the through silicon via 301, and the size of the middle part of the through silicon via is about 4.5 micrometers. In the later stage of etching, the etching efficiency of the etching gas is reduced, the deposition efficiency of the deposition gas is higher, the strength of lateral etching on the side wall is reduced, and the size of the through silicon via is reduced, and the third straight line 403 is a size indication of the lower part of the through silicon via and has a size of about 1 μm. The sizes of the upper part, the middle part and the lower part of the silicon through hole are inconsistent, so that the bending (bowing) abnormity of the silicon through hole occurs.
In order to solve the above technical problems, embodiments of the present invention provide a deep silicon etching method and semiconductor processing equipment, and the embodiments of the present invention are further described in detail with reference to the drawings and the detailed description.
Referring to fig. 5, fig. 5 is a flowchart illustrating a step of a deep silicon etching method provided in this embodiment, where the method may include:
step 501, obtaining an initial parameter value and a final parameter value of a target process parameter in the plurality of process parameters, and a real-time parameter value of other process parameters except the target process parameter.
The target process parameter comprises a deposition process parameter and/or an etching process parameter in a plurality of process parameters.
In this embodiment, the deep silicon etching method may be implemented by a Controller in the semiconductor processing equipment, such as a Programmable Logic Controller (PLC) and a computer, or other electronic equipment with control capability. The semiconductor processing equipment also comprises a process chamber, wherein the process chamber is used for placing a wafer and carrying out deep silicon etching on the wafer. The process chamber may be connected to a first conduit for supplying a center etch gas or a center deposition gas to a center region of a wafer placed in the process chamber and a second conduit for supplying an edge etch gas or an edge deposition gas, such as octafluorocyclobutane (C), to an edge region of the wafer4F8) Etching gases such as sulfur hexafluoride (SF)6). The deposition gas and the etching gas may also be other types of gases. The bottom of the process chamber may be provided with a lower electrode, also referred to as a bias electrode, the top of the process chamber may be provided with an upper electrode,the upper electrode is also referred to as the source electrode. The upper electrode can enable the deposition gas and the etching gas to form plasma, and the lower electrode can control the plasma to move towards the wafer so as to etch and deposit the wafer. The process chamber may be configured with a vacuum pumping device that may control the chamber pressure within the process chamber. The specific structure of the process chamber may be set according to the requirement, which is not limited in this embodiment.
In one embodiment, a user may pre-edit the etch process recipe and pre-store the edited etch process recipe in a pre-set location in the controller. The etching process formula comprises a plurality of process parameters, and the plurality of process parameters comprise a plurality of etching process parameters corresponding to the etching steps and a plurality of deposition process parameters corresponding to the deposition steps. As shown in table 1, table 1 is an exemplary etch process recipe.
Figure BDA0003447341440000051
TABLE 1
In Table 1, the deposition process parameters include chamber pressure, upper electrode center power, upper electrode edge power, center deposition gas flow and edge deposition gas flow, and the single step time of the deposition step, which may also be referred to as the deposition duration. The etching process parameters include chamber pressure, upper electrode center power, upper electrode edge power, lower electrode power, center etching gas flow, edge etching gas flow, and single step time of the etching step, which may also be referred to as etching duration. In Table 1 mTorr is pressure units mTorr, W is power units Watt, sccm is flow units standard milliliters per minute, and s is time units seconds. The upper electrode center power, the upper electrode edge power, and the lower electrode power are collectively referred to as the rf power of the electrode. In table 1, when there is only one parameter value of a certain process parameter, it means that the parameter value of the process parameter is fixed during the deep silicon etching process, for example, the chamber pressure in the deposition process parameter is always 35 millitorr (mTorr) during the whole deep silicon etching process. When the two parameter values are included, one parameter value is an initial parameter value, the other parameter value is a final parameter value, and the parameter value representing the process parameter is gradually changed from the initial parameter value to the final parameter value along with the increase of the etching times in the deep silicon etching process. In table 1, when the parameter values include two, the parameter value on the left side is the initial parameter value, and the parameter value on the right side is the final parameter value, and taking the single step time of the deposition step as an example, the initial parameter value is 0.6 seconds(s), and the final parameter value is 0.5 s.
Wherein, the real-time parameter value is the parameter value actually used in the process of carrying out the etching step or the deposition step. The target process parameter is a process parameter of which the real-time parameter value changes along with the etching times in the deep silicon etching process, and the target process parameter can comprise one or more etching process parameters and/or one or more deposition process parameters. For example, in table 1, the target process parameters for the deposition step include a single step time, and the target process parameters for the etching step include a lower electrode power and a single step time. In table 1, the real-time parameter values of the other process parameters except the target process parameter are the fixed parameter values shown in table 1. For example, in the deposition step, the real-time parameter value of the central deposition gas flow is 300sccm all the time in the whole deep silicon etching process; in the etching step, the upper electrode center power is 2200W all the time in the whole deep silicon etching process. In the deep silicon etching process, the real-time parameter value corresponding to the etching times can be determined according to the etching times in the etching process.
In practice, the chamber pressure may be no less than 5mTorr and no more than 500mTorr among the process parameters shown in table 1; the power range of the upper electrode is not less than 500W and not more than 5000W, the power range of the lower electrode is not less than 5W and not more than 500W, the flow rate of the central etching gas is not less than 10sccm and not more than 1000sccm, the flow rate of the edge etching gas is not less than 10sccm and not more than 1000sccm, the flow rate of the central deposition gas is not less than 10sccm and not more than 1000sccm, the flow rate of the edge deposition gas is not less than 10sccm and not more than 1000sccm, and the single step time is not less than 0.4 s.
In this embodiment, a user may put a wafer to be etched into a process chamber in advance, after a semiconductor process device is started to perform deep silicon etching on the wafer, the controller may obtain an etching process recipe from a preset position, then read parameter values of other process parameters except for a target process parameter from the etching process recipe, take the read parameter values as real-time parameter values, and read an initial parameter value and a final parameter value of the target process parameter, so as to determine the real-time parameter value of the target process parameter according to the read initial parameter value and the real-time parameter value. The above are merely exemplary examples, and the initial parameter value and the final parameter value of the target process parameter, and the specific obtaining method of the real-time parameter values of the other process parameters may also be obtained by other manners, which is not limited in this embodiment.
Step 502, determining real-time parameter values of target process parameters corresponding to the etching times of the etching area.
The real-time parameter value of the target process parameter increases along with the increase of the etching times, and the real-time parameter value changes from the initial parameter value to the final parameter value according to an S-shaped curve, so that the etching strength of the etching area increases along with the increase of the etching times. The etching area is an area in the wafer, which needs to be subjected to deep silicon etching to form a deep silicon structure. The etching times are corresponding etching times when etching steps are executed each time when etching areas in the wafer are etched for multiple times. In combination with the above example, in the deep silicon etching process, the etching region needs to be etched for multiple times, and the greater the etching times, the greater the depth of the through silicon via. A user can preset the total etching times according to the depth requirement of the silicon through hole, so that whether the depth of the silicon through hole meets the requirement or not is determined according to the total etching times in the etching process, and when the depth of the silicon through hole meets the requirement, the etching of the etching area is finished.
In this embodiment, after obtaining the initial parameter value and the final parameter value of the target process parameter, the controller may first determine the real-time parameter value of the target process parameter corresponding to the current etching time according to the etching time of the etching area at the current time and the initial parameter value and the final parameter value of the target process parameter.
Optionally, the target process parameter includes an etching process parameter of the plurality of process parameters; the S-shaped curve is an increasing curve, the front half part of the S-shaped curve is downward convex, and the rear half part of the S-shaped curve is upward convex. The S-shaped curve is a pure etching strength curve formed based on a plurality of cycles, namely, the theoretical pure etching strength of each cycle under the combined action of deposition and etching without considering the depth effect is different (the difference is offset with the depth effect, so that the actual pure etching strength at different depths is kept unchanged) along with the time. In the specific implementation process, the etching strength of the etching step can be increased gradually according to the S-shaped curve, and the deposition step can be a fixed value, increased or decreased, as long as it is ensured that the pure etching strength curve can be increased gradually according to the S-shaped curve, and how to select the specific deposition step will be described in detail later. Compared with linear increasing in the prior art, the pure etching strength of the invention is lower in the middle stage of pure etching than in the prior art, and is higher in the later stage than in the prior art, namely the pure etching strength of the middle section of the through silicon via is reduced, the pure etching strength of the rear section of the through silicon via is increased, and the problems of small upper and lower apertures and large middle aperture bowing existing in the prior art are solved.
Optionally, in order to increase the etching strength with the increase of the etching times, the target process parameter may be one or more etching process parameters of a plurality of process parameters, the S-shaped curve is an increasing curve, the front half part of the S-shaped curve is downward convex, and the rear half part of the S-shaped curve is upward convex. Taking table 1 as an example, the target process parameters may include etching duration and lower electrode power corresponding to the etching step. The initial parameter value of the etching duration is smaller than the final parameter value, the etching duration is increased along with the increase of the etching times in the etching process, and the larger the etching duration is, the larger the etching strength is. Similarly, the initial parameter value of the lower electrode power is smaller than the final parameter value, the lower electrode power is increased along with the increase of the etching times, and the higher the lower electrode power is, the higher the etching strength is.
For example, a ratio of the etching times at the current time to the total etching times may be used as an independent variable x, and a real-time parameter value corresponding to the etching times may be used as a dependent variable y to construct an S-shaped (Sigmoid) function, where a function curve of the S-shaped function is an S-shaped curve. The symbol N may be used to represent the number of etching at the current time, and the symbol N represents the total number of etching, so that x is N/N, and x has a value range of [0,1 ]. Since the range of the independent variable x in the sigmoid function is [0, ∞), a formula can be used to perform logarithmic transformation on x, and the range of x is mapped to [0, ∞).
Figure BDA0003447341440000081
In the first formula, a natural logarithm ln is used for mapping, and in practical applications, a constant logarithm lg with 10 as a base number or a logarithm with another base number may also be used, which is not limited in this embodiment.
In one embodiment, the sigmoid function may be a Hill function (Hill function), and the formula of the Hill function is: y ═ S + (E-S) xn/(kn+xn) The confusion between the parameter n in the hill function and the etching frequency n is avoided, and the symbol p may be used to replace the symbol n in the hill function, so that the formula of the hill function is as follows: y ═ S + (E-S) xp(kp+xp). Can use the symbol PiInitial parameter value, symbol P, representing a target process parameterjRepresenting the final parameter value of the target process parameter, symbol PijReal-time parameter values representing the target process parameters. Initial parameter value PiAs parameter S, terminal parameter value P in the Hill functionjAs a parameter E in the hill function, a formula two shown below can be obtained:
Pij=Pi+(Pj-Pi)xp/(kp+xp) Formula two
Substituting equation one into equation two results in equation three as follows:
Figure BDA0003447341440000091
illustratively, the target process parameter is an etch time duration. As shown in fig. 6, fig. 6 shows a function graph of formula three, where x is N/N on the abscissa and the real-time parameter value y on the ordinate in fig. 6. Obtaining the initial parameter value P of the target process parameteriAnd a final parameter value PjThen, the controller can determine the etching times of the etching area at the current moment, acquire the total etching times input by the user in advance, and convert the initial parameter value P into the total etching timesiEnd parameter value PjSubstituting the etching times N and the total etching times N into a formula III to calculate a real-time parameter value P corresponding to the etching timesij. The parameter k and the parameter p in the formula three can be set by a user according to the specific requirements of the S-shaped curve in the actual etching process. Taking the etching duration in table 1 as an example, before etching is started, the etching frequency is set to be 0, when an etching area in a wafer is etched for the first time, the etching duration is an initial parameter value of 1.2s, in the deep silicon etching process, every time an etching step is performed, the etching frequency is increased by 1 to obtain a new etching frequency, then the new etching frequency and the total etching frequency are substituted into a formula three, the etching duration corresponding to the new etching frequency can be calculated, and then the deep silicon etching is continuously performed by adopting the new etching duration. With the increase of the etching times, the etching duration is increased according to the S-shaped curve shown in fig. 6, when the etching times reach the total etching times, N/N is 1, and the etching duration is the final parameter value of 1.6S.
As shown in fig. 6, when the target process parameter is the etching duration, the first half of the S-shaped curve is convex downward, and the second half of the S-shaped curve is convex upward, where the first half is a part of the S-shaped curve away from the maximum ratio between the etching times and the total etching times, and the second half is a part of the S-shaped curve close to the maximum ratio between the etching times and the total etching times. In the whole deep silicon etching process, the etching time is increased gradually, and the etching strength is increased gradually. Meanwhile, the front half part of the S-shaped curve protrudes downwards, the rear half part protrudes upwards, so that the etching time in the middle etching period is shorter than the etching time corresponding to linear incremental increase in the prior art, the etching time is increased to a larger value quickly, the etching time in the later etching period is longer than the etching time corresponding to linear incremental increase in the prior art, the etching time is increased to a final parameter value slowly from the larger value, and the etching is continuously carried out with a larger etching time in the later etching period, so that the transverse etching strength in the later etching period can be increased, the size of the through silicon via in the later etching period can be increased, and the size difference between the middle part and the lower part of the through silicon via can be reduced. As shown in fig. 7, fig. 7 shows a cross-sectional view of a through silicon via provided in this embodiment, when the etching process parameters are controlled to increase with the etching times and change according to an S-shaped curve, if the front half part of the S-shaped curve protrudes downward and the rear half part protrudes upward, the through silicon via 701 shown in fig. 7 can be formed, and the size difference between the middle part and the lower part of the through silicon via is small.
When the target process parameters comprise etching process parameters in the multiple process parameters, the S-shaped curve is an increasing curve, the front half part of the S-shaped curve is downward convex, and the rear half part of the S-shaped curve is upward convex, the deposition process parameters in the multiple process parameters can be kept unchanged.
Optionally, the target process parameter further includes a deposition process parameter of the plurality of process parameters. And under the condition that the target process parameter is a deposition process parameter in the multiple process parameters, if the S-shaped curve is a decreasing curve, the front half part of the S-shaped curve is upwards convex, and the rear half part of the S-shaped curve is downwards convex.
For example, in order to increase the etching strength of the etching region with the increase of the etching times, the target process parameter may be one or more deposition process parameters among a plurality of process parameters, the S-shaped curve is a decreasing curve, and the front half part of the S-shaped curve is upward convex and the rear half part is downward convex. Taking table 1 as an example, the target process parameter may include a deposition duration corresponding to the deposition step. The initial parameter value of the deposition time is larger than the final parameter value, the smaller the deposition time is in the deep silicon etching process, the smaller the thickness of the polymer layer formed in the etching area is when the deposition step is executed each time, the smaller the thickness of the polymer layer is, the lower the passivation protection effect is, the greater the etching can be performed on the wafer in the etching step after the deposition step, and the etching strength can be increased. As shown in fig. 8, fig. 8 shows another function graph of equation three, when the target process parameter is the deposition duration corresponding to the deposition step, the initial parameter value is greater than the final parameter value, and the graph of the function shown in equation three is the decreasing graph shown in fig. 8. In fig. 8, the abscissa is the ratio of the etching times to the total etching times at the current moment, and as the etching times increase, the deposition duration decreases, and the thickness of the formed polymer layer decreases, so that the etching strength of the etching step corresponding to each deposition step can be increased. In addition, in fig. 8, the front half part of the S-shaped curve is upward convex, and the rear half part is downward convex, and since the deposition duration is rapidly reduced to a lower value from the middle stage of etching, the etching can be performed at a higher etching strength in the later stage of etching, so that the transverse etching strength in the later stage of etching can be increased, the size of the through silicon via in the later stage of etching can be increased, and the size difference between the middle part and the lower part of the through silicon via can be reduced. Taking the deposition duration in table 1 as an example, before etching is started, the etching frequency is set to be 0, when an etching area in a wafer is deposited for the first time, the deposition duration is an initial parameter value of 0.6s, in the deep silicon etching process, every time an etching step is performed, the etching frequency is increased by 1 to obtain a new etching frequency, then the new etching frequency is substituted into a formula three, the deposition duration corresponding to the new etching frequency can be obtained by calculation, and the deep silicon etching is continued by adopting the new deposition duration. With the increase of the etching times, the deposition time length is decreased according to the S-shaped curve shown in FIG. 8, when the etching times reach the total etching times, N/N is 1, and the etching time length is the final parameter value of 0.5S.
Optionally, the target process parameter further includes a deposition process parameter of the plurality of process parameters. And under the condition that the target process parameter is a deposition process parameter in the multiple process parameters, if the S-shaped curve is an increasing curve, the front half part of the S-shaped curve is upwards convex, and the rear half part of the S-shaped curve is downwards convex.
In an embodiment, when the target process parameters include both the etching process parameters and the deposition process parameters, the S-shaped curve corresponding to the etching process parameters may be an increasing curve as shown in fig. 6, and the S-shaped curve corresponding to the deposition process parameters may also be an increasing S-shaped curve, where a front half of the S-shaped curve is upward and a rear half thereof is downward. For example, the inverse function of the Sigmoid function may be constructed by using the ratio of the etching times of the deposition process parameters to the total etching times as an independent variable x and using the real-time parameter value as a dependent variable y, so as to obtain a corresponding Sigmoid curve. Taking the hill function as an example, combining formula two and formula three, the inverse function of the hill function is y ═ k [ (E-S)/(x-S) -1]l/pValue range of independent variable xIs [ S, E]The value range of the dependent variable y is [0, ∞ ]. Making correspondent value conversion, making S be 0 and E be N, making x be value range of [0, N]And converting y into exponent y ═ exp (-1/y) so that y has value range of [0, 1%]Then, linear transformation is carried out to make y ═ S + (E-S) y to make its value range be [ S, E]Let S be Pi,E=PjThe following formula four can be obtained:
Figure BDA0003447341440000111
as shown in fig. 9, fig. 9 shows a function curve of the formula four, when the target process parameter is deposition time, and when the real-time parameter value corresponding to the etching times is determined, the etching times can be substituted into the formula four to obtain the real-time parameter value of the deposition time. The variation curve of the deposition time during the whole etching process is an S-shaped increasing curve as shown in FIG. 9. In the deep silicon etching process, the deposition time is slowly increased in the middle etching period, and the deposition time is rapidly increased to a final parameter value in a short time in the later etching period. In the later stage of etching, the deposition time can be maintained at a lower value for a longer time, so that the transverse etching strength in the later stage of etching can be maintained at a higher strength for a longer time, the size of the through silicon via in the later stage of etching can be increased, and the size difference between the middle part and the lower part of the through silicon via is reduced. The parameter p and the parameter k in the formula four may be set by a user according to actual requirements, which is not limited in this embodiment.
In practical application, when the target process parameters simultaneously include the etching process parameters and the deposition process parameters, and the etching process parameters and the deposition process parameters are increased gradually according to the S-shaped curve, the increase range of the etching process can be larger than that of the deposition process, so that the etching efficiency in the whole etching process can be increased.
Optionally, the target process parameter includes an etching process parameter of the plurality of process parameters; the S-shaped curve is an increasing curve, the front half part of the S-shaped curve is upwards convex, and the rear half part of the S-shaped curve is downwards convex. Wherein, an etching step and a deposition step form a cycle, the S-shaped curve is a pure etching strength curve formed based on a plurality of cycles, namely, as time goes on, the pure etching strength of each cycle under the combined action of deposition and etching without considering the depth effect temporarily has a difference (the difference is offset with the depth effect, thereby keeping the actual pure etching strength at different depths unchanged). In the specific implementation process, the etching strength of the etching step can be increased gradually according to the S-shaped curve, and the deposition step can be a fixed value, increased or decreased, as long as it is ensured that the pure etching strength curve can be increased gradually according to the S-shaped curve, and how to select the specific deposition step will be described in detail later. Compared with the linear increasing in the prior art, the pure etching strength of the invention is higher in the middle stage of pure etching than that of the prior art, and is lower in the later stage than that of the prior art, namely, the pure etching strength of the middle section of the through silicon via is improved, the pure etching strength of the rear section of the through silicon via is reduced, and the problems of large size of upper and lower scallops and small size of middle scallop in the prior art are solved.
In one embodiment, when the target process parameter is an etching process parameter and the etching process parameter is increased gradually according to an S-shaped curve during the whole deep silicon etching process, the first half part of the S-shaped curve may be convex upward and the second half part may be convex downward. Taking the etching duration as an example, the etching duration can be gradually increased along with the increase of the etching times in the whole deep silicon etching process according to the S-shaped curve shown in fig. 9. Similarly, the inverse function of the hill function can be used to construct a sigmoidal curve with respect to the duration of the etch as shown in fig. 9. In the whole deep silicon etching process, with the increase of the etching times, the etching duration is gradually increased according to the S-shaped curve shown in FIG. 9, and the etching efficiency is gradually increased. In the whole deep silicon etching process, the etching time in the middle etching period is longer than the etching time corresponding to linear incremental increase in the prior art and is slowly increased, so that the transverse etching strength in the middle etching period is slowly increased, the etching time in the later etching period is shorter than the etching time corresponding to linear incremental increase in the prior art and is quickly increased in a short time, so that the transverse etching strength in the later etching period is quickly increased in a short time, the transverse etching strength in the later etching period can maintain lower strength in a longer time, and the scallop size in the later etching period can be reduced. As shown in fig. 10 and 11, fig. 10 shows a cross-sectional view of a through-silicon via provided in this embodiment, fig. 11 shows a schematic diagram of a scallop structure in the through-silicon via in fig. 10, when a control target process parameter increases with the number of times of etching and changes according to an S-shaped curve, the through-silicon via 100 shown in fig. 10 can be formed by etching, the scallop structure in the rectangular frame 1001 in fig. 11 is the scallop structure on the upper portion of the through-silicon via 100, the size is about 13 nm, the scallop structure in the rectangular frame 1003 is the scallop structure on the lower portion of the through-silicon via 100, the size is about 10nm, the scallop structure in the rectangular frame 1002 is the scallop structure in the middle portion of the through-silicon via 100, and the size is about 9 nm. As can be seen from fig. 1 and 2, the present embodiment can reduce the size difference of the scallop structure between the middle portion and the lower portion of the through-silicon-via.
Optionally, the target process parameter further includes a deposition process parameter of the plurality of process parameters; and under the condition that the target process parameter is a deposition process parameter in the multiple process parameters, if the S-shaped curve is a decreasing curve, the front half part of the S-shaped curve is downward convex, and the rear half part of the S-shaped curve is upward convex.
In one embodiment, in order to solve the problem of the large difference in the sizes of the middle and lower portions of the scallop structure, the target process parameters may include both the etching process parameters and the deposition process parameters. As shown in fig. 12, fig. 12 shows another function graph of equation four, and taking the deposition time as an example, an S-shaped curve of the deposition time may be constructed by using equation four, where a ratio of the etching times of the deposition time to the total etching times is used as an independent variable x, and a real-time parameter value is used as a dependent variable y, and since an initial parameter value of the deposition time is greater than a final parameter value, the S-shaped curve is a decreasing curve as shown in fig. 12. As shown in fig. 12, since the deposition time is decreased as the number of etching times is increased during the whole deep silicon etching process, the deposition efficiency is decreased and the corresponding etching efficiency is increased. In addition, in the later stage of etching, the deposition time is quickly reduced, so that the deposition efficiency is quickly reduced, the opposite transverse etching strength is quickly reduced to a small value, the transverse etching strength in the later stage of etching can be kept at a low strength for a long time, and the size of the scallop in the later stage of the whole etching can be reduced.
Optionally, in a case that the target process parameter is a deposition process parameter of the plurality of process parameters, if the S-shaped curve is an increasing curve, a front half portion of the S-shaped curve is convex downward, and a rear half portion of the S-shaped curve is convex upward.
In an embodiment, when the target process parameter includes both the etching process parameter and the deposition process parameter, the S-shaped curve corresponding to the etching process parameter may be an increasing curve as shown in fig. 9, and the S-shaped curve corresponding to the deposition process parameter may be an increasing curve as shown in fig. 6, a front half portion of the S-shaped curve is downward convex, and a rear half portion of the S-shaped curve is upward convex. Taking the deposition time as an example, an S-shaped curve of the deposition time may be constructed by using the formula three, where a ratio of the etching times to the total etching times of the deposition time is used as an independent variable x, and a real-time parameter value is used as a dependent variable y, and since an initial parameter value of the deposition time is smaller than a final parameter value, the S-shaped curve is an increasing curve as shown in fig. 6. As shown in fig. 6, in the whole deep silicon etching process, in the later stage of etching, the deposition time is slowly increased, so that the deposition efficiency is slowly increased, and conversely, the etching efficiency in the later stage of etching can be slowly increased, so that the lateral etching strength in the later stage of etching can be maintained at a lower strength for a longer time, and the scallop size in the later stage of the whole etching can be reduced.
When the target process parameter comprises an etching process parameter in a plurality of process parameters; the S-shaped curve is an increasing curve, when the front half part of the S-shaped curve is upwards convex and the rear half part is downwards convex, the deposition process parameters in the multiple process parameters can be kept unchanged.
In practical application, when the target process parameters simultaneously include the etching process parameters and the deposition process parameters, and the etching process parameters and the deposition process parameters are increased gradually according to the S-shaped curve, the increase range of the etching process can be larger than that of the deposition process, so that the etching efficiency in the whole etching process can be increased.
Step 503, controlling the process chamber to perform deposition passivation on the etching region by using the real-time parameter value of the deposition process parameter in the plurality of process parameters, and controlling the process chamber to perform etching on the etching region by using the real-time parameter value of the etching process parameter in the plurality of process parameters.
In this embodiment, after the real-time parameter values of the target process parameters and the real-time parameter values of other process parameters except the target process parameters are obtained, the process chamber may be controlled to etch the etching region of the wafer according to the real-time parameter values of the plurality of process parameters, each etching process includes one deposition step and one etching step, and one deposition passivation and one etching are performed on the etching region. With reference to the above example, when the etching region is etched for the first time, the real-time parameter value of the target process parameter is the initial parameter value, and the real-time parameter values of the process parameters other than the target process parameter are the fixed parameter values shown in table 1. During the first etching, the controller can control the action of the vacuum-pumping device to stabilize the pressure of the process chamber at 35 mTorr, the central power of the upper electrode is 2200 watts (W), the edge power of the upper electrode is 600W, the power of the lower electrode is 0, the first pipeline and the second pipeline are simultaneously controlled to be opened, the gas flow of the first pipeline is controlled to be 300sccm, the gas flow of the second pipeline is controlled to be 50sccm, and the deposition gas C is introduced into the process chamber4F8. The single step time of the deposition step is 0.6s and lasts for 0.6s, deposition passivation is carried out on the etching area, and a polymer layer is formed in the etching area. When the deposition time reaches 0.6s, finishing the deposition step, switching to the etching step, firstly closing the first pipeline and the second pipeline, then controlling the lower electrode power to be 180W, then opening the first pipeline and the second pipeline again, controlling the gas flow of the first pipeline to be 300sccm and the gas flow of the second pipeline to be 150sccm, and introducing etching gas SF into the process chamber6And etching the etching area for 1.2 s. And when the etching time reaches 1.2s, ending the etching step and finishing the primary etching of the etching area. And in the second etching process, the real-time parameter value of the target process parameter is determined again according to the updated etching times, the real-time parameter values of other process parameters except the target process parameter are kept unchanged, and the etching area is repeatedly etched.
Optionally, the wafer may include a silicon substrate layer, and a mask layer located over the substrate layer. Before deep silicon etching is performed on the wafer, the mask layer covering the etching area can be etched first to etch away the mask layer in the etching area and expose the etching window. In the deep silicon etching process, the etching region can be subjected to deep silicon etching through the etching window to form a deep silicon structure. The specific method for etching the mask layer may be set according to the requirement, and this embodiment is not limited thereto.
Step 504, after etching the etching area each time, updating the etching times.
And 505, under the condition that the etching times do not reach the total etching times, repeating the steps of determining the real-time parameter values of the target process parameters and the steps of depositing, passivating and etching the etching area until the etching times reach the total etching times.
In one embodiment, after completing one etching of the etching region, the controller may first add 1 to the etching times to complete the updating of the etching times. And under the condition that the updated etching times do not reach the total etching times, repeating the steps 502 to 504, and circularly etching the etching area. In the process of repeatedly performing steps 502 to 504, after the etching times are updated each time, a real-time parameter value of the target process parameter corresponding to the etching times at the current time is determined according to the initial parameter value and the final parameter value of the target process parameter and the updated etching times at the current time, and then step 503 is performed according to the re-determined real-time parameter value of the target process parameter to perform deposition passivation and etching on the etching area. After each step 504, if the updated etching times reach the total etching times, it is determined that the etching depth meets the requirement, the process chamber is stopped, and the etching is finished.
In another embodiment, after completing one etching of the etching region, the controller may first determine whether the etching frequency at the current time reaches the total etching frequency, and if the etching frequency reaches the total etching frequency, determine that the etching depth meets the requirement, and stop the process chamber. On the contrary, if the etching times at the current moment do not reach the total etching times, determining that the etching depth does not reach the requirement, updating the etching times at the current moment, and then repeatedly executing the step 502 and the step 503 according to the updated etching times to perform circular etching on the etching area. As shown in fig. 13, fig. 13 shows a schematic flow chart of the deep silicon etching method provided in this embodiment, after the deep silicon etching on a wafer is started, a controller may first obtain an initial parameter value and a final parameter value of each target process parameter in table 1, and a real-time parameter value of another process parameter except the target process parameter, and obtain a total number of etching times preset by a user, and at the same time, may set the number of etching times to be 0, where a symbol N in fig. 13 represents the number of etching times, and a symbol N represents the total number of etching times. During the first etching, the initial parameter value of the target process parameter can be directly used as a real-time parameter value, the deposition step and the etching step are executed, and deposition passivation and etching are carried out on the etching area. After the first etching is finished, whether the etching times are equal to the total etching times is judged. And under the condition that the etching times are less than the total etching times, adding 1 to the etching times, determining a real-time parameter value of the target process parameter corresponding to the etching times at the current moment according to an initial parameter value and a final parameter value of the target process parameter, and sequentially executing a deposition step and an etching step according to the real-time parameter value of each process parameter. And repeating the process, determining that the etching depth meets the requirement under the condition that the etching times reach the total etching times, stopping the process chamber, and ending the etching.
It should be noted that, in the process of setting the total etching times, a user may set the total etching times according to the requirement of the etching depth and the specific etching process. For example, if it is determined that 1000 times of etching needs to be performed on the etching region according to the etching depth, the controller sets the etching frequency to be 0 before etching, and updates the etching frequency after the etching step is performed, and then determines whether the updated etching frequency reaches the total etching frequency, the total etching frequency may be set to be 1000 times, so as to finish etching after 1000 times of etching is performed on the etching region during the etching process. If the controller sets the etching frequency to be 0 before etching, after the controller executes the etching step, the controller firstly judges whether the etching frequency reaches the total etching frequency, and then updates the etching frequency, and the total etching frequency can be set to be 999, so that the etching is finished after the 1000 th etching is finished in the etching process.
As shown in table 1, the etching process parameters may include any one or more of an etching duration when etching the etching region each time, a flow rate of an etching gas introduced into the process chamber, and a radio frequency power of an electrode disposed in the process chamber. The deposition process parameters include any one or more of a deposition duration when depositing the etching region each time, a flow rate of a deposition gas introduced into the process chamber, and a radio frequency power of an electrode provided in the process chamber.
To sum up, in the embodiment of the present invention, the initial parameter value and the final parameter value of the target process parameter in the plurality of process parameters and the real-time parameter values of other process parameters except the target process parameter are obtained, the real-time parameter value of the target process parameter corresponding to the etching frequency of the etching region is determined, the real-time parameter value of the deposition process parameter in the plurality of process parameters is used to control the process chamber to perform deposition passivation on the etching region, the real-time parameter value of the etching process parameter in the plurality of process parameters is used to control the process chamber to perform etching on the etching region, the etching frequency is updated after each etching of the etching region, the step of determining the real-time parameter value of the target process parameter and the steps of performing deposition passivation and etching on the etching region are repeated when the etching frequency does not reach the total etching frequency, until the etching times reach the total etching times. In the deep silicon etching process, parameter values of process parameters change according to an S-shaped curve along with the increase of the etching times, so that the horizontal etching strength of the deep silicon structure at the initial stage and the later stage of etching and the horizontal etching strength of the deep silicon structure at the middle stage of etching can be different, and the size difference between the middle part and the lower part of the deep silicon structure can be reduced.
As shown in fig. 14, fig. 14 is a cross-sectional view of another through-silicon via in the prior art, in which deep silicon etching is usually performed by using a step-by-step etching method, and different process parameters are used in different steps. In fig. 14, the first etching section 1401, the second etching section 1402 and the third etching section 1403 are etched by using different process parameters, so that a transition position between the first etching section 1401 and the second etching section 1402 has a large error, and the first etching section 1401 and the second etching section 1402 cannot be smoothly connected. In the embodiment, as the parameter value of the target process parameter changes along with the etching times according to the S curve, the formation of a deep silicon structure by etching in a segmented etching mode can be avoided, and the problem that the etching sections cannot be smoothly connected can be solved.
In one embodiment, the sigmoid function may be a logic function (Logistic function), and the formula of the logic function is: y is A2+(A1-A2)/(1+(x/xo)p). Similarly, for a target process parameter, the initial parameter value P is setiAs a parameter A in a logic function2Final value of the parameter PjAs a parameter A in a logic function1Substituting the independent variable x in the formula one into the formula of the logic function can obtain a formula five shown as follows:
Figure BDA0003447341440000171
wherein, the parameter x in the formula five0And the parameter p can be set by a user according to the specific requirements of the S-shaped curve in the actual etching process. Similarly, when the target process parameter is the etching process parameter, the function curve corresponding to the formula five is the increasing curve shown in fig. 6, and when the target process parameter is the deposition process number, the function curve corresponding to the formula five is the decreasing curve shown in fig. 8.
In one embodiment, an inverse of the logistic function may be used to construct an incremental curve corresponding to a certain process parameter, such as that shown in FIG. 9. The inverse of the logic function is: y is x0[(A1-A2)/(x-A2)-1]1/pReferring to the transformation of the hill function, equation six can be obtained as follows:
Figure BDA0003447341440000181
in another embodiment, the sigmoid function may be a Boltzmann function (Boltzmann function) having the formula: y is A2+(A1-A2)/(1+exp(x-x0And/d)). Similarly, for a target process parameter, the initial parameter value P is setiAs a parameter A in the Boltzmann function2Final value of the parameter PjParameter A as Boltzmann function1Substituting x in the formula one into the formula of boltzmann function can obtain the following formula seven:
Figure BDA0003447341440000182
wherein, the parameter x in the formula seven0And the parameter d can be set by a user according to the specific requirements of the S-shaped curve in the actual etching process. Similarly, when the target process parameter is the etching process parameter, the function curve corresponding to the formula vi is the increasing curve shown in fig. 6, and when the target process parameter is the deposition process parameter, the function curve corresponding to the formula vi is the decreasing curve shown in fig. 8.
In one embodiment, the inverse of the Boltzmann function may be used to construct an incremental curve corresponding to a certain process parameter, such as that shown in FIG. 9. The inverse of the boltzmann function is: y ═ ln [ (A)1-A2)/(x-A2)-1]+x0With reference to the transformation of the hill function,/d, equation eight can be obtained as follows:
Figure BDA0003447341440000183
in one embodiment, the sigmoid function may be a growth curve function (S Gompertz function) formulated as: y ═ a × exp (-exp (-k (x-x)c))). Aiming at a certain target process parameter, the final parameter value P isjWith the initial parameter value PiDifference between as a function of growth curveAnd the initial parameter value PiAdding the constant term to the growth curve function, substituting x in the formula one can obtain the formula nine shown as follows:
Figure BDA0003447341440000191
wherein, the parameter x in the formula ninecAnd the parameter k can be set by a user according to the specific requirements of the S-shaped curve in the actual etching process. For example, the parameter k may be set to 1 and the parameter xcMay be set to one-half of the total number N of etches. Similarly, when the target process parameter is the etching process parameter, the function curve corresponding to the formula nine is the increasing curve shown in fig. 6, and when the target process parameter is the deposition process number, the function curve corresponding to the formula nine is the decreasing curve shown in fig. 8.
In one embodiment, the inverse of the growth curve function may be used to construct an incremental curve corresponding to a certain process parameter, as shown in FIG. 9. The inverse of the growth curve function is: y is-k-1ln[ln a-ln x]+xcThe value range of the independent variable x is [0, a ]]The value range of the dependent variable y is [0, ∞), corresponding value conversion is carried out, a is equal to N, so that the value range of x is [0, N ∞)]And converting y into exponent y ═ exp (-1/y) to make its value range be [0,1]Then, linear transformation is performed to obtain y ═ Pi+(Pj-Pi) y is such that it takes on a value in the range [ Pi,Pj]The equation ten shown below can be obtained:
Figure BDA0003447341440000192
as shown in fig. 9, k in the formula ten may be 1, xcRepresenting the point at which the slope rises least, e.g. xcMay be one-half of the total number of etches.
In another embodiment, the S-type function may adopt an S logic 1 function, and the formula of the function is: y is a/(1+ exp (-k (x-x))c))). For a certainThe final parameter value P of each target process parameterjWith the initial parameter value PiThe difference between the two is used as a parameter a in the function, and the initial parameter value P is used asiAdding the function as an addition constant term, substituting x in formula one can obtain formula eleven as follows:
Figure BDA0003447341440000201
wherein, the parameter x in the formula elevencAnd the parameter k can be set by a user according to the specific requirements of the S-shaped curve in the actual etching process. For example, the parameter k may be set to 1 and the parameter xcMay be set to one-half of the total number N of etches. Similarly, when the target process parameter is the etching process parameter, the function curve corresponding to the formula eleven is the increasing curve shown in fig. 6, and when the target process parameter is the deposition process number, the function curve corresponding to the formula eleven is the decreasing curve shown in fig. 8.
In one embodiment, an increasing curve corresponding to a certain process parameter, as shown in FIG. 9, may be constructed using the inverse of the growth S Logistic 1 function. The inverse of the growth curve function is: y ═ k-1ln[a/x-1]+xcThrough similar transformations as in the above example, the equation twelve as shown below can be obtained:
Figure BDA0003447341440000202
the above is merely an exemplary example, the S-type function may also be a Dose Resp function, a S Richards function, and a S Weibull function, and the specific form of the S-type function may be set according to requirements, which is not limited in this embodiment.
In an embodiment, a ratio of the etching times at the current moment to the total etching times may be used as an independent variable x, a real-time parameter value may be used as a dependent variable y, and a piecewise power function with an S-shaped function curve may be constructed. Illustratively, the etching can be performed by taking one half of the total etching times N as a segmentation pointOne-half of the total number of times N may be represented by the symbol NmShowing the number of etching times NmThe corresponding real-time parameter value may be denoted by the symbol PmIt is shown that a piecewise power function as shown in equation thirteen may be constructed.
Figure BDA0003447341440000211
As shown in FIG. 15, FIG. 15 shows a function graph corresponding to equation thirteen, and the parameter m in equation thirteen can be set1Is greater than 1, and sets the parameter m2Is more than 0 and less than 1, when the target process parameter is the etching process parameter, the etching frequency is less than N in the deep silicon etching processmWhen the etching frequency is more than N, the S-shaped curve is convex downwardsmWhen the etching is carried out, the S-shaped curve protrudes upwards, so that the etching strength at the initial stage and the later stage of etching can be increased at a slower speed, and the etching strength at the middle stage of etching can be increased at a faster speed. Wherein the parameter NmAnd a parameter PmThe setting may be manually selected by a user, and the segmentation point may also be other values, which is not limited in this embodiment.
Alternatively, the sigmoid curve may be composed of a plurality of directionally coincident sigmoid curve segments.
In one embodiment, an sigmoid curve having a plurality of sigmoid curve segments may be constructed by a piecewise power function. Combining with the formula thirteen, a plurality of etching times between 0 and the total etching times can be taken as segmentation points to construct a multi-segment power function. By the number of etching times N1、N2And N3For example, 0 < N1<N2<N3< N, number of etching times N1Corresponding real-time parameter value is P1Number of etching times N2Corresponding real-time parameter value is P2Number of etching times N3Corresponding real-time parameter value is P3. A piecewise power function as shown in equation fourteen may be constructed.
Figure BDA0003447341440000212
As shown in FIG. 16, FIG. 16 shows a function curve corresponding to formula fourteen, in which the parameter m1And parameter m4Greater than 1, parameter m2And parameter m3Greater than 0 and less than 1, so that 0 to N can be made1Between curve segments concave curve, make N1To N2Between curve segments convex curve, make N2To N3Convex curve of curve segment between, and3the curve between N and 0 is convex2Form an S-shaped curve segment between the curve segments, and make N2The curve segments from N to N form S-shaped curve segments, so that the whole S-shaped curve is composed of 2S-shaped curve segments. Wherein the parameter N1、N2And N3And a corresponding parameter P1、P2And P3The specific value of (a) may be set manually by a user, and the present embodiment is not limited thereto. And, the user can set the parameter m according to the requirement1、m2、m3And m4The S-shaped curve has different concave-convex characteristics.
It should be noted that the sigmoid curve shown in fig. 16 includes 2 sigmoid curve segments, and the number of the sigmoid curve segments in the sigmoid curve in practical application may be set according to requirements. As shown in the formula fourteen, a plurality of etching times can be selected from the etching times 0 to the total etching times N as segmentation points, and an S-shaped curve function including a plurality of S-shaped curve segments can be constructed.
Figure BDA0003447341440000221
Wherein, in the formula fifteen, mkNot equal to 0, k is 1,2,3, …, control parameter mkCan form a function curve composed of a plurality of S-shaped curve segments.
Alternatively, a piecewise trigonometric function may be used to construct the sigmoid curve.
In one embodiment, the ratio of the etching times at the current moment to the total etching times can be used as an independent variableAnd x, taking the real-time parameter value as a dependent variable y, and constructing a segmented trigonometric function with an S-shaped function curve. Illustratively, the segmentation point may be one-half of the total number of etching times N, which may be denoted by the symbol NmIndicates the number of etching times NmThe corresponding real-time parameter value may be denoted by the symbol PmIt is shown that a piecewise sinusoidal function as shown in equation sixteen can be constructed.
Figure BDA0003447341440000222
As shown in fig. 15, the graph of formula sixteenth is the same as the graph of formula thirteen, and the parameter m in formula sixteenth can be set1Is greater than 1, and sets the parameter m2Is more than 0 and less than 1, when the target process parameter is the etching process parameter, the etching frequency is less than N in the deep silicon etching processmWhen the etching frequency is more than N, the S-shaped curve is convex downwardsmWhen the etching is carried out, the S-shaped curve protrudes upwards, so that the etching strength at the initial stage and the later stage of etching can be increased at a slower speed, and the etching strength at the middle stage of etching can be increased at a faster speed. Wherein the parameter NmAnd a parameter PmThe setting may be manually selected by a user, and the segmentation point may also be other values, which is not limited in this embodiment.
In practical applications, an increasing sigmoid curve corresponding to a certain process parameter, as shown in fig. 9, may also be constructed by the inverse function of the piecewise sinusoidal function shown in formula sixteen. The inverse of the piecewise sinusoidal function shown in equation sixteenth is equation seventeen shown below:
Figure BDA0003447341440000231
in one embodiment, the segment point may be one-half of the total number of etching times N, and one-half of the total number of etching times N may be represented by the symbol NmIndicates the number of etching times NmThe corresponding real-time parameter value may be denoted by the symbol PmExpressing, can construct a formula ofEight segmented cosine functions shown.
Figure BDA0003447341440000232
As shown in fig. 15, the graph of formula eighteen is the same as the graph of formula thirteen, and the parameter m in formula eighteen can be set1Is greater than 1, and sets the parameter m2Is more than 0 and less than 1, when the target process parameter is the etching process parameter, the etching frequency is less than N in the deep silicon etching processmWhen the etching frequency is more than N, the S-shaped curve is convex downwardsmWhen the etching is carried out, the S-shaped curve protrudes upwards, so that the etching strength at the initial stage and the later stage of etching can be increased at a slower speed, and the etching strength at the middle stage of etching can be increased at a faster speed. Wherein the parameter NmAnd a parameter PmThe setting may be manually selected by a user, and the segmentation point may also be other values, which is not limited in this embodiment.
In practical applications, an increasing S-shaped curve as shown in fig. 9 can also be constructed by the inverse function of the piecewise cosine function shown in formula eighteen. The inverse function of the piecewise cosine function shown in equation eighteen is the equation nineteen shown below:
Figure BDA0003447341440000241
in practical application, a plurality of etching times can be selected from the etching times 0 to the total etching times N as segment points, and a segment power function, a segment sine function and a segment cosine function which comprise a plurality of S-shaped curve segments are constructed.
The present embodiment also provides a semiconductor process apparatus comprising a controller configured to perform the deep silicon etching method as described above.
The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
While preferred embodiments of the present invention have been described, additional variations and modifications of these embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the embodiments of the invention.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or mobile device that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or mobile device. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in the process, method, article, or mobile device that comprises the element.
The deep silicon etching method and the semiconductor process equipment provided by the embodiment of the invention are described in detail, specific examples are applied in the description to explain the principle and the implementation mode of the embodiment of the invention, and the description of the embodiment is only used for helping to understand the method and the core idea of the embodiment of the invention; meanwhile, for a person skilled in the art, according to the idea of the embodiment of the present invention, there may be a change in the specific implementation and application scope, and in summary, the content of the present specification should not be construed as a limitation to the embodiment of the present invention.

Claims (13)

1. A deep silicon etching method is used for etching an etching area in a wafer, and the method comprises the following steps:
acquiring initial parameter values and final parameter values of target process parameters in a plurality of process parameters and real-time parameter values of other process parameters except the target process parameters; the target process parameters comprise deposition process parameters and/or etching process parameters in the multiple process parameters;
determining real-time parameter values of the target process parameters corresponding to the etching times of the etching area; the real-time parameter value of the target process parameter is changed according to an S-shaped curve from the initial parameter value to the final parameter value along with the increase of the etching times, so that the etching strength of the etching area is increased along with the increase of the etching times;
controlling a process chamber to carry out deposition passivation on the etching region by adopting the real-time parameter value of the deposition process parameter in the plurality of process parameters, and controlling the process chamber to etch the etching region by adopting the real-time parameter value of the etching process parameter in the plurality of process parameters;
updating the etching times after etching the etching area each time;
and under the condition that the updated etching times do not reach the total etching times, repeating the steps of determining the real-time parameter values of the target process parameters and the steps of depositing, passivating and etching the etching area until the etching times reach the total etching times.
2. The method of claim 1, wherein the target process parameter comprises an etch process parameter of the plurality of process parameters; the S-shaped curve is an increasing curve, the front half part of the S-shaped curve is downward convex, and the rear half part of the S-shaped curve is upward convex.
3. The method of claim 2, wherein the target process parameter further comprises a deposition process parameter of the plurality of process parameters;
under the condition that the target process parameter is a deposition process parameter in the multiple process parameters, if the S-shaped curve is a decreasing curve, the front half part of the S-shaped curve is upward convex, and the rear half part of the S-shaped curve is downward convex;
and under the condition that the target process parameter is a deposition process parameter in the multiple process parameters, if the S-shaped curve is an increasing curve, the front half part of the S-shaped curve is upward convex, and the rear half part of the S-shaped curve is downward convex.
4. The method of claim 1, wherein the target process parameter comprises an etch process parameter of the plurality of process parameters; the S-shaped curve is an increasing curve, the front half part of the S-shaped curve is upward convex, and the rear half part of the S-shaped curve is downward convex.
5. The method of claim 4, wherein the target process parameter further comprises a deposition process parameter of the plurality of process parameters;
under the condition that the target process parameter is a deposition process parameter in the multiple process parameters, if the S-shaped curve is a decreasing curve, the front half part of the S-shaped curve is downward convex, and the rear half part of the S-shaped curve is upward convex;
and under the condition that the target process parameter is a deposition process parameter in the multiple process parameters, if the S-shaped curve is an increasing curve, the front half part of the S-shaped curve is downward convex, and the rear half part of the S-shaped curve is upward convex.
6. The method of claim 2 or 4, wherein a deposition process parameter of the plurality of process parameters is maintained constant.
7. The method of claim 1, wherein the sigmoid curve is comprised of a plurality of directionally consistent sigmoid curve segments.
8. The method of claim 1, wherein the etching process parameters include any one or more of an etching duration, a flow rate of an etching gas introduced into the process chamber, and a radio frequency power of an electrode disposed in the process chamber each time the etching region is etched.
9. The method of claim 1, wherein the deposition process parameters comprise any one or more of a deposition duration for each deposition on the etch region, a flow rate of a deposition gas into the process chamber, and a radio frequency power of an electrode disposed in the process chamber.
10. The method of claim 1, wherein the sigmoid curve is a function curve of a sigmoid function, a ratio of the etching times to the total etching times is an independent variable of the sigmoid function, and the real-time parameter value corresponding to the etching times is a dependent variable of the sigmoid function.
11. The method according to claim 1, wherein the sigmoid curve is a function curve of a piecewise power function, the ratio of the etching times to the total etching times is an independent variable of the piecewise power function, and the real-time parameter value corresponding to the etching times is a dependent variable of the piecewise power function.
12. The method according to claim 1, wherein the sigmoid curve is a function curve of a piecewise trigonometric function, the ratio of the etching times to the total etching times is an independent variable of the piecewise trigonometric function, and the real-time parameter value corresponding to the etching times is a dependent variable of the piecewise trigonometric function.
13. A semiconductor processing tool, comprising a controller configured to perform the method of any one of claims 1-12.
CN202111662968.7A 2021-12-30 Deep silicon etching method and semiconductor process equipment Active CN114446779B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111662968.7A CN114446779B (en) 2021-12-30 Deep silicon etching method and semiconductor process equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111662968.7A CN114446779B (en) 2021-12-30 Deep silicon etching method and semiconductor process equipment

Publications (2)

Publication Number Publication Date
CN114446779A true CN114446779A (en) 2022-05-06
CN114446779B CN114446779B (en) 2024-05-14

Family

ID=

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050287815A1 (en) * 2004-06-29 2005-12-29 Shouliang Lai Method and apparatus for reducing aspect ratio dependent etching in time division multiplexed etch processes
CN104746078A (en) * 2013-12-27 2015-07-01 北京北方微电子基地设备工艺研究中心有限责任公司 A reaction cavity and a plasma processing device
CN105789078A (en) * 2014-12-23 2016-07-20 中国科学院苏州纳米技术与纳米仿生研究所 Measurement method for small-area pattern etching depth
CN110534426A (en) * 2018-09-18 2019-12-03 北京北方华创微电子装备有限公司 Deep silicon etching method, deep silicon slot structure and semiconductor devices
CN110534425A (en) * 2018-09-18 2019-12-03 北京北方华创微电子装备有限公司 Deep silicon etching method, deep silicon slot structure and semiconductor devices

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050287815A1 (en) * 2004-06-29 2005-12-29 Shouliang Lai Method and apparatus for reducing aspect ratio dependent etching in time division multiplexed etch processes
CN104746078A (en) * 2013-12-27 2015-07-01 北京北方微电子基地设备工艺研究中心有限责任公司 A reaction cavity and a plasma processing device
CN105789078A (en) * 2014-12-23 2016-07-20 中国科学院苏州纳米技术与纳米仿生研究所 Measurement method for small-area pattern etching depth
CN110534426A (en) * 2018-09-18 2019-12-03 北京北方华创微电子装备有限公司 Deep silicon etching method, deep silicon slot structure and semiconductor devices
CN110534425A (en) * 2018-09-18 2019-12-03 北京北方华创微电子装备有限公司 Deep silicon etching method, deep silicon slot structure and semiconductor devices

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
吕利;孙建东;李欣幸;秦华;: "硅基单电子晶体管的可控制备", 微纳电子技术, no. 03, 15 March 2013 (2013-03-15) *
张旭;张迪雅;: "梳齿型深硅刻蚀工艺研究", 仪表技术与传感器, no. 02, 15 February 2018 (2018-02-15) *

Similar Documents

Publication Publication Date Title
JP6154820B2 (en) Plasma processing method and plasma processing apparatus
JP7159180B2 (en) Directional control in atomic layer etching
TW201841256A (en) Hydrogen activated atomic layer etching
CN1922722B (en) Reduction of feature critical dimensions
US20040157457A1 (en) Methods of using polymer films to form micro-structures
TWI609423B (en) Etching method for controlling shallow trench depth micro-loading effect
CN107112232A (en) Plasma-etching method
TWI416609B (en) Methods for minimizing mask undercuts and notches for plasma processing system
CN107611128B (en) A kind of three-dimensional computer flash memory device and preparation method thereof and buffering layer manufacturing method thereof
CN103578973B (en) The circulation lithographic method of silicon nitride high depth-to-width ratio hole
CN107591409B (en) The production method of channel structure in a kind of 3D nand flash memory
JP2010245101A (en) Dry etching method
CN105589131A (en) Etching method of silicon chip grooves for optical waveguide
CN103950887A (en) Deep silicon etching method
CN114446779A (en) Deep silicon etching method and semiconductor process equipment
TWI644358B (en) Method of etching
CN114446779B (en) Deep silicon etching method and semiconductor process equipment
CN109390216A (en) A kind of forming method of semiconductor devices
Hoang et al. Feature profile evolution during shallow trench isolation etch in chlorine-based plasmas. I. Feature scale modeling
KR20040070812A (en) Method for forming gate of semiconductor element
CN109326519B (en) Inclination angle silicon groove etching process
CN108573867A (en) Silicon deep hole lithographic method
CN105097494B (en) Lithographic method
Moroz et al. Numerical Simulation of Bosch Processing for Deep Silicon Plasma Etching
TWI759754B (en) Dry etching process for making trench structure of semiconductor device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant