CN114446239B - Display control method, device and system and display equipment - Google Patents

Display control method, device and system and display equipment Download PDF

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Publication number
CN114446239B
CN114446239B CN202210146275.0A CN202210146275A CN114446239B CN 114446239 B CN114446239 B CN 114446239B CN 202210146275 A CN202210146275 A CN 202210146275A CN 114446239 B CN114446239 B CN 114446239B
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signal
driving circuit
display control
transmitting
image data
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CN114446239A (en
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韩新斌
商广良
赵辉
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

The application provides a display control method, a device, a system and display equipment, wherein the display control method comprises the following steps: acquiring image data and a clock signal; generating a driving time sequence signal and a wake-up signal according to the clock signal and the target refresh frequency; and transmitting the image data, the driving time sequence signal and the wake-up signal to the display module, so that the display module refreshes the image data according to the target refresh frequency. The technical scheme of the application can realize the dynamic adjustment of the refresh frequency.

Description

Display control method, device and system and display equipment
Technical Field
The present application relates to display technologies, and in particular, to a display control method, device, system, and display apparatus.
Background
The OLED (Organic Light-Emitting Diode) display technology has different Light Emitting principles from the LCD (Liquid Crystal Display) display technology, and the OLED display technology has advantages of self-luminescence, wide viewing angle, almost infinite contrast, lower power consumption, extremely high response speed, and the like, and has been widely used in mobile display terminal devices.
The OLED notebook display screen in the related art is usually prepared based on an LTPS (Low Temperature Poly-Silicon) backboard technology, and the refresh frequency of the display screen is generally set to be higher than a high refresh frequency of 60Hz (hertz), so that the power consumption is high.
Disclosure of Invention
The embodiment of the application provides a display control method, a device, a system and display equipment, which are used for solving the problems of the related technology, and the technical scheme is as follows:
in a first aspect, an embodiment of the present application provides a display control method, including:
acquiring image data and a clock signal;
generating a driving time sequence signal and a wake-up signal according to the clock signal and the target refresh frequency;
and transmitting the image data, the driving time sequence signal and the wake-up signal to the display module, so that the display module refreshes the image data according to the target refresh frequency.
In a second aspect, an embodiment of the present application provides a display control apparatus, including:
the image processing module is used for acquiring image data;
the time sequence control module is used for acquiring a clock signal and generating a driving time sequence signal according to the clock signal and the target refresh frequency;
the wake-up control module is used for acquiring a clock signal and generating a wake-up signal according to the clock signal and the target refresh frequency;
and the output interface module is used for transmitting the image data, the driving time sequence signal and the wake-up signal to the display module so that the display module refreshes the image data according to the target refresh frequency.
In a third aspect, an embodiment of the present application provides a display control system, including: an image processing unit, a storage unit and a display control device provided by any one of the embodiments of the present application;
the image processing unit and the storage unit are both in communication connection with the display control device;
the image processing unit is used for rendering the image data and transmitting the image data and the clock signal to the display control device;
the storage unit is used for storing configuration parameters of the display control device.
In a fourth aspect, an embodiment of the present application provides a display apparatus, including: the application provides a display module and a display control system provided by any embodiment of the application.
The advantages or beneficial effects in the technical scheme at least comprise:
the technical scheme of the application can generate the driving time sequence signal and the wake-up signal based on the clock signal and the target refresh frequency, and can drive the display module based on the matching of the driving time sequence signal and the wake-up signal, so that the display module can refresh the image data according to the target refresh frequency, thereby realizing the dynamic adjustment of the refresh frequency, and the refresh frequency can be adjusted from high frequency to low frequency so as to reduce the power consumption.
The foregoing summary is for the purpose of the specification only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the present application will become apparent by reference to the drawings and the following detailed description.
Drawings
In the drawings, the same reference numerals refer to the same or similar parts or elements throughout the several views unless otherwise specified. The figures are not necessarily drawn to scale. It is appreciated that these drawings depict only some embodiments according to the disclosure and are not therefore to be considered limiting of its scope.
Fig. 1 is a schematic flow chart of a display control method according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a source driving circuit controlled by a wake-up signal according to an embodiment of the present application;
FIG. 3 is a timing diagram of a low frequency driving display module with a highest refresh rate of 120Hz and a target refresh rate of 24Hz according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a refresh phase and a hold phase at different target refresh frequencies in an embodiment of the present application;
fig. 5 is a schematic structural diagram of a display control device according to an embodiment of the present application;
fig. 6 is a schematic structural frame and a connection diagram of a display control system and a display module according to an embodiment of the present application.
Detailed Description
Hereinafter, only certain exemplary embodiments are briefly described. As will be recognized by those of skill in the pertinent art, the described embodiments may be modified in various different ways without departing from the spirit or scope of the present application. Accordingly, the drawings and description are to be regarded as illustrative in nature and not as restrictive.
The following describes the technical scheme of the present application and how the technical scheme of the present application solves the above technical problems in detail with specific embodiments.
An embodiment of the present application provides a display control method applicable to a display control device, such as TCON (Timer Control Register, timing controller or counter control register), as shown in fig. 1, including:
s101, acquiring image data and a clock signal;
s102, generating a driving time sequence signal and a wake-up signal according to a clock signal and a target refresh frequency;
s103, transmitting the image data, the driving time sequence signal and the wake-up signal to the display module to enable the display module to refresh the image data according to the target refresh frequency.
The display control method provided by the embodiment of the application can generate the driving time sequence signal and the wake-up signal based on the clock signal and the target refresh frequency, and can drive the display module based on the matching of the driving time sequence signal and the wake-up signal, so that the display module can refresh the image data according to the target refresh frequency, thereby realizing the dynamic adjustment of the refresh frequency, and the refresh frequency can be adjusted from high frequency to low frequency so as to reduce the power consumption.
In step S101, the image data and the clock signal may be provided by a GPU (graphics processing unit, image processing unit) at the AP (Application Platform ) end.
The target refresh frequency can be set according to actual requirements, and can be preset frequency or real-time received frequency. When the target refresh frequency is a low refresh frequency (for short, low frequency), for example, a refresh frequency less than 60Hz, the generated driving timing signal is a low frequency driving timing signal, the wake-up signal is a low frequency wake-up signal, and the low frequency driving timing signal and the low frequency wake-up signal can jointly adjust the refresh frequency of the display module to be low frequency. The above manner of distinguishing high frequency from low frequency with 60Hz as the threshold is merely an example, and is not limited to the embodiment of the present application, and in practical application, other frequency values may be used as the thresholds of the high frequency and the low frequency of the region.
Optionally, in step S103, transmitting the image data, the driving timing signal and the wake-up signal to the display module, so that the display module performs refreshing of the image data according to the target refresh frequency, may include: transmitting a driving time sequence signal to a grid driving circuit in the display module, so that the grid driving circuit drives a pixel circuit in the display module under the control of the driving time sequence signal; and transmitting the wake-up signal and the image data to a source electrode driving circuit in the display module, so that the source electrode driving circuit refreshes the image data according to the target refresh frequency under the control of the wake-up signal.
The on-off state of each transistor in the pixel circuit determines whether the effective frame data of the image data output by the source driving circuit can be input into the pixel circuit, so that the refreshing of the image data is realized. The wake-up signal may control the state of the source driving circuit, and thus the refresh frequency of the image data.
Optionally, transmitting the wake-up signal and the image data to a source driving circuit in the display module includes: a wake-up signal is transmitted to the source drive circuit, and image data is transmitted to the source drive circuit in response to a feedback signal returned by the source drive circuit for the wake-up signal.
In one example, after the display control device transmits a wake-up signal to the source drive circuit, the source drive circuit starts to power up (enters an operating state from a sleep state) and returns a feedback signal to the display control device, and the display control device outputs image data to the source drive circuit after receiving the feedback signal, so that the source drive circuit can realize subsequent output, and the display control device does not output the image data after receiving the feedback signal, so as to reduce invalid output.
Optionally, transmitting a wake-up signal to the source driving circuit, transmitting image data to the source driving circuit in response to a feedback signal returned by the source driving circuit for the wake-up signal, including: and transmitting the wake-up signal to the source drive circuit, transmitting the image data to the source drive circuit in a refreshing stage in response to a feedback signal returned by the source drive circuit for the wake-up signal, stopping the transmission of the image data in a holding stage and holding the image data in a state of stopping the transmission currently for a specified period of time.
In the refresh stage, the wake-up signal is a first level, in the hold stage, the wake-up signal is a second level, which may be a high level or a low level, when the first level is a high level, the second level is a low level, and when the first level is a low level, the second level is a high level.
The cooperation of the refresh phase and the hold phase can extend the duration of each frame, thereby enabling the refresh frequency to be switched from high frequency to low frequency.
Fig. 2 is a schematic diagram showing a principle of controlling the source driving circuit by a WAKE-up signal, where VEDIO is a part of frame data in image data, WAKE is a WAKE-up signal, LOCK is a feedback signal, SDIC STATE is a state of the source driving circuit, and DATA STATE is each phase (including a refresh phase and a hold phase) of a display period of the image data. Referring to the example of fig. 2, the first level is high and the second level is low, when the WAKE-up signal WAKE transitions from low to high, the source driver circuit starts to power up, switches from sleep to power up ready, and returns a high feedback signal LOCK to the display control device, and when both WAKE-up signal WAKE and feedback signal LOCK are high, the source driver circuit is powered up ready (its duration is T READY ) When the WAKE signal WAKE jumps from high level to low level, the feedback signal LOCK also jumps to low level, the source driving circuit is switched from working state to dormant state, and the output of the source driving circuit is in high resistance state (Hi-Z).
In practice, there may be a delay in the reception of the feedback signal LOCK with respect to the output of the WAKE-up signal WAKE, e.g. delay T in fig. 2 RELOCK . There may be a delay in the end of the operation state of the source driving circuit with respect to the transition of the WAKE signal WAKE from high to low, e.g. delay T in fig. 2 off 。
It should be noted that fig. 2 illustrates, as an example, only one set of switching procedures of the power-on ready state, the operating state and the sleep state, and in practical application, the switching procedures of the power-on ready state, the operating state and the sleep state may include multiple sets.
Optionally, the specified duration is determined according to a preset refresh frequency and a target refresh frequency. The preset refresh frequency may be the highest refresh frequency allowed by the display module (for example, 120 Hz) or the current refresh frequency, for example, 120Hz, and the target refresh frequency may be any refresh frequency set according to the actual requirement and smaller than the preset refresh frequency, for example, 60Hz, 30Hz, 24Hz, 3Hz, etc.
In one example, the specified duration is calculated as follows:
the above-described manner of determining the specified duration may more accurately adjust the refresh rate to the target refresh rate.
Fig. 3 shows a timing diagram of a display module driven at a low frequency with a highest refresh frequency of 120Hz and a target refresh frequency of 24Hz, where the low frequency driving is implemented in a frequency hopping (Frame skip) manner. The synchronization signal Vsync is refreshed at a frequency of 120Hz, the image data is correspondingly refreshed at a frequency of 120Hz, and the WAKE-up signal WAKE is output at a frequency of 24Hz, forming a plurality of display periods, each including a refresh phase and a hold phase.
Referring to the example of fig. 3, in the refresh stage, the WAKE signal WAKE is at a high level, and the source driving circuit is controllable to be in an operating state, and receives and outputs valid frame data, and the duration of the valid frame data is 1 frame duration (the duration of the 1 st frame in fig. 3) at 120 Hz; in the holding stage, the wake-up signal is low level, the source driving circuit can be controlled to be in a dormant state, the output of effective frame data is stopped, the 4-frame duration (namely, the designated duration is 4-frame duration, and the 2 nd to 5 th frames in fig. 3) under the duration of 120Hz is maintained, so that the duration of one frame can be prolonged from the duration of one frame under the duration of 120Hz to the duration of 5 frames under the duration of 120Hz, the refreshing frequency of the display module can be adjusted to 24Hz, and the overall power consumption of the display module under the low-frequency refreshing state is lower.
Fig. 4 shows a comparative schematic of the refresh phase and the hold phase at different target refresh frequencies, 120Hz in fig. 4 being the highest refresh frequency of the display module, 60Hz, 30Hz and 3Hz being three different target refresh frequencies. Under the condition that the target refresh frequency is 60Hz, the duration of the refresh stage and the duration of the holding stage are both 1 frame duration under 120Hz, and the duration of one display period after adjustment is 2 frame duration under 120 Hz; under the condition that the target refresh frequency is 30Hz, the duration of the refresh stage is 1 frame duration under 120Hz, the duration of the hold stage is 3 frame duration under 120Hz, and the duration of one display period after adjustment is 4 frame duration under 120 Hz; in the case where the target refresh frequency is 3Hz, the refresh period has a duration of 1 frame at 120Hz, the hold period has a duration of 39 frames at 120Hz (only part of which is shown in fig. 4), and the adjusted duration of one display period has a duration of 40 frames at 120 Hz. The duration of the refresh phase and the hold phase may be determined according to the same principle when the target refresh frequency is other.
Optionally, the driving timing signal is transmitted to a gate driving circuit in the display module, so that the gate driving circuit drives the pixel circuit under the control of the driving timing signal, and the method includes: and transmitting a driving time sequence signal to the gate driving circuit to enable the gate driving circuit to start the driving transistor in the pixel circuit in a refreshing stage and to close the driving transistor in the pixel circuit in a holding stage.
The driving time sequence signal is generated based on the target refresh frequency, the driving mode of the grid driving circuit is controlled based on the driving time sequence signal, the driving transistor in the pixel circuit can be opened or closed based on the requirement of the target refresh frequency, and the refreshing of the target refresh frequency can be realized by matching with the output of the source driving circuit under the control of the wake-up signal, so that the dynamic adjustment of the refresh frequency is realized.
The display module in the embodiment of the application can be an OLED display module prepared by adopting an LTPO backboard technology, and the pixel circuit of the display module comprises an oxide transistor, an LTPS transistor and an oxide transistor, so that the characteristics of high LTPS mobility and small cut-off leakage current of the oxide transistor are combined, the flicker phenomenon of the display module under low frequency can be improved, the power consumption of the display module is reduced, and the service life of the display module is prolonged.
For the display module prepared based on LTPO back plate technology, the GATE driving circuit may include a first driving circuit (or gate_n circuit) for driving the oxide transistor in the pixel circuit, and a second driving circuit (or gate_p circuit) for driving the LTPS transistor in the pixel circuit, and the second driving circuit for driving the oxide transistor in the pixel circuit.
Optionally, transmitting a driving timing signal to the gate driving circuit, so that the gate driving circuit turns on the driving transistor in the pixel circuit in the refresh stage and turns off the driving transistor in the pixel circuit in the hold stage, may include: transmitting a first driving time sequence signal to the first driving circuit, enabling the first driving circuit to start an oxide transistor in the pixel circuit in a refreshing stage, starting the driving transistor based on the output of the oxide transistor, and turning off the oxide transistor in a holding stage to turn off the driving transistor; and transmitting a second driving time sequence signal to the second driving circuit, so that the second driving circuit starts the LTPS transistor in the pixel circuit under the control of the second driving time sequence signal with the first level, and closes the LTPS transistor in the pixel circuit under the control of the second driving time sequence signal with the second level.
The oxide transistor with smaller cut-off leakage current is used for controlling the driving transistor and is matched with the wake-up signal to control the source electrode driving circuit, so that the flicker phenomenon caused by large cut-off current in a low-frequency state can be further improved, and the display module can keep a good display effect in the low-frequency state.
Optionally, the first driving timing signal fluctuates during the refresh period based on a preset refresh frequency, and the second level is maintained during the hold period or fluctuates based on a specified frequency; the second driving timing signal fluctuates based on a preset refresh frequency in both the refresh stage and the hold stage. Wherein, the designated frequency can be set according to the actual requirement.
Fig. 3 shows a timing diagram of the first driving timing signal and the second driving timing signal, wherein the CK1 signal and the CB1 signal in fig. 3 are both second driving timing signals for driving LTPS transistors, the CK2 signal and the CB2 signal are both first driving timing signals for driving oxide transistors, the gstv_p signal is a start pulse signal provided to the gate_p circuit, and the gstv_n signal is a start pulse signal provided to the gate_n circuit.
Referring to the example of fig. 3, the gstv_n signal is refreshed at a frequency of 24Hz, and during the refresh period, the CK2 signal and the CB2 signal both fluctuate based on a frequency of 120Hz, and the gate_n circuit turns on or off the oxide transistor, thereby turning on or off the driving transistor, enabling the source driving circuit to write the voltage of the valid frame data, and completing the refresh of the valid frame data; in the hold phase, the CK2 signal and the CB2 signal both hold low, the oxide transistor remains turned off, and the driving transistor is turned off, and the source driving circuit cannot write the voltage of the valid frame data, and the pixel circuit maintains the current voltage state. The gstv_p signal is refreshed at a frequency of 120Hz, and the CK1 signal and the CB1 signal are refreshed at a frequency of 120Hz during both the refresh phase and the hold phase to effect a reset of the drive transistor source or drain voltage.
Based on the same inventive concept, an embodiment of the present application further provides a display control apparatus, as shown in fig. 5, which may include: an image processing module 501, a timing control module 502, a wake-up control module 503, and an output module 504.
The image processing module 501 is configured to acquire image data.
The timing control module 501 is configured to acquire a clock signal and generate a driving timing signal according to the clock signal and a target refresh frequency.
The wake-up control module 503 is configured to obtain the clock signal and generate a wake-up signal according to the clock signal and the target refresh frequency.
The output interface module 504 is configured to transmit the image data, the driving timing signal and the wake-up signal to the display module, so that the display module performs refreshing of the image data according to the target refresh frequency. Wherein the image data may be output in the form of a digital image signal.
The image processing module 501 may include an image processing IP (Intellectual Property ) core, and the timing control module 501 may include a timing control IP core. An IP core refers to a module that designs some functional modules (e.g., filters, interfaces, controllers, etc.) that are commonly used in digital circuits but are relatively complex to modify parameters.
Optionally, the output interface module 504 is specifically configured to: transmitting a driving time sequence signal to a grid driving circuit in the display module, so that the grid driving circuit drives a pixel circuit in the display module under the control of the driving time sequence signal; and transmitting the wake-up signal and the image data to a source electrode driving circuit in the display module, so that the source electrode driving circuit refreshes the image data according to the target refresh frequency under the control of the wake-up signal.
Optionally, the output interface module 504 is specifically configured to: a wake-up signal is transmitted to the source drive circuit, and image data is transmitted to the source drive circuit in response to a feedback signal returned by the source drive circuit for the wake-up signal.
Optionally, when transmitting the wake-up signal to the source driving circuit, and transmitting the image data to the source driving circuit in response to the feedback signal returned by the source driving circuit for the wake-up signal, the output module 504 is specifically configured to: transmitting the wake-up signal to the source driving circuit, transmitting the image data to the source driving circuit in a refresh stage in response to a feedback signal returned by the source driving circuit for the wake-up signal, stopping the transmission of the image data in a hold stage, and holding for a specified period of time in a state where the transmission is currently stopped.
Optionally, the specified duration is determined according to a preset refresh frequency and a target refresh frequency.
Optionally, the driving timing signal is transmitted to the gate driving circuit in the display module, so that when the gate driving circuit drives the pixel circuit under the control of the driving timing signal, the output module 504 is specifically configured to: and transmitting a driving time sequence signal to the gate driving circuit to enable the gate driving circuit to start the driving transistor in the pixel circuit in a refreshing stage and to close the driving transistor in the pixel circuit in a holding stage.
Optionally, when the driving timing signal is transmitted to the gate driving circuit, so that the gate driving circuit turns on the driving transistor in the pixel circuit in the refresh stage and turns off the driving transistor in the pixel circuit in the hold stage, the output module 504 is specifically configured to: and transmitting a first driving time sequence signal to a first driving circuit in the grid driving circuit, so that the first driving circuit turns on an oxide transistor in the pixel circuit in a refreshing stage, turns on the driving transistor based on the output of the oxide transistor, turns off the oxide transistor in a holding stage, and turns off the driving transistor.
Optionally, the first driving timing signal fluctuates during the refresh period based on a preset refresh frequency, and the second level is maintained during the hold period or fluctuates based on a specified frequency.
In an example, the display control device provided in the embodiment of the present application may be a TCON, or may be another type of controller, which is not limited in this embodiment of the present application.
In one example, the display control apparatus provided by the embodiment of the present application may further include: and the input interface module can receive image data, clock signals and the like rendered and sent by the GPU through a specific protocol interface and transmit the image data, the clock signals and the like to the image processing module, the time sequence control module and the wake-up control module.
The functions of each module in the display control device provided in the embodiment of the present application may refer to the corresponding descriptions in the above method embodiments, and are not repeated herein.
Based on the same inventive concept, the embodiment of the present application further provides a display control system, as shown in fig. 6, including: the image processing unit 601, the storage unit 602, and the display control device 603, the image processing unit 601 and the storage unit 602 are all connected with the display control device 603 in communication. The display control device 603 may be any one of the display control devices provided in the embodiments of the present application.
The image processing unit 601 is configured to render image data and transmit the image data and a clock signal to the display control device, and may be disposed at the AP end.
The storage unit 602 is configured to store configuration parameters of the display control device, and in some examples, may also store information such as a Gamma LUT (Look-Up Table), demura LUT, etc.; the Gamma represents a Gamma curve index of the display screen, and represents the relation between the gray level and the brightness of the image.
The memory unit 602 may include read only memory and random access memory, and may also include nonvolatile random access memory. The memory may be volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. The nonvolatile Memory may include Read-Only Memory (ROM), programmable ROM (PROM), erasable Programmable ROM (EPROM), electrically Erasable EPROM (EEPROM), or FLASH Memory (FLASH), among others. Volatile memory can include random access memory (Random Access Memory, RAM), which acts as external cache memory. By way of example, and not limitation, many forms of RAM are available. For example, static RAM (SRAM), dynamic RAM (Dynamic Random Access Memory, DRAM), synchronous DRAM (SDRAM), double Data rate Synchronous DRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous DRAM (SLDRAM), and Direct RAM (DR RAM).
In an optional implementation manner, the display control system provided by the embodiment of the application further includes: the voltage conversion unit 604, which is electrically connected to the display control device and the gate driving circuit, is used to convert the voltage of the driving timing signal output by the display control device into the operating voltage of the gate driving circuit, and transmit the operating voltage to the gate driving circuit.
The display control system of the embodiment of the application can further comprise: a PMIC (Power Management IC, integrated power management circuit) 605 electrically connected to the storage unit 602, the display control device 603, the voltage conversion unit 604, and the display module, respectively, may provide working logic voltages to the storage unit 602, the display control device 603, the voltage conversion unit 604, and the display module, respectively, and may also provide a light emission control signal to the display module.
Referring to the example of fig. 3, the light emission control signal includes a light emission start pulse signal em_stv, a light emission timing signal CK3, and a light emission timing signal CB3, and in one display period including a refresh period and a sustain period, the em_stv signal, the CK3 signal, and the CB3 signal each fluctuate based on 120Hz, and continuous light emission of the sustain period may cause no flicker to occur in the sustain period.
The functions of each unit and device in the display control system provided by the embodiment of the present application may refer to the corresponding descriptions in the method embodiment and the device embodiment, and are not repeated herein.
Based on the same inventive concept, the embodiment of the application also provides a display device, as shown in fig. 6, which comprises a display module and any one of the display control systems provided by the embodiment of the application, wherein the display module is in communication connection with the display control system.
The display module in the embodiment of the application can be an OLED display module prepared by adopting an LTPO backboard technology, a pixel circuit (positioned in a display area) in the display module comprises an oxide transistor and a low-temperature polysilicon transistor, a grid driving circuit in the display module comprises a first driving circuit for driving the oxide transistor and a second driving circuit for driving the low-temperature polysilicon transistor, and the first driving circuit and the second driving circuit can be GOA (Gate on Array) circuits. The structure of the display module can improve the flicker phenomenon under low frequency, reduce the power consumption of the display module and prolong the service life of the display module.
The display module further includes a source driving circuit, which can perform digital-to-analog conversion on the digital image signal outputted by the display control device to obtain a pixel voltage, for example, RGB (red, green and blue) pixel voltage, and other functions of the gate driving circuit and the source driving circuit can refer to the foregoing embodiments, which will not be described herein.
In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions in accordance with the present application are fully or partially produced. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. Computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
Any process or method description in a flowchart or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process. And the scope of the preferred embodiments of the present application includes additional implementations in which functions may be performed in a substantially simultaneous manner or in an opposite order from that shown or discussed, including in accordance with the functions that are involved.
Logic and/or steps represented in the flowcharts or otherwise described herein, e.g., a ordered listing of executable instructions for implementing logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions.
It is to be understood that portions of the present application may be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, the various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. All or part of the steps of the methods of the embodiments described above may be performed by a program that, when executed, comprises one or a combination of the steps of the method embodiments, instructs the associated hardware to perform the method.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing module, or each unit may exist alone physically, or two or more units may be integrated in one module. The integrated modules may be implemented in hardware or in software functional modules. The integrated modules described above, if implemented in the form of software functional modules and sold or used as a stand-alone product, may also be stored in a computer-readable storage medium. The storage medium may be a read-only memory, a magnetic or optical disk, or the like.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that various changes and substitutions are possible within the scope of the present application. Therefore, the protection scope of the application is subject to the protection scope of the claims.

Claims (12)

1. A display control method, characterized by comprising:
acquiring image data and a clock signal;
generating a driving time sequence signal and a wake-up signal according to the clock signal and the target refresh frequency;
transmitting the driving time sequence signal to a grid driving circuit in a display module, so that the grid driving circuit drives a pixel circuit in the display module under the control of the driving time sequence signal;
and transmitting the awakening signal and the image data to a source driving circuit in the display module, so that the source driving circuit refreshes the image data according to the target refreshing frequency under the control of the awakening signal.
2. The display control method according to claim 1, wherein the transmitting the wake-up signal and the image data to a source driving circuit in the display module includes:
and transmitting the wake-up signal to the source driving circuit, and transmitting the image data to the source driving circuit in response to a feedback signal returned by the source driving circuit for the wake-up signal.
3. The display control method according to claim 2, wherein the transmitting the wake-up signal to the source driving circuit, the transmitting the image data to the source driving circuit in response to a feedback signal returned by the source driving circuit for the wake-up signal, comprises:
transmitting the wake-up signal to the source driving circuit, transmitting the image data to the source driving circuit in a refresh stage in response to a feedback signal returned by the source driving circuit for the wake-up signal, stopping the transmission of the image data in a hold stage, and holding for a specified period of time in a state where the transmission is currently stopped.
4. The display control method according to claim 3, wherein the specified duration is determined based on a preset refresh frequency and the target refresh frequency.
5. The display control method according to any one of claims 1 to 4, wherein the transmitting the driving timing signal to the gate driving circuit in the display module causes the gate driving circuit to drive the pixel circuit under the control of the driving timing signal, comprising:
and transmitting the driving time sequence signal to the gate driving circuit, so that the gate driving circuit turns on the driving transistor in the pixel circuit in a refreshing stage and turns off the driving transistor in the pixel circuit in a holding stage.
6. The display control method according to claim 5, wherein the transmitting the drive timing signal to the gate drive circuit causes the gate drive circuit to turn on the drive transistor in the pixel circuit in a refresh phase and to turn off the drive transistor in the pixel circuit in a hold phase, comprising:
and transmitting a first driving time sequence signal to a first driving circuit in the grid driving circuit, so that the first driving circuit turns on an oxide transistor in the pixel circuit in a refreshing stage, turns on the driving transistor based on the output of the oxide transistor, turns off the oxide transistor in a holding stage, and turns off the driving transistor.
7. The display control method according to claim 6, wherein the first driving timing signal fluctuates based on a preset refresh frequency in the refresh stage, and the second level is maintained in the hold stage or fluctuates based on a specified frequency.
8. A display control apparatus, comprising:
the image processing module is used for acquiring image data;
the time sequence control module is used for acquiring a clock signal and generating a driving time sequence signal according to the clock signal and a target refresh frequency;
the wake-up control module is used for acquiring the clock signal and generating a wake-up signal according to the clock signal and the target refresh frequency;
and the output interface module is used for transmitting the driving time sequence signal to a gate driving circuit in the display module, so that the gate driving circuit drives a pixel circuit in the display module under the control of the driving time sequence signal, and transmitting the awakening signal and the image data to a source driving circuit in the display module, so that the source driving circuit refreshes the image data according to the target refreshing frequency under the control of the awakening signal.
9. A display control system, comprising: an image processing unit, a storage unit, and the display control apparatus of claim 8;
the image processing unit and the storage unit are both in communication connection with the display control device;
the image processing unit is used for rendering image data and transmitting the image data and clock signals to the display control device;
the storage unit is used for storing configuration parameters of the display control device.
10. The display control system of claim 9, further comprising: a voltage conversion unit electrically connected with the display control device and the gate driving circuit respectively;
the voltage conversion unit is used for: and converting the voltage of the driving time sequence signal output by the display control device into the working voltage of the grid driving circuit, and transmitting the working voltage to the grid driving circuit.
11. A display device, characterized by comprising: a display module and a display control system as claimed in claim 9 or 10;
the display module is in communication connection with the display control system.
12. The display device according to claim 11, wherein the pixel circuit in the display module includes an oxide transistor and a low-temperature polysilicon transistor;
the grid driving circuit in the display module comprises a first driving circuit used for driving the oxide transistor and a second driving circuit used for driving the low-temperature polysilicon transistor.
CN202210146275.0A 2022-02-17 2022-02-17 Display control method, device and system and display equipment Active CN114446239B (en)

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