CN1144360A - Communication method and device - Google Patents
Communication method and device Download PDFInfo
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- CN1144360A CN1144360A CN96108783A CN96108783A CN1144360A CN 1144360 A CN1144360 A CN 1144360A CN 96108783 A CN96108783 A CN 96108783A CN 96108783 A CN96108783 A CN 96108783A CN 1144360 A CN1144360 A CN 1144360A
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- instruction
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
- G06F13/126—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine and has means for transferring I/O instructions and statuses between control unit and main processor
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1673—Details of memory controller using buffers
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- General Engineering & Computer Science (AREA)
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Abstract
To provide a communication method/device which can evade a buffer- full state for a transmission buffer of a communication device with no increase of the production cost. This method/device includes a reception buffer, a CPU which generates the reply data, a transmission buffer, and a communication port which transmits the reply data undergone the buffering by the buffer to the computer in a transmission timing. When the CPU processes the command requiring the transmission of data to the computer, the buffer is instructed to apply the buffering to only the reply command corresponding to the command undergone the buffering by the buffer. Then the transmission data are in the transmission timing based on the reply command undergone the buffering by the buffer and the data corresponding to the reply data.
Description
The present invention relates to communication means and communicator, specifically, the present invention relates to have according to from the monitor apparatus of computer system such as the instruction of the data transfer requested of the computer body of principal computer main equipment and communication means between the slave unit and communicator to principal computer loopback parameter function.
In recent years, the intellectuality of the monitor apparatus of computer system is in continuous development, with regard to monitor apparatus, has under a lot of situations and as the communication function of the computer body of principal computer.The intelligentized fundamental purpose of this monitor apparatus is for the function of monitor apparatus, characteristic are notified to principal computer.For this reason, generally all use such method: to the instruction that the monitor apparatus request of sending transmits preset parameter, the monitor apparatus that has received above-mentioned instruction is giving principal computer for the response instruction of this instruction and the parameter loopback of being asked from principal computer.
As the interface of realizing this method, general all is the extremely serial communication of simple communication protocols: when monitor apparatus sent data, principal computer and monitor apparatus became main equipment and slave unit respectively and transmit data (instruction) from the principal computer as main equipment to the monitor apparatus as slave unit at the needs principal computer.Otherwise, needs from monitor apparatus when principal computer sends data, monitor apparatus and principal computer become main equipment and slave unit respectively, and transmit data (response instruction and desired parameter) from the monitor apparatus as main equipment to the principal computer as slave unit.
The communication protocol that this data transmit is generally only undertaken by data line and these two lines of clock line.Thereby, can not send data by two-way simultaneous.
Yet, in above-mentioned existing method, when as the monitor apparatus of slave unit when the principal computer as main equipment receives data, as long as principal computer just might unrestrictedly send data as main equipment.Also have, to the instruction that monitor apparatus sends, also comprise the instruction that indication passes a parameter to principal computer from monitor apparatus from principal computer.Under the situation that has received this instruction, prepare with regard to needs in the monitor apparatus and buffer memory is used for corresponding with this instruction and to the parameter of principal computer transmission.Also have, having under the situation of a plurality of this instructions, carry out buffer memory together corresponding to the parameters of all instructions and with the instruction that is used to respond with regard to preparing.
Below, be that example specifically describes above-mentioned prior art with principal computer shown in the block diagram of Fig. 5 and the monitor apparatus that is connected.
Among Fig. 5, reference symbol 1 expression principal computer, general computer system body is suitable therewith.Principal computer 1 is connected with monitor apparatus 3 by vision cable 2.Via vision cable 2 transmitting-receiving vision signals, horizontal-drive signal, vertical synchronizing signal, data-signal, clock signal etc.
Digital circuit block 8, analog circuit block 5, FBT6, CRT7 or the like be equipped with in the monitor apparatus 3.
Digital circuit block 8 has constituted so-called single-chip microcomputer usually, and himself totally plays a communicator as one.Digital circuit block 8 is equipped with CPU81, ROM82, RAM83, communication 84 and these is constituted bus 85 that devices are connected with each other or the like.
CPU81 is the control maincenter of monitoring arrangement 3, and as described later, it also plays instruction processing unit.Storing control program etc. among the ROM82 in advance.RAM83 is except that being used as various signs, storehouse, and its specific zone also is assigned as reception buffer 831 and the impact damper 832 of posting a letter.Communication port 84 be connected with principal computer 1 via vision cable 2 and carry out and principal computer 1 between communication.Yet, from monitoring arrangement 3 when principal computer 1 is posted a letter, communication 84 plays answering device.
The necessary horizontal output circuit 51 of display image, vertical output circuit 52, Distoriton compensating circuit 53, return line blanking circuit 54 etc. constitute analog circuit block 5 on CRT7 by being used for.In addition, because these of analog circuit block 5 constitute device and aim of the present invention is irrelevant, so save detailed explanation.
CRT7 is by mimic channel 5 controls and principal computer 1 given R, G, B signal is shown as image.
Fig. 6 be illustrated between principal computer 1 and the monitoring arrangement 3 communication instruction and with the general chart of an example of these instruction corresponding communication parameters.In this example, have in advance from principal computer 1 pass to monitor apparatus 3 make the instruction " 00 " that monitor apparatus 3 resets (wherein, with two sexadecimal numbers promptly 1 byte come presentation directives), the instruction " 01 " of request horizontal frequency, the instruction " 02 " of request vertical frequency, the instruction " 03 " of the horizontal dimension of picture of request, the instruction " 04 " of request vertical image size etc.
On the other hand, have the corresponding corresponding corresponding corresponding instruction " 84 " of replying the vertical image size of instruction " 83 ", and instruction " 04 " of replying the horizontal image size of instruction " 82 ", and instruction " 03 " of replying vertical frequency of instruction " 81 ", and instruction " 02 " of replying horizontal frequency of and instruction " 01 " of passing to principal computer 1 from monitor apparatus 3 in advance.
For example, when principal computer 1 was wanted to understand horizontal resolution that monitor apparatus 3 supported and spent, principal computer 1 sent instruction " 01 ".When monitor apparatus 3 receives this instruction, for to the own horizontal frequency of being supported of principal computer 1 announcement and to the instruction " 81 " of 1 byte of principal computer 1 loopback with represent the parameter of 4 bytes (respectively with 2 byte representation lower limits, the upper limit) of horizontal frequency.Thus, just can know the horizontal resolution degree that monitor apparatus 3 is supported in the principal computer 1.
Below, the existing communication order that the process description of the processing of posting a letter that the flow process of the reception Interrupt Process of being carried out when the flow process that the master who handles with reference to the general level of conduct shown in Figure 7 handles, reception data shown in Figure 8, the timing from regularly interrupting beginning shown in Figure 9 are called is undertaken by the digital circuit block 8 as communicator.
In main processing the shown in the flow process of Fig. 7, CPU81 at first checks whether received data from principal computer 1 at first, specifically, whether is storing the data (step S11) from principal computer 1 in the reception buffer 831 of inspection RAM83.When the data that do not have to receive from principal computer 1, circulate at step S11.When the data that received from principal computer 1, CPU81 by this data interpretation for instruct branch (step S12) from principal computer 1 given instruction, handle accordingly respectively.
3 pairs of reception operations from the data of principal computer 1 of monitor apparatus then are to be undertaken by the Interrupt Process shown in the flow process of Fig. 8.Promptly, having when principal computer 1 sends via the data of vision cable 2, owing to 84 implemented to CPU81 and receive to have interrupted from communicating by letter, so, CPU81 checks at first in the reception buffer 831 of RAM83 whether dummy section (step S21) is arranged, if have, then in this dummy section, write the data that receive from principal computer 1 row cache (step S22) of going forward side by side.In addition, in step S21, when in judging reception buffer 831, not having dummy section, just carry out etc. pending (step S23).
Thereby, in main processing the shown in the flow process of Fig. 7, preferably make step S11 circulation up in step S11, distinguish the data of reception are arranged till.
As mentioned above, from principal computer 1 offers the instruction of monitor apparatus 3, all instructions shown in Fig. 6 general chart are arranged.The existing instruction that needs monitor apparatus 3 to reply to principal computer 1 in these instructions, having does not need the instruction of replying yet, for example instruction " 00 " such reset instruction.Thereby, in step S12, judge that the instruction that offers monitor apparatus 3 from principal computer 1 is the instruction that need reply, or reset instruction or other instruction, and handle accordingly respectively.
Belong to need be to instruction that principal computer 1 is replied the time in the instruction that offers monitor apparatus 3 from principal computer 1, CPU81 is arranged on the parameter of replying instruction and asked in the interior impact damper 832 of posting a letter of RAM83 (step S13), when being reset instruction, CPU81 makes monitor apparatus 3 reset (step S14), when being other instruction, CPU81 carries out relative processing (step S15) respectively.
In step S13, by the processing of carrying out like that shown in the flow process of Fig. 9 in the impact damper 832 of posting a letter that is arranged in the RAM83 of posting a letter of replying instruction and parameter.By by unshowned timers institute in the digital circuit block 8 regularly the timing of generation interrupt carrying out the above-mentioned processing of posting a letter.At first, CPU81 checks whether the transmission data are arranged, and specifically, whether buffer memory transmission data (step S31) at first in the impact damper 832 of posting a letter of RAM83.When having the transmission data.CPU81 reads the data of posting a letter (step S32) and sends to vision cable 2 (step S33) via communication 84 from the impact damper 832 of posting a letter of RAM83.In case sent one group of data (instruction and parameter), then whether the just further inspection of CPU81 has other transmission data (step S34), if have, the processing of then carrying out step S32, S33 repeatedly sends data to send remaining all, up to the transmission end of whole transmission data.
Here, illustrated from the communication of monitor apparatus 3 to principal computer 1.As previously mentioned, the transmission communication protocol between principal computer 1 and the monitor apparatus 3 is only to carry out with the extremely simple communication protocols of data line and these 2 lines of clock line.Therefore, though the energy two-way communication can not be carried out two-way communication simultaneously.
Also have, though at first be to send instruction from principal computer 1 to monitor apparatus 3 in the communication between principal computer 1 and monitor apparatus 3, the instruction that is sent is not limited to 1.Sometimes, principal computer 1 also sends many instructions to monitor apparatus 3 as requested.In this case, monitor apparatus 3 just need correspond respectively to many instructions reply the instruction and parameter be buffered in the impact damper 832 of posting a letter of RAM83.
Below, with reference to the explanation of the mode chart of Figure 10 in the impact damper 832 of posting a letter buffer memory which data.Now, illustrate for example from principal computer 1 when monitor apparatus 3 sends instruction shown in Figure 6 " 01 " continuously and promptly asks the instruction of horizontal frequency and instruction " 02 " promptly to ask the instruction of vertical frequency, the processing of being carried out in the monitor apparatus 3.Wherein, establish this moment monitor apparatus 3 and support the vertical frequency of 32KHz to the horizontal frequency of 84KHz and 50Hz to 150Hz.
As shown in Figure 6, corresponding to the instruction " 01 " that sends to monitor apparatus 3 from principal computer 1, be " 81 " from monitor apparatus 3 to the instruction that principal computer 1 sends, i.e. horizontal frequency loopback instruction, instruction corresponding to instruction " 02 " is " 82 ", i.e. vertical frequency loopback instruction.Therefore, shown in the mode chart of Figure 10, in the impact damper 832 of posting a letter of RAM83 successively buffer memory " 32 " of " 81 " of 1 byte, 2 bytes, " 84 ", " 82 ", " 50 " of 2 bytes of 1 byte of 2 bytes, " 150 " of 2 bytes amount to the data of totally 10 bytes.
Here, although show reply instruction and the parameter thereof of the instruction of sending from principal computer 1 corresponding to two are cached to example in the impact damper 832 of posting a letter, but also possibly must be in the metadata cache that principal computer 1 sends be more being posted a letter impact damper 832, in this case, the buffering overflow status can appear in the impact damper 832 of posting a letter, and constitutes the main cause of makeing mistakes.
As mentioned above, since in the monitor apparatus of computer system as the employed microcomputer of communicator single-chip microcomputer normally, so its memory size aspect is restricted, and it is just more limited to the capacity of the impact damper 832 of posting a letter of the transmission data of principal computer 1 wherein can to distribute to buffer memory.Thereby; as above-mentioned existing example; need all being buffered in the impact damper 832 of posting a letter, become the main cause of makeing mistakes thereby therefore be absorbed in the buffering overflow status through regular meeting from all data (replying instruction and parameter) that monitor apparatus 3 sends to principal computer 1.Though can alleviate this problem by enlarging memory span, will cause the raising of manufacturing cost like this.
The present invention forms in view of such situation, and purpose is to provide the impact damper of posting a letter of communicator can not be absorbed in communication means and the communicator that cushions overflow status, and manufacturing cost is gone up.
Communication means of the present invention be a kind of when having received the request that comes autonomous device and sent the instruction of data the communication means that instruction and desired data send to main equipment of replying corresponding to the instruction that is received, it is characterized in that, when having received the instruction that comes autonomous device, only the buffer memory correspondence replys instruction, and, in transmission timing, form by what buffer memory and reply the transmission data that instruction and data corresponding with it are constituted, and these data are sent to main equipment.
In addition, communicator of the present invention is characterised in that it is equipped with:
The reception instruction that comes autonomous device is carried out the reception buffer of buffer memory;
Processing is buffered in the instruction in the reception buffer and generates the instruction processing unit of reply data;
The reply data that is generated by instruction processing unit is carried out the impact damper of posting a letter of buffer memory;
In transmission timing being buffered in the answering device that reply data in the impact damper of posting a letter sends to main equipment;
Above-mentioned instruction processing unit need be when main equipment sends the instruction of data in processing, only with the corresponding Instructions Cache of replying of the instruction that is buffered in reception buffer in the impact damper of posting a letter, in transmission timing, replying of the impact damper of posting a letter instructed and data corresponding with it generate the transmission data by being buffered in.
In the communication means of the present invention, when having received the instruction that comes autonomous device, only buffer memory is corresponding with it replys instruction, and in transmission timing, reply instruction and the data corresponding with it by buffer memory generate and send data and these data are sent to main equipment.
Also have, in the communicator of the present invention, need be when main equipment sends the instruction of data in processing, only be buffered in the corresponding Instructions Cache of replying of instruction in the reception buffer in the impact damper of posting a letter, in transmission timing, generate the transmission data and these data are sent to main equipment with corresponding therewith data by the instruction of replying that is buffered in the impact damper of posting a letter.
Fig. 1 shows the block diagram of example that communicator of the present invention is applied to the monitor apparatus of computer system;
Fig. 2 is the process flow diagram that shows based on the communication sequence of communication means of the present invention;
Fig. 3 is the process flow diagram that shows based on the communication sequence of communication means of the present invention;
Fig. 4 shows the mode chart that is buffered in the data in the impact damper of posting a letter in the communication means of the present invention;
Fig. 5 is the block diagram of demonstration as the structure example of the monitor apparatus of the computer system of existing communication device;
Fig. 6 is a general chart that shows instruction of communicating by letter between principal computer and the monitor apparatus and the example of the messaging parameter that accompanies with it;
Fig. 7 is the process flow diagram that shows based on the communication sequence of existing communication method;
Fig. 8 is the process flow diagram that shows based on the communication sequence of existing communication method;
Fig. 9 is the process flow diagram that shows based on the communication sequence of existing communication method;
Figure 10 shows the mode chart that is buffered in the data in the impact damper of posting a letter in the existing communication method.
(embodiment)
Following accompanying drawing according to expression embodiment describes the present invention in detail.In addition, as an example, communication means of the present invention is to implement between common microcomputer body (principal computer) and monitor apparatus.In addition, instruction of communicating by letter between principal computer and monitor apparatus and the messaging parameter that accompanies with it and above-mentioned existing environmental facies shown in Figure 6 are together.
Below, specifically describe the example that communication means of the present invention is applied to monitor apparatus in the computer system shown in the block diagram of Fig. 1.
Among Fig. 1, reference symbol 1 expression principal computer, the body of common computer system is suitable therewith.Principal computer 1 links to each other with monitor apparatus 3 by vision cable 2.Can receive and dispatch vision signal, horizontal-drive signal, vertical synchronizing signal, data-signal, clock signal etc. via vision cable 2.
Digital circuit block 4, analog circuit block 5, FBT6, CRT7 etc. are equipped with in the monitor apparatus 3.
Digital circuit block 4 has constituted so-called single-chip microcomputer usually, the effect that himself totally plays a communicator is communicator of the present invention.The bus 45 that is equipped with CPU41, ROM42, RAM43, communication 44 in the digital circuit block 4 and these main structure divisions are coupled together.
CPU41 is the control maincenter of monitor apparatus 3, also plays the effect of instruction processing unit as described later.Storing control program etc. among the ROM42 in advance.RAM43 also distributes specific zone as the reception buffer 431 and the impact damper 432 of posting a letter except that using as various signs, storehouse.Communication port 44 connect via vision cable 2 and principal computer 1 and be responsible for principal computer 1 between communicate by letter.Thereby, from monitor apparatus 3 when principal computer 1 is posted a letter, communication 44 plays answering device.
CRT7 is controlled by analog circuit block 5 and R, the G, the B signal that provide from principal computer 1 is shown as image.
Below, with reference to the main treatment scheme of general grade of processing of conduct shown in Figure 2, the flow process of periodically asking transmission to be handled from regularly interrupting beginning shown in Figure 3 the communication sequence of communication means of the present invention is described.In addition, reception Interrupt Process of being carried out when principal computer 1 receives data and the not special relation of existing example shown in Figure 8 essence identical and of the present invention are so omitted.
In main processing of the communication means of the present invention shown in the flow process of Fig. 2, CPU41 at first checks at first whether received data from principal computer 1, specifically, check the data (step S51) of whether storing in the reception buffer 431 of RAM43 from principal computer 1.When the data that do not receive from principal computer 1, circulate at step S51 place.When the data that received from principal computer 1, CPU41 is this data interpretation the instruction that principal computer 1 provides, and instructs branch (step S52) thus, and handles accordingly respectively.
But the reception of being undertaken by monitor apparatus 3 for from the data of principal computer 1 then is to be undertaken by the Interrupt Process identical with the existing example shown in Fig. 8 flow process.That is to say, having when principal computer 1 sends via the data of vision cable 2, owing to receive interruption to the CPU41 application from communication port 44, so, CPU41 checks at first in the reception buffer 431 of RAM43 whether dummy section (step S21) is arranged, if have, then in this dummy section, write and data (step S22) that buffer memory receives from principal computer 1.In addition, in step S21, distinguish when not having dummy section in the reception buffer 431, just carry out etc. pending (step S23).
Therefore, in main processing the shown in Fig. 2 flow process, make step S51 circulation up in step S51, distinguish the data of reception are arranged till.
As previously mentioned, the various instructions shown in the general chart of Fig. 6 are arranged the instruction of passing to monitor apparatus 3 from principal computer 1.In these instructions, the existing instruction that need reply to principal computer 1 from monitor apparatus 3, having does not need the reset instruction of instruction as instruction " 00 " of replying etc. yet.Thereby, in step S12, judge that the instruction of passing to monitor apparatus 3 from principal computer 1 is the instruction that need reply, or reset instruction or other instruction, and handle accordingly respectively.
Belonging to need be to instruction that principal computer 1 is replied the time, CPU41 only replys instruction pack into (step S53) in the transmission buffer 432 in the RAM43 to 1 byte.When being reset instruction, CPU41 is monitor apparatus 3 reset (step S54).When being other instruction, CPU41 handles (step S55) respectively accordingly.
In step S53, the transmission processing of replying instruction that is encased in the impact damper 432 of posting a letter in the RAM43 is carried out shown in the flow process of Fig. 3 like that.This transmission is handled by the timing that is regularly taken place by unshowned timer in the digital circuit block 4 and is interrupted carrying out.At first, CPU41 checks whether the transmission data are arranged, and specifically, whether buffer memory transmission data (step S61) in the impact damper 432 of posting a letter of inspection RAM43.When exist sending data, CPU41 reads from the impact damper 432 of posting a letter of RAM43 as 1 byte instruction (step S62) that sends data, instructs branch (step S63) by the content of judging these transmission data, and handles accordingly respectively.
Suppose that now the instruction of reading from the impact damper 432 of posting a letter of RAM43 is " 81 ", CPU41 sends the needed processing of instruction " 81 ", specifically, generate and instruct the processing (step S64) of the parameter that " 81 " send to principal computer 1 together, equally, when the instruction of reading from the impact damper 432 of posting a letter of RAM43 is " 82 " or " 83 ", CPU41 sends instruction " 82 " or " 83 " needed processing, specifically, generate and instruct processing (the step S65 of the parameter that " 82 " or " 83 " send to principal computer 1 together, S66).As for other each instruction, each all similarly divides the generation of carrying out parameters needed when principal computer 1 is posted a letter in addition to handle.
Like this, CPU41 the instruction of reading from the impact damper 432 of posting a letter of RAM43 with corresponding with it and parameter that generate sends (step S67) via communication port 44 to vision cable 2.Send one group of data (instruction and parameter), CPU41 is with regard to further checking the transmission data (step S68) that whether also have other, if having, the then processing of repeating step S62 to S67 sends end up to whole instructions.
Below, with reference to the mode chart of Fig. 4 buffer memorys have been described in the impact damper 432 of having posted a letter in the communication means of the present invention which data.To for example describing from principal computer 1 processing in the monitor apparatus 3 when monitor apparatus 3 sends the instruction shown in above-mentioned Fig. 6 " 01 " continuously and promptly asks horizontal frequency instruction and instruction " 02 " promptly to ask the vertical frequency instruction.Wherein, establish at this moment monitor apparatus 3 and support the horizontal frequency of 32KHz to 84KHz respectively, 50Hz is to the vertical frequency of 150Hz.
As shown in Figure 6, corresponding to the instruction " 01 " that sends to monitor apparatus 3 from principal computer 1, be " 81 " from monitor apparatus 3 to the instruction that principal computer 1 sends, promptly horizontal frequency is replied instruction, corresponding to the instruction " 02 " be the instruction " 82 ", promptly vertical frequency is replied instruction.Thereby, shown in the mode chart of Fig. 4, in the impact damper 432 of posting a letter of RAM43, only buffer memory instruction " 82 " data of 2 bytes altogether of the instruction " 81 " of 1 byte, 1 byte.
And when sense order " 81 " from the impact damper 432 of posting a letter of RAM43, CPR41 generates the data of two byte parameters " 32 " and two byte parameters " 84 " and these data is sent to principal computer 1 and sends.
In addition, in the above-described embodiments, computer body with microsystem is a main equipment, with the monitor apparatus is that slave unit is illustrated, although such relation is arranged, also be applicable to and other various devices between communication means or and other the device between from the device that communicates as slave unit.
As above detailed description the in detail,,, make mistakes or the probability of happening of waiting status so reduced because the impact damper of posting a letter that has reduced communicator is absorbed in the possibility of buffering overflow status according to communication means of the present invention and communicator.In addition, owing to do not need to enlarge the capacity of the impact damper of posting a letter, so manufacturing cost not will rise.
Claims (2)
1. communication means wherein, sends corresponding to the data of replying instruction and being asked that receive instruction to above-mentioned main equipment when having received from main equipment that request sends data command, and this communication means is characterised in that:
When above-mentioned main equipment has received instruction, only buffer memory is corresponding replys instruction;
In transmission timing, generate and send data by reply instruction and the corresponding data of buffer memory, and should send data and send to above-mentioned main frame transmission.
2. communicator, it is equipped with:
Buffer memory is from the reception buffer of the data of main equipment reception;
Processing is buffered in the instruction in the above-mentioned reception buffer and generates the instruction processing unit of reply data;
Buffer memory is by the impact damper of posting a letter of the reply data of above-mentioned instruction processing unit generation;
In transmission timing, send the answering device that is buffered in the reply data in the above-mentioned impact damper of posting a letter to above-mentioned main equipment.
Above-mentioned communicator is characterised in that:
Described instruction processing unit handle need be when main equipment sends the instruction of data only be buffered in the corresponding Instructions Cache of replying of instruction in the above-mentioned reception buffer in the above-mentioned impact damper of posting a letter; And
Instruct and the data corresponding with it generate the transmission data with being buffered in by replying in the above-mentioned impact damper of posting a letter in transmission timing for this instruction processing unit.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7154740A JPH096698A (en) | 1995-06-21 | 1995-06-21 | Communication method and device |
| JP154740/95 | 1995-06-21 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1144360A true CN1144360A (en) | 1997-03-05 |
| CN1096641C CN1096641C (en) | 2002-12-18 |
Family
ID=15590894
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN96108783A Expired - Fee Related CN1096641C (en) | 1995-06-21 | 1996-06-18 | Communication method and device |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPH096698A (en) |
| KR (1) | KR970002687A (en) |
| CN (1) | CN1096641C (en) |
| TW (1) | TW280887B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI392271B (en) * | 2006-11-27 | 2013-04-01 | Hon Hai Prec Ind Co Ltd | System and method for managing communication instructions |
| JP5102917B2 (en) * | 2008-02-22 | 2012-12-19 | 株式会社日立製作所 | Storage apparatus and access command transmission method |
-
1995
- 1995-06-21 JP JP7154740A patent/JPH096698A/en active Pending
-
1996
- 1996-02-07 TW TW085101484A patent/TW280887B/en active
- 1996-06-18 CN CN96108783A patent/CN1096641C/en not_active Expired - Fee Related
- 1996-06-20 KR KR1019960022516A patent/KR970002687A/en not_active Application Discontinuation
Also Published As
| Publication number | Publication date |
|---|---|
| TW280887B (en) | 1996-07-11 |
| KR970002687A (en) | 1997-01-28 |
| JPH096698A (en) | 1997-01-10 |
| CN1096641C (en) | 2002-12-18 |
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Granted publication date: 20021218 Termination date: 20100618 |