CN114429941A

CN114429941A - Semiconductor device and method for manufacturing the same

Info

Publication number: CN114429941A
Application number: CN202210082019.XA
Authority: CN
Inventors: 范纯圣; 林蔚峰
Original assignee: Omnivision Semiconductor Shanghai Co Ltd
Current assignee: Omnivision Semiconductor Shanghai Co Ltd
Priority date: 2022-01-24
Filing date: 2022-01-24
Publication date: 2022-05-03

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, comprising the following steps: the device comprises a silicon substrate and a transparent substrate which are oppositely arranged, wherein a first electrode is arranged on the periphery of the surface of one side, facing the transparent substrate, of the silicon substrate, and a second electrode is arranged on the periphery of the surface of one side, facing the silicon substrate, of the transparent substrate; the first electrode is electrically connected with the second electrode; the transfer carrier plate is provided with a lead electrode in a region which is positioned on at least one side of the silicon substrate and is far away from the silicon substrate; the lead electrode is electrically connected with the second electrode and leads the electric signal of the second electrode to the surface of one side of the transfer carrier plate far away from the silicon substrate. The lead electrode is arranged in the region of the transfer carrier plate, which is positioned on at least one side of the silicon substrate and is far away from the silicon substrate, namely the lead electrode can be led out from at least one side of the periphery of the silicon substrate and then led to the back side by the transfer carrier plate. Can support the multi-edge wire-out of the high-density lead electrode and simplify the manufacturing process. At the same time, the electrical signal is led to the back side, saving the size of the semiconductor device.

Description

Semiconductor device and method for manufacturing the same

Technical Field

The invention belongs to the technical field of integrated circuit manufacturing, and particularly relates to a semiconductor device and a manufacturing method thereof.

Background

LCOS (liquid Crystal on silicon) is a new LCD display made on single Crystal silicon, and is an emerging technology for organically combining LCD and CMOS integrated circuits. LCOS has the features of high resolution, reflecting imaging and low cost. LCOS displays are a reflective liquid crystal display device that uses semiconductor silicon technology to control the liquid crystal and "project" color pictures.

Fig. 1 is a cross-sectional view of an LCOS display. As shown in fig. 1, the LCOS display includes a silicon substrate 01, a liquid crystal layer 02 located above the silicon substrate 01, an ITO electrode layer 03, and a glass substrate 04, a pixel array is formed in the silicon substrate 01, and the ITO electrode layer 03 serves as a common electrode of the LCOS display.

In the LCOS display, the right side of the silicon substrate 01 protrudes from the glass substrate 04 by a portion for placing a lead electrode (e.g., a dense single row pad 05a) for electrical connection with a peripheral circuit or as an input/output (I/O) electrode; a portion of the glass substrate 04 on the left side thereof protrudes from the silicon substrate 01. The two extending directions extend towards opposite directions, so that a lot of area is occupied, the connecting function is only completed, and the display function is not realized, so that the size of the LCOS panel with the structure is larger.

Further, as the I/O density increases, the number of lead electrodes provided on the side of the silicon substrate 01 protruding from the glass substrate 04 is not sufficient, and thus, as shown in fig. 2, more lead electrodes (for example, dense

double row pads

05a and 05b) are provided on the side of the silicon substrate 01 protruding from the glass substrate 04, which increases the difficulty of designing the integrated circuit, causes the double row pads to interfere with each other, causes the double row pads to become noise sources of each other, increases the complexity of suppressing the LCOS noise, and increases the cost due to the smaller line width of the pads in the same area.

Disclosure of Invention

The invention aims to provide a semiconductor device and a manufacturing method thereof, which can support the multi-edge wire outgoing of a high-density lead electrode and simplify the manufacturing process. At the same time, the electrical signal is led to the back side, saving the size of the semiconductor device.

The present invention provides a semiconductor device including:

the device comprises a silicon substrate and a transparent substrate which are oppositely arranged, wherein a first electrode is arranged on the periphery of the surface of one side, facing the transparent substrate, of the silicon substrate, and a second electrode is arranged on the periphery of the surface of one side, facing the silicon substrate, of the transparent substrate; the first electrode is electrically connected with the second electrode;

the transfer carrier plate is provided with a lead electrode in an area which is positioned on at least one side of the silicon substrate and is far away from the silicon substrate; the lead electrode is electrically connected with the second electrode and leads the electric signal of the second electrode to the surface of one side of the transfer carrier plate, which is far away from the silicon substrate.

Furthermore, the silicon substrate is square, and the transfer carrier plate is arranged in the outer area of at least one group of opposite sides of the silicon substrate.

Furthermore, a heat dissipation metal layer is arranged in an area of the transfer carrier plate below the silicon substrate.

Further, a heat dissipation paste layer is arranged between the silicon substrate and the heat dissipation metal layer.

Furthermore, the surface of one side of the transfer carrier plate, which is far away from the silicon substrate, is provided with heat dissipation fins, and the heat dissipation fins are located in the area below the heat dissipation metal layer.

Furthermore, a protective glue or a metal sealing film layer is arranged on the periphery of the joint of the transparent substrate and the transfer support plate.

Furthermore, a dummy pad is arranged on one side, away from the silicon substrate, of the lead electrode in the transfer carrier plate, the dummy pad is insulated from the lead electrode, and the metal sealing film layer is formed on the dummy pad.

Furthermore, an ITO electrode layer is further arranged on the surface of one side, facing the silicon substrate, of the transparent substrate, the ITO electrode layer is electrically connected with the second electrode, and a liquid crystal layer is arranged between the ITO electrode layer and the silicon substrate.

The invention also provides a method for forming a semiconductor device, which comprises the following steps:

providing a silicon substrate and a transparent substrate which are oppositely arranged, wherein a first electrode is arranged on the surface peripheral side of one side, facing the transparent substrate, of the silicon substrate, and a second electrode is arranged on the surface peripheral side of one side, facing the silicon substrate, of the transparent substrate; the first electrode is electrically connected with the second electrode;

providing a transfer carrier plate, wherein a lead electrode is arranged on the transfer carrier plate in an area which is positioned on at least one side of the silicon substrate and is far away from the silicon substrate; the lead electrode is electrically connected with the second electrode and leads the electric signal of the second electrode to the surface of one side of the transfer carrier plate, which is far away from the silicon substrate.

Further, when the silicon substrate is an LCOS silicon substrate, providing the silicon substrate and the transparent substrate which are oppositely disposed specifically includes:

providing a silicon wafer, wherein a liquid crystal layer is formed above the silicon wafer, and the first electrodes are embedded on the upper surface of the silicon wafer at intervals; providing a transparent substrate wafer, wherein an ITO electrode layer and the second electrode which are electrically connected are formed on the surface of one side of the transparent substrate wafer, which faces to the silicon wafer;

arranging conductive adhesive at the joint of the second electrode and the first electrode, and thermally pressing the silicon wafer and the transparent substrate wafer, wherein the second electrode is electrically connected with the first electrode through the conductive adhesive;

scribing the silicon wafer to form a groove, wherein the groove penetrates through the silicon wafer and the conductive adhesive and exposes the second electrode;

and scribing the transparent substrate wafer.

Compared with the prior art, the invention has the following beneficial effects:

the invention provides a semiconductor device and a manufacturing method thereof, the semiconductor device comprises: the device comprises a silicon substrate and a transparent substrate which are oppositely arranged, wherein a first electrode is arranged on the surface peripheral side of one side, facing the transparent substrate, of the silicon substrate, and a second electrode is arranged on the surface peripheral side of one side, facing the silicon substrate, of the transparent substrate; the first electrode is electrically connected with the second electrode; the transfer carrier plate is provided with a lead electrode in an area which is positioned on at least one side of the silicon substrate and is far away from the silicon substrate; the lead electrode is electrically connected with the second electrode and leads the electric signal of the second electrode to the surface of one side of the transfer carrier plate, which is far away from the silicon substrate. The lead electrode (such as an I/O pad) is arranged in a region, far away from the silicon substrate, of at least one side of the silicon substrate of the transfer carrier plate, namely the lead electrode can be led out from at least one side of the periphery of the silicon substrate and then led to the surface (back side) far away from the silicon substrate by the transfer carrier plate. Can support the multi-edge outgoing line of high-density lead electrode (I/O pad), and simplify the process design. At the same time, the electrical signal is led to the back side, saving the size of the semiconductor device.

Furthermore, a heat dissipation metal layer may be embedded in an area of the transfer carrier plate located below the silicon substrate. The silicon substrate is in an approximate suspension state based on the heat dissipation paste layer, so that the mechanical stress is effectively reduced, and low-stress packaging is realized.

Furthermore, a protective glue or a metal sealing film layer is arranged on the periphery of the joint of the transparent substrate and the transfer support plate, so that the moisture resistance and the moisture resistance of the semiconductor device are improved.

Drawings

Fig. 1 is a schematic diagram of an LCOS display.

Fig. 2 is a schematic diagram of the noise effect of dual rows of pads of an LCOS display.

Fig. 3a is a schematic diagram of a semiconductor device being an LCOS display and a protective sealant according to an embodiment of the present invention.

Fig. 3b is a bottom view of fig. 3 a.

Fig. 4 is a schematic diagram of a semiconductor device of an LCOS display and provided with heat dissipation fins according to an embodiment of the present invention.

Fig. 5 is a schematic diagram of the semiconductor device of the embodiment of the invention being an LCOS display and the metal sealing film layer being sealed.

Fig. 6 is a schematic view of a semiconductor device of an embodiment of the present invention being a CIS and provided with a heat dissipating paste layer.

Fig. 7 is a schematic view of a semiconductor device according to an embodiment of the present invention in which a CIS is not provided with a heat dissipating paste layer.

Fig. 8 is a schematic diagram of the semiconductor device of the embodiment of the invention being a CIS and the interposer substrate being disposed only on the outer sides of a pair of opposite sides.

Fig. 9 is a schematic view of a semiconductor device of an embodiment of the present invention being a CIS and the first electrode and the second electrode being disposed in the form of a redistribution metal layer (RDL).

Fig. 10 is a flow chart illustrating a method for forming a semiconductor device according to an embodiment of the invention.

Fig. 11 is a schematic view illustrating a silicon wafer and a transparent substrate wafer being pressed together in a method for forming a semiconductor device according to an embodiment of the present invention;

fig. 12 is a schematic view of a groove formed by dicing a silicon wafer in the method of forming a semiconductor device according to the embodiment of the invention;

fig. 13 is a schematic view of a transparent substrate wafer after dicing in a method for forming a semiconductor device according to an embodiment of the present invention.

Fig. 14 is a schematic view illustrating an assembly of a stand-alone semiconductor device and a transfer carrier in a method for forming a semiconductor device according to an embodiment of the invention.

Fig. 15 is a schematic view of a semiconductor device according to an embodiment of the present invention after completion of assembly.

Wherein the reference numbers are as follows:

01-a silicon substrate; 02-liquid crystal layer; 03-an ITO electrode layer; 04-a glass substrate; 05 a-pad; 05 b-pad;

11-a silicon substrate; 12-a transparent substrate; 13-a first electrode; 14-a second electrode; 15-transferring the carrier plate; 16-a lead electrode; 17-an ITO electrode layer; 18-a liquid crystal layer; 19-a thermal grease layer; 20-a heat-dissipating metal layer; 21-radiating fins; 22-a connector; 23 a-protective glue; 23 b-a metal sealing film layer; 24-conductive glue; 25-conductive particles; 26-conductive particles; d-a virtual pad;

31-a silicon substrate; 32-a transparent substrate; 33-a microlens; 34-redistribution of the metal layer; 35-frame glue.

Detailed Description

Based on the above research, embodiments of the present invention provide a semiconductor device and a method for manufacturing the same. The invention is described in further detail below with reference to the figures and specific examples. The advantages and features of the present invention will become more apparent from the following description. It is to be noted, however, that the drawings are designed in a simplified form and are not to scale, but rather are to be construed in an illustrative and descriptive sense only and not for purposes of limitation.

In the drawings, the size of layers, regions, elements, and relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on" … …, "adjacent to … …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on … …," "directly adjacent to … …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application. And the discussion of a second element, component, region, layer or section does not imply that a first element, component, region, layer or section is necessarily present in the application.

Spatial relational terms such as "under … …," "under … …," "below," "under … …," "over … …," "above," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below … …" and "below … …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

An embodiment of the present invention provides a semiconductor device, including:

the device comprises a silicon substrate and a transparent substrate which are oppositely arranged, wherein a first electrode is arranged on the surface peripheral side of one side, facing the transparent substrate, of the silicon substrate, and a second electrode is arranged on the surface peripheral side of one side, facing the silicon substrate, of the transparent substrate; the first electrode is electrically connected with the second electrode;

Specifically, the silicon substrate is any one of an LCOS silicon substrate, a micro led silicon substrate and a CMOS Image Sensor (CIS) silicon substrate, and the corresponding manufactured semiconductor devices are an LCOS display, a micro led display and a CMOS Image Sensor (CIS), respectively.

Fig. 3a is a schematic diagram of a semiconductor device being an LCOS display and a protective sealant according to an embodiment of the present invention. Fig. 3b is a bottom view of fig. 3 a. With reference to fig. 3a to fig. 5, the silicon substrate is an LCOS silicon substrate, and the corresponding semiconductor device is an LCOS display.

As shown in fig. 3a and 3b, the semiconductor device a includes:

a silicon substrate 11 and a transparent substrate 12 which are oppositely arranged, wherein a first electrode 13 is arranged on the surface peripheral side of one side of the silicon substrate 11 facing the transparent substrate 12, and a second electrode 14 is arranged on the surface peripheral side of one side of the transparent substrate 12 facing the silicon substrate 11; the first electrode 13 is electrically connected with the second electrode 14;

a transfer carrier plate 15, wherein the transfer carrier plate 15 is provided with a lead electrode 16 in an area, which is located on at least one side of the silicon substrate 11 and is far away from the silicon substrate 11, the lead electrode 16 is electrically connected with the second electrode 14, and leads an electric signal of the second electrode 14 to a side surface, which is far away from the silicon substrate 11, of the transfer carrier plate 15.

Specifically, a pixel array is formed on one side of the silicon substrate 11 facing the transparent substrate 12, and the pixel array includes a plurality of pixels arranged in a plurality of columns and a plurality of rows. Specifically, a plurality of display units are formed on the silicon substrate 11, and each display unit includes a pixel array. Each display unit includes: the pixel array comprises a plurality of scanning lines, a plurality of data lines and a plurality of active devices (such as thin film transistors), wherein the active devices are electrically connected with pixel electrodes of the pixel array. A first electrode 13 is arranged on the periphery of one side surface of the silicon substrate 11 facing the transparent substrate 12, and the first electrode 13 is used for leading out an electric signal and electrically connecting with a peripheral device.

The transparent substrate 12 is, for example, a glass substrate, and an ITO electrode layer 17 is further disposed on a surface of the transparent substrate 12 facing the silicon substrate 11, and the ITO electrode layer 17 is electrically connected to the second electrode 14. The ITO electrode layer 17 serves as a common electrode for the LCOS display. ITO (indium tin oxide) is transparent to about 95% of the wavelengths in the visible spectrum. The thickness of the ITO electrode layer 17 ranges from 20nm to 60nm to achieve high optical performance. A liquid crystal layer 18 is provided between the ITO electrode layer 17 and the silicon substrate 11. A first alignment layer (not shown) may be further formed between the silicon substrate 11 and the liquid crystal layer 18, and a second alignment layer, such as a PI (polyimide) layer, may be formed between the liquid crystal layer 18 and the ITO electrode layer 17 for alignment of the liquid crystal layer.

The first electrode 13 and the second electrode 14 are electrically connected by conductive particles 25 in a conductive paste 24. The lead electrode 16 and the second electrode 14 are electrically connected by conductive particles 26 in a conductive paste. The conductive particles 25 and the conductive particles 26 may each be at least one of a single metal conductive particle and an alloy conductive particle. Wherein, the single metal conductive particles may be at least one of gold particles, silver particles, copper particles and nickel particles, but are not limited thereto; the alloy conductive particles may be at least one of silver-plated copper particles, silver-plated gold particles, silver-plated nickel particles, gold-plated copper particles, and gold-plated nickel particles, but are not limited thereto. The alloy conductive particles have good oxidation resistance and conductivity, and the product is convenient to store and carry, does not influence the physical property of the product, and has high stability and reliability.

In the example in fig. 3a and 3b, the interposer carrier 15 is arranged in layers in the lower region and the peripheral side adjacent region of the silicon substrate 11, a recess is provided in the interposer carrier 15, and the silicon substrate 11 is arranged in the recess of the interposer carrier 15. Lead electrodes 16 are provided in the peripheral side region of the recess of interposer carrier 15. In another example, the silicon substrate 11 is square, the interposer carrier 15 is not disposed in a whole layer, the interposer carrier 15 is not disposed in the region directly below the silicon substrate 11, and the interposer carrier 15 is disposed only in the outer region of at least one pair of opposite sides of the silicon substrate 11, for example, the interposer carrier 15 is disposed in the outer region of one pair of opposite sides CF and DE of the silicon substrate 11 and/or the outer region of the other pair of opposite sides CD and EF of the silicon substrate 11, the outer region refers to a region far away from the silicon substrate 11. The interposer carrier 15 is provided with the lead electrodes 16 in an outer region of at least one side of the silicon substrate 11, the lead electrodes 16 may be provided in an outer region of any one side of the square of the silicon substrate 11, or in outer regions of any two sides, or in outer regions of any three sides, or the lead electrodes 16 may be provided on each of four sides of the square of the silicon substrate 11, and the lead electrodes 16 in the outer regions of any one side of the square of the silicon substrate 11 are, for example, a group of pads densely distributed in a single row.

The present embodiment provides optimal electrical and optical adaptation without multiple cavity glass protection, and the lead electrodes 16 (e.g., I/O wires) can be led out from the periphery of the silicon substrate 11 and then to the backside via the interposer carrier 15 (e.g., ceramic carrier). Can support high density I/O pads with multi-edge lines, and simplify the process design.

Illustratively, the lead electrode 16 includes a first end portion 16c electrically connected to the second electrode 14, a connecting portion 16b arranged along the thickness direction of the interposer carrier 15, and a second end portion 16a located on a side surface of the interposer carrier 15 away from the silicon substrate 11; the first end 16c, the connection portion 16b, and the second end 16a are electrically connected in this order; the second end 16a is, for example, a single row of closely spaced pads. The material of the lead electrode 16 may be at least one of copper, aluminum, or tungsten.

The transfer carrier plate 15 includes: at least one of a ceramic carrier plate, a resin carrier plate and an epoxy glass carrier plate. Illustratively, the ceramic carrier plate includes: ceramic Leadless Chip Carriers (CLCC) or pre-molded leadless chip carriers (PLCC), and the like. The example leads the electric signal to the surface of one side of the transfer carrier plate 15 far away from the silicon substrate 11, so that the size of the semiconductor device is saved; meanwhile, for better heat dissipation, a heat dissipation metal layer 20 may be embedded in the region of the interposer carrier 15 below the silicon substrate 11. Specifically, the heat dissipation metal layer 20 is distributed as a whole metal layer in the area near the top and bottom surfaces of the interposer carrier 15, and the middle area in the thickness direction of the interposer carrier 15 may be a columnar structure distributed at intervals in the plane parallel to the silicon substrate 11, so as to facilitate heat dissipation. A heat dissipation paste layer 19 may be further disposed between the silicon substrate 11 and the heat dissipation metal layer 20, and the heat dissipation paste layer 19 is, for example, a phase-change type heat dissipation paste. The gap between the silicon substrate 11 and the heat-dissipating metal layer 20 can be filled with the heat-dissipating paste layer 19, so that the heat generated during the operation of the silicon substrate 11 can be effectively conducted away through the heat-dissipating paste layer 19. Based on the use of the heat dissipation paste layer 19, the silicon substrate 11 (e.g., LCOS silicon substrate) is in an approximate suspension state, so that the mechanical stress is effectively reduced, and low-stress packaging is realized.

As shown in fig. 4, a heat dissipation fin 21 may be further disposed on a surface of the transfer carrier 15 on a side away from the silicon substrate 11, where the heat dissipation fin 21 is, for example, in a shape of a comb, and the heat dissipation fin 21 is located in a lower area of the heat dissipation metal layer 20, so that the silicon substrate 11 (e.g., an LCOS silicon substrate) can work normally and simultaneously achieve a better heat dissipation effect.

In the example of fig. 3a and 4, a protective adhesive 23a is disposed around a seam between the transparent substrate 12 and the interposer carrier 15, so that the interposer carrier 15 and the transparent substrate 12 form a sealed space structure, and a semiconductor device (e.g., an LCOS display) is placed in the sealed space structure, thereby improving moisture resistance and water vapor resistance of the semiconductor device (e.g., the LCOS display), and implementing a package structure design with low stress, moisture resistance and optimal optical adaptation. The packaging structure is suitable for LCOS displays, MicroLED devices and CMOS Image Sensors (CIS).

In other examples, as shown in fig. 5, a metal sealing film layer 23b is disposed around a seam between the transparent substrate 12 and the transfer carrier 15 to improve moisture resistance and moisture resistance of a semiconductor device (e.g., an LCOS display), where the metal sealing film layer 23b is made of: at least one of tungsten, titanium, aluminum, chromium, tin, and copper. The metal sealing film layer 23b may be formed by, for example, sputtering, chemical vapor deposition, or metal melting. The transfer carrier 15 may further include a dummy pad d, the dummy pad d is disposed outside the lead electrode 16 (on a side away from the silicon substrate 11), the dummy pad d and the lead electrode 16 are spaced (insulated), the dummy pad d is, for example, a metal layer, and the metal sealing film layer 23b may be better attached to or deposited on the dummy pad d, or the metal sealing film layer 23b is fused and fixed with the dummy pad by a metal melting method, so as to improve the adhesion of the metal sealing film layer 23b on the transfer carrier 15 and facilitate the formation of the metal sealing film layer 23 b. The dummy pads d are not electrically connected to other devices in the interposer carrier 15, and serve as auxiliary metal sealing film 23b, so they are called dummy pads d. With reference to fig. 6 to 9, the silicon substrate is a CMOS Image Sensor (CIS) silicon substrate, and the corresponding semiconductor device is a CMOS Image Sensor (CIS) for example.

As shown in fig. 6, a semiconductor device B (for example, a CMOS image sensor) includes:

a silicon substrate 31 and a transparent substrate 32 which are oppositely arranged, wherein a first electrode 13 is arranged on the surface peripheral side of one side of the silicon substrate 31 facing the transparent substrate 32, and a second electrode 14 is arranged on the surface peripheral side of one side of the transparent substrate 32 facing the silicon substrate 31; the first electrode 13 is electrically connected with the second electrode 14;

a transfer carrier plate 15, wherein a lead electrode 16 is arranged on the transfer carrier plate 15 in a region which is far away from the silicon substrate 31 and is positioned on at least one side of the silicon substrate 31; the lead electrode 16 is electrically connected to the second electrode 14, and leads an electrical signal of the second electrode 14 to a surface of the interposer carrier 15 away from the silicon substrate 11.

Specifically, the silicon substrate 31 may be a semiconductor substrate made of any semiconductor material (such as Si, SiC, SiGe, etc.) suitable for a semiconductor device. A plurality of pixel units including, for example, photodiodes for photoelectrically converting incident light in the optical path are formed in the silicon substrate 31. A microlens 33 may be formed above the silicon substrate 31, and incident light enters the pixel unit through the microlens 33. The transparent substrate 32 is, for example, a glass substrate, and an AR (anti-reflection) layer may be further formed on a surface of the transparent substrate 32 away from the silicon substrate 31, where the AR layer can reduce reflection of incident light as much as possible, so that more incident light enters the pixel unit.

The transfer carrier plate 15 includes: at least one of a ceramic carrier, a resin carrier and an epoxy glass carrier. The interposer carrier 15 is provided with a heat dissipation metal layer 20 in an area below the silicon substrate 31 for effective heat dissipation. A heat-dissipating paste layer 19 can be disposed between the silicon substrate 31 and the heat-dissipating metal layer 20, so that the silicon substrate 31 is in an approximately suspended state, thereby effectively reducing mechanical stress and realizing low-stress packaging. Comb-tooth-shaped heat dissipation fins (not shown) are arranged on the surface of one side of the transfer carrier plate 15 away from the silicon substrate 31, and the heat dissipation fins are located in the lower area of the heat dissipation metal layer 20, so that the silicon substrate 31 can work normally and simultaneously has a better heat dissipation effect.

In fig. 6, which shows that the semiconductor device is a CIS, the interposer carrier 15 is provided with a heat dissipation metal layer 20 in a region below the silicon substrate 31. A heat-dissipating paste layer 19 may be disposed between the silicon substrate 31 and the heat-dissipating metal layer 20. The silicon substrate 31 (such as a CIS silicon substrate) is in an approximate suspension state, so that the mechanical stress is effectively reduced, and the low-stress packaging of the CMOS image sensor is realized. In the present embodiment, a lead electrode 16 is disposed in the interposer carrier 15, and the lead electrode 16 is disposed in an area of the interposer carrier 15 located outside at least one side of the silicon substrate 31. The lead electrode 16 leads the electrical signal of the second electrode 14 to a surface of the interposer carrier 15 away from the silicon substrate 31. The side surface of the interposer carrier 15 away from the silicon substrate 31 may also be provided with connectors 22, such as ZIF connectors or B2B connectors as an example.

In another example, as shown in fig. 7, the semiconductor device is a CIS, a heat dissipation metal layer may not be disposed in a region of the interposer carrier 15 under the silicon substrate 31, and a heat dissipation paste layer may not be disposed between the silicon substrate 31 and the interposer carrier 15.

In still another example, as shown in fig. 8, the semiconductor device is a CIS, and the interposer carrier 15 is not disposed in a whole layer in a lower region of the silicon substrate 31, but disposed in an outer region of at least one set of opposite sides of the silicon substrate 31.

In the examples of fig. 6 to 8, it is shown that the periphery of the joint between the transparent substrate 32 and the relay carrier 15 is provided with a protective adhesive 23 a. The silicon substrate 31 and the transparent substrate 32 are made to enclose a sealed space structure, and a semiconductor device (e.g., CIS) is placed in the sealed space structure, so that the moisture resistance and moisture resistance of the semiconductor device (e.g., CIS) are improved. In other examples, a metal sealing film layer (not shown) may be disposed around the joint between the transparent substrate 32 and the interposer carrier 15 to improve the moisture and moisture resistance of a semiconductor device (e.g., CIS).

Fig. 9 shows that the semiconductor device is a CIS, and the first electrode on the silicon substrate 31 and the second electrode on the transparent substrate 32 are uniformly arranged in the form of a redistribution metal layer (RDL) 34. The silicon substrate 31 and the transparent substrate 32 are sealed by a sealant 35. One end of a redistribution metal layer (RDL)34 is disposed on the periphery of the surface of the transparent substrate 32 facing the silicon substrate 31, the other end of the redistribution metal layer (RDL)34 is disposed on the periphery of the surface of the silicon substrate 31 facing the transparent substrate 32, the redistribution metal layer (RDL)34 is distributed along the periphery of the sealant 35, and the redistribution metal layer (RDL)34 realizes the electrical signal connection between the silicon substrate 31 and the transparent substrate 32. The sealant 35 is disposed between the silicon substrate 31 and the transparent substrate 32 and holds the silicon substrate 31 and the transparent substrate 32 together. The sealant 35 may be made of a UV curable material, a time/temperature curable material, or a photo-patterned material.

When the silicon substrate is a MicroLED silicon substrate, the corresponding semiconductor device is a MicroLED display. A MicroLED (also called MicroLED, mLED or mu LED) display comprises a MicroLED wafer, a MicroLED chip block or an array of distributed MicroLED chip particles. The MicroLED silicon substrate includes: at least one of a GaN-based UV/blue/green MicroLED substrate, an AlInGaP-based red/orange MicroLED substrate, and a GaAs or InP-based Infrared (IR) MicroLED substrate. Micro leds can achieve the high density required for light field displays. Micro leds can provide better performance, including brightness and energy efficiency, than other display technologies, such as Liquid Crystal Display (LCD) technology or organic led (oled) technology. Also formed in the micro led silicon substrate is a driver circuit, which may be configured to provide appropriate signals, voltages, and/or currents to drive or operate the micro led chip (e.g., select light emitting elements, control settings or control brightness, etc.). The driving circuit may be configured to drive a single micro led chip or a plurality of micro led chips.

The present invention also provides a method for forming a semiconductor device, as shown in fig. 10, including:

The silicon substrate is any one of an LCOS silicon substrate, a MicroLED silicon substrate and a CMOS Image Sensor (CIS) silicon substrate, and the corresponding manufactured semiconductor devices are an LCOS display, a MicroLED display and a CMOS Image Sensor (CIS) respectively.

The silicon substrate is an LCOS silicon substrate, and the corresponding semiconductor device is an LCOS display. Providing a silicon substrate and a transparent substrate which are oppositely arranged, and specifically comprising:

as shown in fig. 11, a silicon wafer 110 is provided, a liquid crystal layer 18 is formed above the silicon wafer 110, a first electrode 13 is embedded on the upper surface of the silicon wafer 110 at an interval, and the first electrode 13 is used for leading out an electrical signal and electrically connecting the electrical signal with a peripheral device. A transparent substrate wafer 120 is provided, the transparent substrate wafer 120 being, for example, a glass wafer. An ITO electrode layer 17 and a second electrode 14 are formed on one side surface of the transparent substrate wafer 120 facing the silicon wafer 110, and the ITO electrode layer 17 is electrically connected with the second electrode 14. The conductive adhesive 24 is disposed at the joint of the second electrode 14 and the first electrode 13, and the ITO electrode layer 17 is applied to the liquid crystal layer 18 by thermal pressing, so that the transparent substrate wafer 120 and the silicon wafer 110 are pressed together, and after cooling and solidification by the conductive adhesive 24, the upper and lower substrates and the circuit are bonded together to form the display module. The second electrode 14 is electrically connected to the first electrode 13 via the conductive particles 25 in the conductive paste 24.

Next, as shown in fig. 11 and 12, the silicon wafer 110 is diced to form trenches; specifically, the silicon wafer 110 is cut to form a groove, and a groove is formed between adjacent silicon substrates 11 (single chips), the groove penetrating the silicon wafer 110 and the conductive paste 24 and exposing the second electrode 14.

Next, as shown in fig. 12 and 13, the transparent substrate wafer 120 is diced, and the transparent substrate wafer 120 is cut between adjacent silicon substrates 11 (individual chips) to form individual semiconductor devices.

Next, as shown in fig. 14 and 15, the individual semiconductor device is assembled with a transfer carrier 15, illustratively, a groove is provided in the transfer carrier 15, the silicon substrate 11 is provided in the groove of the transfer carrier 15, a conductive paste 24 is provided between the line electrode 16 facing the second electrode 14, and the lead electrode 16 and the second electrode 14 are electrically connected through conductive particles 26 in the conductive paste 24. The lead electrode 16 and the second electrode 14 may be electrically connected by melting solder paste.

A protective adhesive 23a or a metal sealing film layer may be formed around the joint between the transparent substrate 12 and the interposer carrier 15 to improve the moisture and moisture resistance of the semiconductor device. The interposer carrier 15 is provided with a heat dissipation metal layer 20 in an area below the silicon substrate 11 for effective heat dissipation. Specifically, the heat dissipation metal layer 20 is distributed as a whole metal layer in the area near the top and bottom surfaces of the interposer carrier 15, and the middle area in the thickness direction of the interposer carrier 15 may be a columnar structure distributed at intervals in the plane parallel to the silicon substrate 11, so as to facilitate heat dissipation. A heat-dissipating paste layer 19 can be arranged between the silicon substrate 11 and the heat-dissipating metal layer 20, so that the silicon substrate 11 is in an approximate suspension state, the mechanical stress is effectively reduced, and the low-stress packaging is realized.

In summary, the present invention provides a semiconductor device and a method for fabricating the same, the semiconductor device includes: the device comprises a silicon substrate and a transparent substrate which are oppositely arranged, wherein a first electrode is arranged on the surface peripheral side of one side, facing the transparent substrate, of the silicon substrate, and a second electrode is arranged on the surface peripheral side of one side, facing the silicon substrate, of the transparent substrate; the first electrode is electrically connected with the second electrode; and the transfer carrier plate is provided with a lead electrode in the region, which is positioned on at least one side of the silicon substrate and is far away from the silicon substrate, the lead electrode is electrically connected with the second electrode, and the electric signal of the second electrode is led to the surface of one side, which is far away from the silicon substrate, of the transfer carrier plate. The lead electrode (such as an I/O pad) is arranged in a region, far away from the silicon substrate, of at least one side of the silicon substrate of the transfer carrier plate, namely the lead electrode can be led out from at least one side of the periphery of the silicon substrate and then led to the surface (back side) far away from the silicon substrate by the transfer carrier plate. Can support the multi-edge outgoing line of high-density lead electrode (I/O pad), and simplify the process design. At the same time, the electrical signal is led to the back side, saving the size of the semiconductor device.

In the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the method disclosed by the embodiment, the description is relatively simple because the method corresponds to the device disclosed by the embodiment, and the relevant points can be referred to the description of the method part.

The above description is only for the purpose of describing preferred embodiments of the present invention and is not intended to limit the scope of the claims of the present invention, and any person skilled in the art may make possible variations and modifications of the technical solution of the present invention using the method and technical content disclosed above without departing from the spirit and scope of the present invention, and therefore, any simple modifications, equivalent changes and modifications of the above embodiments according to the technical essence of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A semiconductor device, comprising:

2. The semiconductor device of claim 1, wherein the silicon substrate is square and the interposer carrier is disposed outside of at least one set of opposing sides of the silicon substrate.

3. The semiconductor device of claim 1, wherein the interposer carrier is provided with a heat-dissipating metal layer in a region below the silicon substrate.

4. The semiconductor device according to claim 3, wherein a heat-dissipating paste layer is provided between the silicon substrate and the heat-dissipating metal layer.

5. The semiconductor device according to claim 3, wherein a surface of the interposer carrier away from the silicon substrate is provided with heat dissipation fins, and the heat dissipation fins are located in an area below the heat dissipation metal layer.

6. The semiconductor device according to any one of claims 1 to 5, wherein a protective adhesive or a metal sealing film layer is disposed around a seam between the transparent substrate and the interposer carrier.

7. The semiconductor device according to claim 6, wherein a dummy pad is provided in the interposer carrier on a side of the lead electrode away from the silicon substrate, the dummy pad being insulated from the lead electrode, and the metal sealing film layer being formed on the dummy pad.

8. The semiconductor device according to claim 1, wherein an ITO electrode layer is further provided on a surface of the transparent substrate on a side facing the silicon substrate, the ITO electrode layer being electrically connected to the second electrode, and a liquid crystal layer being provided between the ITO electrode layer and the silicon substrate.

9. A method of forming a semiconductor device, comprising:

10. The method of forming a semiconductor device according to claim 9, wherein providing the silicon substrate and the transparent substrate disposed opposite to each other when the silicon substrate is an LCOS silicon substrate specifically comprises:

providing a silicon wafer, wherein a liquid crystal layer is formed above the silicon wafer, and the first electrodes are embedded on the upper surface of the silicon wafer at intervals; providing a transparent substrate wafer, wherein an ITO electrode layer and the second electrode which are electrically connected are formed on the surface of one side, facing the silicon wafer, of the transparent substrate wafer;

and scribing the transparent substrate wafer.