CN114420548A - Double-pattern etching method and DRAM manufacturing method - Google Patents

Double-pattern etching method and DRAM manufacturing method Download PDF

Info

Publication number
CN114420548A
CN114420548A CN202011173181.XA CN202011173181A CN114420548A CN 114420548 A CN114420548 A CN 114420548A CN 202011173181 A CN202011173181 A CN 202011173181A CN 114420548 A CN114420548 A CN 114420548A
Authority
CN
China
Prior art keywords
mask layer
layer
etching
top surface
spin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202011173181.XA
Other languages
Chinese (zh)
Inventor
姜东勋
周娜
王佳
李琳
李俊杰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Institute of Microelectronics of CAS
Zhenxin Beijing Semiconductor Co Ltd
Original Assignee
Institute of Microelectronics of CAS
Zhenxin Beijing Semiconductor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Institute of Microelectronics of CAS, Zhenxin Beijing Semiconductor Co Ltd filed Critical Institute of Microelectronics of CAS
Priority to CN202011173181.XA priority Critical patent/CN114420548A/en
Publication of CN114420548A publication Critical patent/CN114420548A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0331—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers for lift-off processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

The invention relates to a double-pattern etching method and a DRAM manufacturing method, belongs to the technical field of semiconductors, and solves the problem that in the prior art, all etching processes are implemented in a process chamber to cause the increase of manufacturing cost. The method comprises the following steps: providing a substrate including a semiconductor in a process chamber; sequentially forming a first hard mask layer, a second hard mask layer, a bottom mask layer and a top mask layer over a semiconductor substrate; patterning the top mask layer by a photolithography process; depositing a side wall material layer above the patterned top mask layer; etching the sidewall material layer and the top silicon oxynitride mask layer to expose the top surface of the spin-on carbon mask layer; and transferring the semiconductor substrate from the process chamber to a photoresist stripping chamber, and removing the spin-on carbon mask layer through a photoresist stripping process. Sidewall oxide and SiON etch processes are performed in the process chamber and a spin-on carbon etch process is performed in the photoresist stripping chamber to reduce the lifetime of the process chamber.

Description

Double-pattern etching method and DRAM manufacturing method
Technical Field
The invention relates to the technical field of semiconductors, in particular to a double pattern etching method and a DRAM manufacturing method.
Background
Memory is a device or component used in digital systems to store large amounts of information and is an important component in computers and digital devices. Memories may be divided into two broad categories, Random Access Memories (RAMs) and Read Only Memories (ROMs). The RAM includes DRAM, PRAM, MRAM, and the like, and the capacitor is one of the key components for manufacturing these RAMs. Each memory cell in a DRAM device consists of 1T1C (i.e., 1 transistor and 1 capacitor).
A typical etch tool may consist of only a process chamber, but the process chamber may also consist of a photoresist pr (photo resist) stripping chamber. Implementing a capacitive aperture structure etch Recipe (Recipe) within a process chamber includes a minimum of three etch steps: atomic Layer Deposition (ALD) sidewall oxide etch, silicon oxynitride (SiON) etch, and Spin On Carbon (SOC) etch. Since expensive process chambers are used, the manufacturing cost is high, the process time is long, and the like.
Disclosure of Invention
In view of the foregoing, embodiments of the present invention are directed to a dual pattern etching method and a method for manufacturing a DRAM, which solve the problem of increased manufacturing costs caused by performing all etching processes in a process chamber.
In one aspect, an embodiment of the present invention provides a double pattern etching method, including: providing a substrate including a semiconductor in a process chamber; sequentially forming a first hard mask layer, a second hard mask layer, a bottom mask layer and a top mask layer above the semiconductor substrate, wherein the top mask layer comprises a spin-on carbon mask layer and a top silicon oxynitride mask layer above the spin-on carbon mask layer; patterning the top mask layer by a photolithography process; depositing a side wall material layer above the patterned top mask layer; etching the side wall material layer and the top silicon oxynitride mask layer to expose the top surface of the spin-on carbon mask layer; and transferring the semiconductor substrate from the process chamber to a photoresist stripping chamber, and removing the spin-on carbon mask layer by an etching process.
The beneficial effects of the above technical scheme are as follows: the sidewall oxide etching process and the silicon oxynitride (SiON) etching process are implemented in the process chamber, and the spin-on carbon etching process is implemented in the photoresist stripping chamber, so that the service time of the process chamber can be shortened, and the manufacturing cost can be reduced.
Based on a further improvement of the above method, patterning the top mask layer by a photolithography process comprises: and patterning the photoresist mask layer into a plurality of first openings and a plurality of first bulges through the photoetching process, wherein the first openings and the first bulges are arranged at intervals.
Based on the further improvement of the method, the step of depositing a side wall material layer above the patterned top mask layer comprises the following steps: and depositing a side wall material layer above the plurality of first openings and the plurality of first bulges through an atomic layer deposition process to form a plurality of second openings.
Based on the further improvement of the method, the top surface of the side wall material layer comprises: the first top surface is located on the top surface of the first raised side wall material layer, and the second top surface is located in the first opening and is lower than the second top surface.
Based on the further improvement of the method, etching the side wall material layer and the top silicon oxynitride mask layer to expose the top surface of the spin-on carbon mask layer comprises the following steps: performing in-situ etching on the side wall material layer on the bottom surface of the first opening and the top surface of the first protrusion through a first etching process to expose the top surface of the top silicon oxynitride mask layer and the bottom surface of the second opening; and carrying out in-situ etching on the exposed top silicon oxynitride mask layer through a second etching process so as to remove the top silicon oxynitride mask layer.
Based on the further improvement of the method, the first etcherThe etchant used in the process and the second etching process comprises: CF (compact flash)4And CHF3。
Based on the further improvement of the method, in the first etching process, CF4Gas flow of greater than CHF3The gas flow rate of (a); and in the second etching process, CF4Gas flow of less than CHF3The gas flow rate of (2).
Based on the further improvement of the method, the spin-coating carbon mask layer is removed by an etching process: ex-situ etching the exposed spin-on carbon mask layer with an etchant comprising N to form a first trench exposing a third top surface of the bottom mask layer in the photoresist stripping chamber2、He、H2、H2N2Ar and CF4Any one of (1) and O2Plasma is generated.
Based on further improvement of the method, in the process of etching the top silicon oxynitride mask layer and the spin-on carbon mask layer, the bottom mask layer in the opening is partially etched to form a second groove, the bottom mask layer is partially recessed to expose a fourth top surface of the partially recessed bottom mask layer, wherein the fourth top surface is lower than the third top surface, and a side wall material layer protrusion is arranged between the first groove and the second groove.
Based on the further improvement of the method, the double-pattern etching method further comprises the following steps: and etching the bottom mask layer, the second hard mask layer and the first hard mask layer in the first groove and the second groove by taking the side wall material layer protrusion as a mask to form the capacitor hole, wherein the second hard mask layer is made of amorphous carbon, and the first hard mask layer is made of oxide.
In another aspect, an embodiment of the present invention provides a method for manufacturing a DRAM, including: forming a capacitor hole by using the double-pattern etching method; forming a lower electrode inside the capacitor hole; removing the side wall material layer, the bottom masking layer, the second hard masking layer and the first hard masking layer outside the lower electrode; and sequentially forming a capacitance dielectric layer and an upper electrode inside and outside the capacitor hole.
Based on a further improvement of the above method, the material of the lower electrode and the upper electrode comprises TaN or TiN.
Compared with the prior art, the invention can realize at least one of the following beneficial effects:
1. in the prior art, the etching processes of the sidewall oxide, the silicon oxynitride (SiON) and the spin-on carbon are all completed in the same process chamber, however, in the embodiment, the etching processes of the sidewall oxide and the silicon oxynitride (SiON) are implemented in the process chamber, and the spin-on carbon etching process is implemented in the PR stripping chamber, so that the service time of the process chamber can be shortened, and the manufacturing cost can be reduced.
2. The process chamber is expensive, but compared with the expensive process chamber, the PR stripping chamber is low in price, so that when a large number of semiconductor substrates are subjected to batch processing simultaneously, a side wall oxide and silicon oxynitride (SiON) etching process can be implemented in the process chamber, a spin-on carbon etching process can be implemented in the PR stripping chamber, the service time of the process chamber of a single semiconductor substrate is shortened, and the utilization rate of the process chamber can be further improved.
3. By changing CF4And CHF3The sidewall oxide material and the silicon oxynitride (SiON) material are etched in such a ratio that the etch selectivity is improved.
4. The trench width is adjusted by controlling the thickness of the mandrel and sidewall oxide material deposition on the mandrel sidewalls.
In the invention, the technical schemes can be combined with each other to realize more preferable combination schemes. Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and drawings.
Drawings
The drawings are only for purposes of illustrating particular embodiments and are not to be construed as limiting the invention, wherein like reference numerals are used to designate like parts throughout.
Fig. 1 is a schematic view of loading a semiconductor substrate into a process chamber according to an embodiment of the invention.
Fig. 2 is a schematic diagram of an intermediate stage of a double pattern etching method according to an embodiment of the present invention.
Fig. 3 is a schematic diagram of an intermediate stage of a double pattern etching method according to an embodiment of the present invention.
Fig. 4 is a schematic diagram of an intermediate stage of a double pattern etching method according to an embodiment of the present invention.
Fig. 5 is a schematic diagram of an intermediate stage of a double pattern etching method according to an embodiment of the present invention.
FIG. 6 is a schematic view of transferring a semiconductor substrate from a process chamber to a photoresist stripping chamber according to an embodiment of the present invention.
Reference numerals:
102-a process chamber; 202-a semiconductor substrate; 204 — a first hard mask layer; 206-a second hard mask layer; 208-bottom mask layer; 210-spin coating a carbon mask layer; 212-top silicon oxynitride mask layer; 214-a first projection; 216 — a first opening; 218-a first top surface; 220-a second top surface; 222-a side wall material layer; 224-a second opening; 226-top surface; 228-a second trench; 230-a fourth top surface; 232-a first trench; 234-a third top surface; 236-side wall material layer protrusion; 238-a third opening; 602-Photoresist stripping Chamber
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.
The invention discloses a double pattern etching method. Hereinafter, the double pattern etching method will be described in detail with reference to fig. 1 to 6.
Referring to fig. 1 and 2, a semiconductor substrate 202 is provided in the process chamber 102. For the sake of simplified view, the semiconductor substrate 202 is shown only in fig. 2, but the semiconductor substrate 202 is omitted in fig. 2 to 5.
Referring again to fig. 2, a first hard mask layer 204, a second hard mask layer 206, a bottom mask layer 208, and a top mask layer are sequentially formed over the semiconductor substrate 202. The top mask layer includes a spin-On carbon SOC (spin On carbon) mask layer 210 and a top silicon oxynitride mask layer 212 over the spin-On carbon mask layer 210. The material of the first hard mask layer 204 comprises an oxide, the material of the second hard mask layer 206 comprises Amorphous carbon (amophorus carbon) and the material of the bottom mask layer 208 comprises silicon oxynitride.
Referring again to fig. 2, the top mask layer is patterned by a photolithography process. Specifically, the method includes patterning the top mask layer into a plurality of first openings 216 and a plurality of first protrusions 214 through a photolithography process, wherein the first openings 216 and the first protrusions 214 are alternately disposed. In an embodiment, the 3 times width of the first protrusion 214 and the width of the first opening 216 may be equal or unequal.
Referring to fig. 3, a sidewall material layer 222 is deposited over the patterned photoresist mask layer to form a plurality of second openings 224. And reducing the pattern interval and densifying the pattern by depositing a side wall material layer. Specifically, the method includes depositing a sidewall spacer material layer 222 over the plurality of first openings 216 and the plurality of first protrusions 214 by an atomic layer deposition process to form a plurality of second openings 224, such that the width of the first protrusions 214 is the same as or different from the width of the sidewall spacer material layer 222 on two opposite sidewalls of the first protrusions 214. The width of the first protrusion 214 may be the same as or different from the width of the second opening 224 remaining after the deposition of the sidewall material layer 222. The top surface of the sidewall material layer 222 includes: a first top surface 218 at a top surface of the spacer material layer of the first protrusion 214 and a second top surface 220 of the spacer material layer in the first opening 216, wherein the first top surface 218 is higher than the second top surface 220.
Compared with the prior art, in the double pattern etching method provided by the embodiment, the width of the trench is adjusted by controlling the thicknesses of the mandrel and the oxide material on the side walls of the mandrel, which are opposite to the side walls of the mandrel.
Referring to fig. 4, the sidewall material layer and the top silicon oxynitride mask layer are etched to expose the top surface of the spin-on carbon mask layer. Specifically, the etching agents adopted for etching the side wall material layer and the top silicon oxynitride mask layer respectively comprise: CF (compact flash)4And CHF3. First, the sidewall material layer 222 on the bottom surface of the first opening 216 and the top surface of the first protrusion 214 is in-situ etched by a first etching process to form a third opening 238 to expose the top surface 226 of the top SiON mask layer. In the first etching process, CF4Gas flow of greater than CHF3The gas flow rate of (2). Then, the exposed top silicon oxynitride mask layer 212 is subjected to in-situ etching by a second etching process to remove the top silicon oxynitride mask layer 212 while leaving the remaining sidewall material layer unetched to expose the top surface of the spin-on carbon mask layer 210. In the second etching process, CF4Gas flow of less than CHF3The gas flow rate of (2).
Compared with the prior art, in the double-pattern etching method provided by the embodiment, CF is changed4And CHF3Etching sidewall oxidation with a ratio ofA material and a silicon oxynitride (SiON) material.
Referring to fig. 5 and 6, the semiconductor substrate is transferred from the process chamber 102 into a photoresist stripping chamber 602, and the spin-on carbon mask layer is removed by an etching process. Specifically, first, the load Lock module llm (load Lock module) is opened, the semiconductor substrate is transferred by the load module to the outside of the process chamber 102 through the load port lp (load port), and then the semiconductor substrate is moved into the photoresist stripping chamber 602, and the load Lock module is closed. Ex situ etching the exposed spin-on carbon mask layer 210 with an etchant comprising N to form a first trench 232 exposing a third top surface 234 of the bottom mask layer in a photoresist stripping chamber 6022、He、H2、H2N2Ar and CF4Any one of (1) and O2Plasma is generated. During the etching of the top silicon oxynitride mask layer 212 and the spin-on carbon mask layer 210, the bottom mask layer 208 in the third opening is partially etched to form a second trench 228, the bottom mask layer 208 is partially recessed to expose a fourth top surface 230 of the partially recessed bottom mask layer 208, wherein the fourth top surface 230 is lower than the third top surface 234, and a sidewall material layer protrusion 236 is disposed between the first trench 232 and the second trench 228.
After forming the first trench 232 and the second trench 228, the bottom mask layer 208, the second hard mask layer 206, and the first hard mask layer 204 in the first trench 232 and the second trench 228 are etched using the sidewall material layer protrusion 236 as a mask to form a capacitor hole, wherein the material of the second hard mask layer includes amorphous carbon, and the material of the first hard mask layer includes oxide.
Compared with the prior art, in the double-pattern etching method provided by the embodiment, the sidewall oxide etching process and the silicon oxynitride (SiON) etching process are implemented in the process chamber, and the spin-on carbon etching process is implemented in the PR stripping chamber, so that the service time of the process chamber can be shortened, and the manufacturing cost can be reduced.
The invention discloses a method for manufacturing a DRAM, which comprises the following steps: forming a capacitor hole by using the double-pattern etching method; forming a lower electrode inside the capacitor hole; removing the side wall material layer, the bottom masking layer, the second hard masking layer and the first hard masking layer outside the lower electrode; and sequentially forming a capacitance dielectric layer and an upper electrode inside and outside the capacitor hole. The lower electrode, the internal capacitance dielectric layer and the internal upper electrode form a first capacitor, and the lower electrode, the external capacitance dielectric layer and the external upper electrode form a second capacitor. The material of the lower electrode and the upper electrode includes TaN or TiN.
Compared with the prior art, the invention can realize at least one of the following beneficial effects:
1. in the prior art, the etching processes of the sidewall oxide, the silicon oxynitride (SiON) and the spin-on carbon are all completed in the same process chamber, however, in the embodiment, the etching processes of the sidewall oxide and the silicon oxynitride (SiON) are implemented in the process chamber, and the spin-on carbon etching process is implemented in the PR stripping chamber, so that the service time of the process chamber can be shortened, and the manufacturing cost can be reduced.
2. The process chamber is expensive, but compared with the expensive process chamber, the PR stripping chamber is cheap, so that when a large number of semiconductor substrates are simultaneously subjected to batch processing, a sidewall oxide and silicon oxynitride (SiON) etching process can be implemented in the process chamber, and a spin-on carbon etching process can be implemented in the PR stripping chamber, so that the service time of the process chamber of a single semiconductor substrate is shortened, and the utilization rate of the process chamber can be further improved.
3. By changing CF4And CHF3The sidewall oxide material and the silicon oxynitride (SiON) material are etched in such a ratio that the etch selectivity is improved.
4. The trench width is adjusted by controlling the thickness of the mandrel and the sidewall oxide material on the opposing sidewalls of the mandrel.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.

Claims (12)

1. A double pattern etching method is characterized by comprising the following steps:
providing a substrate including a semiconductor in a process chamber;
sequentially forming a first hard mask layer, a second hard mask layer, a bottom mask layer and a top mask layer above the semiconductor substrate, wherein the top mask layer comprises a spin-on carbon mask layer and a top silicon oxynitride mask layer above the spin-on carbon mask layer;
patterning the top mask layer by a photolithography process;
depositing a side wall material layer on the patterned top mask layer;
etching the side wall material layer and the top silicon oxynitride mask layer to expose the top surface of the spin-on carbon mask layer; and
and transferring the semiconductor substrate from the process chamber to a photoresist stripping chamber, and removing the spin-on carbon mask layer through an etching process.
2. The double pattern etching method according to claim 1, wherein patterning the top mask layer by a photolithography process comprises: patterning the top mask layer into a plurality of first openings and a plurality of first protrusions by the photolithography process, wherein the first openings and the first protrusions are alternately arranged.
3. The dual pattern etching method of claim 2, wherein depositing a layer of sidewall material over the patterned top mask layer comprises: and depositing a side wall material layer above the plurality of first openings and the plurality of first bulges through an atomic layer deposition process to form a plurality of second openings.
4. The dual pattern etching method according to claim 3, wherein the top surface of the spacer material layer comprises: the first top surface is positioned on the top surface of the first raised side wall material layer, and the second top surface is positioned in the first opening and is higher than the second top surface.
5. The dual pattern etching method of claim 2, wherein etching the sidewall material layer and the top silicon oxynitride mask layer to expose a top surface of the spin-on carbon mask layer comprises:
performing in-situ etching on the side wall material layer on the bottom surface of the first opening and the top surface of the first protrusion through a first etching process to expose the top surface of the top silicon oxynitride mask layer and the bottom surface of the second opening; and
and carrying out in-situ etching on the exposed top silicon oxynitride mask layer through a second etching process so as to remove the top silicon oxynitride mask layer.
6. The double pattern etching method according to claim 5, wherein the etchant used in the first etching process and the second etching process comprises: CF (compact flash)4And CHF3。
7. The double pattern etching method according to claim 6,
in the first etching process, CF4Gas flow of greater than CHF3The gas flow rate of (a); and
in the second etching process, CF4Flow rate of gasLess than CHF3The gas flow rate of (2).
8. The double pattern etching method according to claim 1, wherein the spin-on carbon mask layer is removed by an etching process:
ex-situ etching the exposed spin-on carbon mask layer with an etchant comprising N to form a first trench exposing a third top surface of the bottom mask layer in the photoresist stripping chamber2、He、H2、H2N2Ar and CF4Any one of (1) and O2Plasma is generated.
9. The dual pattern etching method of claim 8, wherein during the etching of the top silicon oxynitride mask layer and the spin-on carbon mask layer, the bottom mask layer in the second opening is partially etched to form a second trench, the bottom mask layer is partially recessed to expose a fourth top surface of the partially recessed bottom mask layer, wherein the fourth top surface is lower than the third top surface, and a sidewall material layer protrusion is disposed between the first trench and the second trench.
10. The double pattern etching method according to claim 9, further comprising:
and etching the bottom mask layer, the second hard mask layer and the first hard mask layer in the first groove and the second groove by taking the side wall material layer protrusion as a mask to form the capacitor hole, wherein the second hard mask layer is made of amorphous carbon, and the first hard mask layer is made of oxide.
11. A method of manufacturing a DRAM, comprising:
forming a capacitor hole using the double pattern etching method as claimed in any one of claims 1 to 10;
forming a lower electrode inside the capacitor hole;
removing the side wall material layer, the bottom masking layer, the second hard masking layer and the first hard masking layer outside the lower electrode; and
and sequentially forming a capacitance dielectric layer and an upper electrode inside and outside the capacitor hole.
12. The method of manufacturing a DRAM of claim 11, wherein a material of the lower electrode and the upper electrode includes TaN or TiN.
CN202011173181.XA 2020-10-28 2020-10-28 Double-pattern etching method and DRAM manufacturing method Pending CN114420548A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202011173181.XA CN114420548A (en) 2020-10-28 2020-10-28 Double-pattern etching method and DRAM manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202011173181.XA CN114420548A (en) 2020-10-28 2020-10-28 Double-pattern etching method and DRAM manufacturing method

Publications (1)

Publication Number Publication Date
CN114420548A true CN114420548A (en) 2022-04-29

Family

ID=81260364

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202011173181.XA Pending CN114420548A (en) 2020-10-28 2020-10-28 Double-pattern etching method and DRAM manufacturing method

Country Status (1)

Country Link
CN (1) CN114420548A (en)

Similar Documents

Publication Publication Date Title
CN108550569B (en) Capacitor device of semiconductor integrated circuit and manufacturing method thereof
KR20020039839A (en) Method for Fabricating of Semiconductor device
US20230012863A1 (en) Mask structure, semiconductor structure and methods for manufacturing same
US11889676B2 (en) Method for manufacturing capacitor, capacitor array structure and semiconductor memory
US8143163B2 (en) Method for forming pattern of semiconductor device
WO2022160632A1 (en) Method for manufacturing semiconductor structure
CN113097145A (en) Preparation method of semiconductor structure and semiconductor structure
CN114334619A (en) Method for forming semiconductor structure
CN114420548A (en) Double-pattern etching method and DRAM manufacturing method
WO2023000657A1 (en) Semiconductor structure and preparation method therefor
CN114823323A (en) Hard mask and preparation method thereof, and preparation method of semiconductor structure
US6475919B2 (en) Method for producing trenches for DRAM cell configurations
US9230967B2 (en) Method for forming self-aligned isolation trenches in semiconductor substrate and semiconductor device
CN111341725B (en) Method for manufacturing semiconductor pattern
TWI530992B (en) Semiconductor substrate to define reticle-free bit line trenches and method for fabricating the same
US20230038593A1 (en) Method for fabricating semiconductor device and semiconductor device
US20220320099A1 (en) Method for manufacturing a semiconductor structure and semiconductor structure
WO2021233269A1 (en) Semiconductor device holes, semiconductor device preparation method, and semiconductor device
KR100388453B1 (en) Method for fabricating capacitor
US20240178267A1 (en) Capacitor and fabricating method thereof
US20220246617A1 (en) Method for manufacturing semiconductor structure and semiconductor structure
CN111180386B (en) Semiconductor device mesoporous structure and forming method thereof
US20220044940A1 (en) Semiconductor structure and manufacturing method thereof
CN114975285A (en) Manufacturing method of bit line contact hole and DRAM
CN114093833A (en) Contact hole and DRAM manufacturing method

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination