CN114420065B - Driving circuit, driving method thereof and display device - Google Patents
Driving circuit, driving method thereof and display device Download PDFInfo
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- CN114420065B CN114420065B CN202011174618.1A CN202011174618A CN114420065B CN 114420065 B CN114420065 B CN 114420065B CN 202011174618 A CN202011174618 A CN 202011174618A CN 114420065 B CN114420065 B CN 114420065B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
Abstract
The invention provides a driving circuit, a driving method thereof and a display device, and relates to the technical field of circuits. A driving circuit includes: the level conversion module is configured to respectively perform level conversion on a first frame start signal of the frame start signal line and a first gate clock signal of the gate clock signal line to obtain a second frame start signal and a second gate clock signal, and provide the second gate clock signals for a plurality of first nodes under the control of the second frame start signal; the control module is configured to provide a second gate clock signal to the gate driving module under control of the voltage of the first node, and simultaneously provide a common voltage signal of the common voltage signal line to the display panel; the gate driving module is configured to transmit a gate driving signal to the display panel under control of the second gate clock signal. The invention is suitable for manufacturing the driving circuit.
Description
Technical Field
The present invention relates to the field of circuit technologies, and in particular, to a driving circuit, a driving method thereof, and a display device.
Background
Liquid crystal displays (Liquid Crystal Display, LCD) have been widely used, but in the process of client authentication, the liquid crystal display often has a problem of power-on flashing, which greatly reduces user experience.
Disclosure of Invention
The embodiment of the invention provides a driving circuit, a driving method thereof and a display device.
In order to achieve the above purpose, the embodiment of the present invention adopts the following technical scheme:
in one aspect, there is provided a driving circuit applied to driving a display panel, the driving circuit including: : the device comprises a level conversion module, a control module and a grid driving module;
the level conversion module is respectively and electrically connected with a frame start signal line, a plurality of grid clock signal lines and a plurality of first nodes, and is configured to respectively perform level conversion on a first frame start signal of the frame start signal line and a first grid clock signal of the grid clock signal line to obtain a second frame start signal and a second grid clock signal, and provide the second grid clock signal for the plurality of first nodes under the control of the second frame start signal;
the control module is electrically connected with the first nodes, the common voltage signal line, the grid driving module and the display panel respectively, and is configured to provide the second grid clock signal for the grid driving module under the control of the voltage of the first nodes and simultaneously provide the common voltage signal of the common voltage signal line for the display panel;
the grid driving module is respectively and electrically connected with the control module and the display panel and is configured to transmit a grid driving signal to the display panel under the control of the second grid clock signal.
Optionally, the control module comprises a plurality of groups of sub-modules, and the sub-modules comprise a first control sub-module and a second control sub-module;
in each group of the sub-modules, the first control sub-module and the second control sub-module are electrically connected with the same first node;
the input end of the first control sub-module is electrically connected with the first node, the output end of the first control sub-module is electrically connected with the grid driving module, and the first control sub-module is configured to provide the second grid clock signal for the grid driving module under the control of the voltage of the first node;
the second control submodule comprises a switch unit, the switch unit comprises a control end, a first end and a second end, the control end is electrically connected with the first node, the first end is electrically connected with the common voltage signal line, the second end is electrically connected with the display panel, and the second end is configured to provide the common voltage signal for the display panel under the control of the voltage of the first node.
Optionally, the switching unit includes a field effect transistor, a control electrode of the field effect transistor is used as the control terminal, a first electrode is used as the first terminal, and a second electrode is used as the second terminal.
Optionally, the field effect transistor includes an N-type thin film transistor or a P-type thin film transistor.
Optionally, the second control submodule further includes a first zero ohm resistor, and two ends of the first zero ohm resistor are respectively connected with the first node and the control end of the switch unit.
Optionally, the second control submodule further includes a first zero ohm resistor, and two ends of the first zero ohm resistor are respectively connected with the first node and the control end of the switch unit.
Optionally, the first control submodule further includes a second zero ohm resistor, and two ends of the second zero ohm resistor are respectively connected with the input end and the output end of the first control submodule.
Optionally, the number of groups of the submodules is the same as the number of clock signal lines.
Optionally, the number of the groups of the sub-modules is four groups, six groups or eight groups.
Optionally, the driving circuit further includes: a time sequence control module and a public voltage driving module;
the time sequence control module is respectively and electrically connected with the frame start signal line and the grid clock signal lines and is configured to provide a first frame start signal for the frame start signal line and provide the first grid clock signal for the grid clock signal lines;
the common voltage module is electrically connected to the common voltage signal line and configured to provide the common voltage signal to the common voltage signal line.
In another aspect, there is provided a display apparatus including: the driving circuit.
In still another aspect, there is provided a driving method for driving the driving circuit described above, the method comprising:
a first frame start signal is input to a frame start signal line, a first gate clock signal is input to a plurality of gate clock signal lines, and a common voltage signal is input to a common voltage signal line.
The embodiment of the invention provides a driving circuit, a driving method thereof and a display device, wherein the driving circuit is applied to driving a display panel and comprises a level conversion module, a control module and a grid driving module; the level conversion module is respectively and electrically connected with a frame start signal line, a plurality of grid clock signal lines and a plurality of first nodes, and is configured to respectively perform level conversion on a first frame start signal of the frame start signal line and a first grid clock signal of the grid clock signal line to obtain a second frame start signal and a second grid clock signal, and provide the second grid clock signal for the plurality of first nodes under the control of the second frame start signal; the control module is electrically connected with the first nodes, the common voltage signal line, the grid driving module and the display panel respectively, and is configured to provide the second grid clock signal for the grid driving module under the control of the voltage of the first nodes and simultaneously provide the common voltage signal of the common voltage signal line for the display panel; the grid driving module is respectively and electrically connected with the control module and the display panel and is configured to transmit a grid driving signal to the display panel under the control of the second grid clock signal.
In this way, the control module can provide the second gate clock signal to the gate driving module and simultaneously provide the common voltage signal to the display panel; the second grid clock signal can control the grid driving signal at the same time, so that the grid driving signal and the common voltage signal are transmitted to the display panel at the same time; therefore, the problem of poor white flash caused by the fact that the common voltage signal is started earlier than the grid driving signal in the related art is solved, the product quality is improved, and the user experience is improved.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a timing diagram of signals according to an embodiment of the present invention;
FIG. 2 is a timing diagram of another signal according to an embodiment of the present invention;
FIG. 3 is a timing diagram of a signal with a sparkling problem according to an embodiment of the present invention;
FIG. 4 is a signal timing diagram for solving the problem of white flash according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a driving circuit according to an embodiment of the present invention;
FIG. 6 is a timing diagram of the signals of FIG. 5;
FIG. 7 is a timing diagram of another signal of FIG. 5.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the embodiments of the present invention, the words "first," "second," and the like are used to distinguish between the same item or similar items that have substantially the same function and function, and are merely used to clearly describe the technical solutions of the embodiments of the present invention, and are not to be construed as indicating or implying relative importance or implying that the number of technical features indicated is indicated.
In the embodiments of the present invention, the meaning of "plurality" is two or more, and the meaning of "plurality" is two or more, unless specifically defined otherwise.
In the verification process of a client, a display (MNT) project product often has the problem of starting up and flashing, and the product quality and the user experience are greatly reduced. The inventors found after careful analysis that: referring to fig. 1, in the liquid crystal display having the problem of the flash, a common voltage signal (VCOM signal) is turned on at time t1, a gate driving signal (G-OUT signal) is turned on at time t2, and the common voltage signal is turned on about 335ms earlier than the gate driving signal; during this time (time period t1-t 2), since the thin film transistor (Thin Film Transistor, TFT) is not turned on, the data voltage (Source data) cannot enter the thin film transistor (i.e., the Source output signal is not turned on in fig. 1); then, only the common voltage (Vcom) is applied across the liquid crystal, and the voltage difference across the liquid crystal is the largest, and the screen is displayed as a white screen (ADS type liquid crystal screen), and the backlight is not turned on, but the flash Bai Bu is good under the irradiation of the external ambient light. Meanwhile, the VDD1 signal (GOA noise reduction power supply voltage signal) is turned on synchronously with the VCOM signal, or turned on after the VCOM signal (in fig. 2, the VDD1 signal is turned on at time T2, and the VDD1 signal is turned on after the VCOM signal is shown as an example), then, referring to fig. 3, if the GOA noise reduction operation is performed during the flash period (in the T1 period) (in fig. 3, GOA noise reduction is performed during the T2 period as an example), a black line phenomenon may also occur.
In order to solve the above-described problems, an embodiment of the present invention provides a driving circuit applied to driving a display panel, as shown with reference to fig. 5, including: a level conversion module 1, a control module 2 and a gate driving module 3.
The level conversion module 1 is electrically connected to a frame start signal line (STV line), a plurality of gate clock signal lines, and a plurality of first nodes, and is configured to perform level conversion on a first frame start signal of the frame start signal line and a first gate clock signal of the gate clock signal line, respectively, to obtain a second frame start signal and a second gate clock signal, and provide the second gate clock signal to the plurality of first nodes under control of the second frame start signal.
In fig. 5, taking 4 gate clock signal lines (including clk1_in line, clk2_in line, clk3_in line, and clk4_in line) as an example, the level conversion module performs level conversion on the first frame start signal of the STV line and the first gate clock signal of the 4 gate clock signal lines, respectively, to obtain a second frame start signal and 4 second gate clock signals clk1_out, clk2_out, clk3_out, and clk4_out. The second frame start signal is generated within the level shift module and does not need to be output externally, not shown in fig. 5.
The Level Shift module may include a Level Shift (Level Shift) circuit, and the specific circuit of the Level Shift circuit is not limited herein. The level conversion module may be disposed on the driving circuit board alone or may be integrated in a driving chip, which may be a P-Gamma IC (programmable Gamma chip), for example.
The level conversion module can be used for level conversion, and can convert a low level signal into a high level signal or convert a high level signal into a low level signal, which is not limited herein.
Referring to fig. 5, the control module 2 is electrically connected to a plurality of first nodes N1, a common voltage signal line (vcom_in line), the gate driving module 3, and the display panel 4, respectively, and is configured to supply a second gate clock signal to the gate driving module 3 while supplying a common voltage signal (vcom_in signal) of the common voltage signal line (vcom_in line) to the display panel 4 under control of the voltage of the first node N1. In fig. 5, the gate driving module 3 is shown by taking 4 second gate clock signals clk1_goa, clk2_goa, clk3_goa, clk4_goa as an example.
The specific circuit configuration of the control module is not limited herein.
Referring to fig. 5, the gate driving module 3 is electrically connected to the control module 2 and the display panel 4, respectively, and is configured to transmit a gate driving signal to the display panel under the control of a second gate clock signal. In fig. 5, the display panel 4 is shown by way of example with 4 gate driving signals g_out1, g_out2, g_out3, and g_out4.
The gate driving module may include a GOA (Gate Driver on Array, array substrate row driving) circuit capable of generating gate driving signals.
Note that, referring to fig. 5, the display panel 4 includes a liquid crystal (not shown in fig. 5), a pixel electrode, a common electrode 11, a plurality of thin film transistors 10, a plurality of Gate lines (Gate lines), and a plurality of Data lines (Data lines); the grid lines and the data lines transversely and longitudinally intersect to form a plurality of limiting areas; the thin film transistor is located in the limited area and comprises a grid electrode, a source electrode and a drain electrode, wherein the drain electrode is electrically connected with the pixel electrode, and the source electrode is electrically connected with the data line. Referring to fig. 5, the display panel includes a plurality of subpixels arranged in an array, and the subpixels may be R (red), G (green), and B (blue) subpixels. Fig. 5 illustrates an example in which the display panel includes 4 rows and 4 columns of subpixels, 4 gate lines, and 4 data lines. In addition, specific shapes of the pixel electrode and the common electrode are not limited herein. For example, the common electrode is disposed entirely and electrically connected to the common voltage signal line. Of course, referring to fig. 5, the driving circuit may further include a source driving module 7, and the source driving module 7 is electrically connected to the display panel and is capable of providing Data signals (Data 1-Data4 signals) to the Data lines of the display panel.
The gate driving module is configured to transmit a gate driving signal to a plurality of gate lines of the display panel under the control of a second gate clock signal to turn on the thin film transistor so that a data voltage signal of the data line is written into the pixel electrode; meanwhile, the control module is configured to provide a common voltage signal to the common electrode of the display panel under the control of the voltage of the first node. Therefore, a pressure difference is formed between the pixel electrode and the common electrode, so that liquid crystal of the display panel is driven to deflect, and display of different pictures is realized.
The principle of the driving circuit for solving the problem of poor flashing white and poor black line is as follows: referring to fig. 4, the common voltage signal (VCOM signal) is turned on with a delay so that the common voltage signal and the gate driving signal (G-OUT signal) are turned on at the same time, thereby avoiding occurrence of a sparkling defect; meanwhile, the VDD1 signal is kept normally on, and the black line occurs in a period T2 in which the common voltage signal is not on (before time T1 shown in fig. 4), and the black line is not visible because there is no flashing phenomenon in this period.
The embodiment of the invention provides a driving circuit, which can provide a second grid clock signal for a grid driving module through a control module and simultaneously provide a common voltage signal for a display panel; the second grid clock signal can control the grid driving signal at the same time, so that the grid driving signal and the common voltage signal are transmitted to the display panel at the same time; thus solving the problem of poor white flash caused by the fact that the common voltage signal is started earlier than the grid driving signal in the related art; meanwhile, the problem of bad black lines caused by GOA noise reduction action in the flashing period in the related technology is solved; thereby greatly improving the product quality and improving the user experience.
Optionally, in order to reduce the difficulty of circuit design, referring to fig. 5, the control module 2 includes multiple groups of sub-modules, where the sub-modules include a first control sub-module 21 and a second control sub-module 22.
Referring to fig. 5, in each group of sub-modules, a first control sub-module 21 and a second control sub-module 22 are electrically connected to the same first node N1.
As shown in fig. 5, the input terminal of the first control sub-module 21 is electrically connected to the first node N1, and the output terminal is electrically connected to the gate driving module 3, and is configured to provide the second gate clock signal to the gate driving module under the control of the voltage of the first node.
The second control submodule comprises a switch unit, the switch unit comprises a control end, a first end and a second end, the control end is electrically connected with the first node, the first end is electrically connected with the common voltage signal line, the second end is electrically connected with the display panel, and the switch unit is configured to provide a common voltage signal for the display panel under the control of the voltage of the first node.
Fig. 5 illustrates an example in which the control module 2 includes 4 sub-modules. Referring to fig. 5, the switching units may be thin film transistors TFT, respectively denoted as T1, T2, T3, T4. The control end of the switch unit can be directly connected with the first node to realize electric connection; alternatively, the thin film transistor T1 (as a switching unit) may be electrically connected to the first node N1 by other elements, for example, as shown in fig. 5, by being connected to a zero ohm (0Ω) resistor, and the zero ohm resistor may be connected to the first node N1, thereby electrically connecting the thin film transistor T1 to the first node N1.
Referring to fig. 5, IN the second control sub-module 22, a gate G (as a control terminal) of the thin film transistor T1 is electrically connected to the first node N1, a source S (as a first terminal) is electrically connected to a common voltage signal line (vcom_in line), a drain D (as a second terminal) is electrically connected to the common electrode 11 of the display panel 4, and is configured to provide a common voltage signal (vcom_out signal) to the display panel 4 under control of the voltage of the first node N1.
The number of the groups of the sub-modules is the same as the number of the first nodes, one first node controls one group of the sub-modules, and different first nodes control different sub-modules.
The first control submodule can provide a second gate clock signal for the gate driving module under the control of the voltage of the first node; the second control sub-module can provide a common voltage signal to the display panel under the control of the voltage of the first node. Namely, under the condition that the first node controls the first control sub-module, the second control sub-module is added, so that the voltage of the first node can control the output of the first control sub-module and the output of the second control sub-module simultaneously. The circuit has simple design structure, small change to the original driving circuit and is beneficial to reducing the cost and the manufacturing difficulty.
Optionally, the switching unit includes a field effect transistor, where a control electrode of the field effect transistor is used as a control terminal, a first electrode is used as a first terminal, and a second electrode is used as a second terminal.
The field effect transistor can be a MOSFET (Metal Oxide Semiconductor Field Effect Transistor ) transistor, which is called MOS transistor for short; alternatively, other types of field effect transistors are not limited herein. The control electrode of the field effect transistor may be a gate electrode, the first electrode may be a source electrode, and the second electrode may be a drain electrode.
The field effect transistor may include an N-type thin film transistor (Thin Film Transistor, TFT) or a P-type thin film transistor.
The N-type thin film transistor and the P-type thin film transistor have different conduction conditions, the former is conducted at a high level, and the latter is conducted at a low level. The specific use of an N-type or P-type thin film transistor depends on the second gate clock signal.
Optionally, referring to fig. 5, for facilitating subsequent testing and finding of the fault point, the second control sub-module 22 further includes a first zero ohm resistor (0Ω), two ends of the first zero ohm resistor being connected to the first node N1 and the control terminal (G-pole of T1 in fig. 5) of the switching unit, respectively.
Optionally, referring to fig. 5, for facilitating subsequent testing and finding of fault points, the first control sub-module 21 further includes a second zero ohm resistor (0Ω), two ends of the second zero ohm resistor being connected to an input (not labeled in fig. 5) and an output (not labeled in fig. 5) of the first control sub-module, respectively.
It should be noted that the zero ohm resistor is also called a crossover resistor, and is a resistor with a specific purpose, and its resistance value is not zero. In practice, zero ohm resistance is a resistance with a very small resistance value. The first zero ohm resistor and the second zero ohm resistor can be identical in model number, and the first node can control the first control sub-module and the second control sub-module simultaneously.
Optionally, the number of groups of the sub-modules is the same as the number of the gate clock signal lines, so as to fully utilize the gate clock signals of the gate clock signal lines.
Further optionally, the number of groups of the sub-modules is four, six or eight. At this time, the gate clock signal lines may correspond to four, six, or eight lines, respectively. In fig. 5, four groups of sub-modules are shown as an example, and at this time, the driving module may drive the display panel by using a 4clock (4 clock signals) method.
Optionally, referring to fig. 5, the driving circuit further includes: a timing control module 5 and a common voltage driving module 6.
As shown in fig. 5, the timing control module 5 is electrically connected to a frame start signal line (STV line) and a plurality of gate clock signal lines (clk1_in line, clk2_in line, clk3_in line, clk4_in line), respectively, and is configured to supply a first frame start signal (STV signal) to the frame start signal line and a first gate clock signal to the plurality of gate clock signal lines.
Referring to fig. 5, the common voltage module 6 is electrically connected to a common voltage signal line (vcom_in line) configured to supply a common voltage signal (vcom_in signal) to the common voltage signal line.
The timing control module may include a timing controller (Tcon); the common voltage module may include a DC/DC (direct current/direct current) converter, or may further include a P-Gamma IC (programmable Gamma chip). If the common voltage module includes a P-Gamma IC, the level shift module may be integrated into the P-Gamma IC.
In another aspect, an embodiment of the present invention further provides a display apparatus, including: the driving circuit.
The display device may be an LCD (Liquid Crystal Display ) display device, for example: ADS (Advanced Super Dimension Switch, advanced super-dimensional field switching) liquid crystal display devices; or any product or component with display function, such as a television, a digital camera, a mobile phone, a tablet computer and the like, comprising the display device. The display device can solve the problem of poor flashing caused by the fact that common voltage signals are started earlier than grid driving signals in the related art; meanwhile, the problem of bad black lines caused by GOA noise reduction action in the flashing period in the related technology can be solved; the method has the characteristics of high product quality and good user experience.
In still another aspect, an embodiment of the present invention further provides a driving method for driving the driving circuit, where the method includes:
a first frame start signal is input to the frame start signal line, a first gate clock signal is input to the plurality of gate clock signal lines, and a common voltage signal is input to the common voltage signal line.
The driving method and the circuit operation principle will be specifically described below by taking the driving circuit shown in fig. 5 as an example. In fig. 5, the example of the display panel includes 4 rows and 4 columns of sub-pixels, in which the control module includes 4 groups of sub-modules, and the gate clock signal lines are 4.
As shown in fig. 5 to 7, the timing control module 5 supplies the first frame start signal to the frame start signal line and supplies 4 first gate clock signals to the 4 gate clock signal lines. The level conversion module 1 performs level conversion on the first frame start signal of the frame start signal line and the first gate clock signal of the gate clock signal line, respectively, to obtain a second frame start signal (STV 1 signal) and 4 second gate clock signals (clk1_out, clk2_out, clk3_out, and clk4_out), and provides the second gate clock signals to the 4 first nodes N1 under the control of the second frame start signal.
The 4 second gate clock signals (clk1_out, clk2_out, clk3_out, and clk4_out) are respectively transmitted to the G poles of the thin film transistors T1-T4 through zero ohm resistances of the second modules in the 4 groups of sub-modules, and the signals of the G poles of the thin film transistors T1-T4 can be respectively marked as CLK1-CLK4; under the control of the CLK1-CLK4 signals, the thin film transistors T1-T4 are turned on IN sequence, thereby transmitting the common voltage signal vcom_in signal of the common voltage driving module 6 to the common electrode 11 of the display panel 4. The voltage signal output by the drain D of the thin film transistors T1-T4 may be labeled VCOM_OUT, wherein the timing diagrams of the signals CLK1-CLK4, VCOM_IN, VCOM_OUT may be as shown with reference to FIG. 6, with the VCOM_OUT signal being delayed relative to the VCOM_IN signal under the control of the CLK1-CLK4 signal.
Meanwhile, the 4 second gate clock signals (clk1_out, clk2_out, clk3_out and clk4_out) are respectively transmitted to the output terminals through zero ohm resistances of the first module in the 4 groups of sub-modules, and at this time, the output signals of the 4 output terminals can be respectively marked as clk1_goa-clk4_goa; the 4 output terminals transmit the output signals to the gate driving module 3, and the gate driving module 3 processes the clk1_goa-clk4_goa signals and outputs g_out1-g_out4 to the 4 gate lines of the display panel 4, respectively, thereby completing the row scanning. The signal timing diagrams of clk1_goa-clk4_goa, g_out1-g_out4, and STV1 may refer to fig. 7, where after STV1 is turned on, clk1_goa-clk4_goa controls g_out1-g_out4, respectively, and the clk1_goa signal and g_out1 are turned on simultaneously, the clk2_goa signal and g_out2 are turned on simultaneously, and the clk3_goa signal and g_out3 are turned on simultaneously, and the clk4_goa signal and g_out4 are turned on simultaneously.
In the group 1 submodule, the CLK1 signal and the clk1_goa signal are generated synchronously, and the CLK1 signal can synchronously control the vcom_outsignal, and the clk1_goa signal can synchronously control the g_out1 signal, so that the vcom_out1 signal and the g_out1 signal are synchronously turned on. The other group of sub-modules provide G_OUT2-G_OUT4 in turn, and maintain the VCOM_OUT signal active, respectively, under the control of CLK2 OUT-CLK4 OUT. It should be noted that, in fig. 5, the 4 groups of sub-modules included in the control module are respectively referred to as 1 st-4 th groups of sub-modules from top to bottom.
In this way, the control module can provide the second gate clock signal to the gate driving module and simultaneously provide the common voltage signal to the display panel; the second grid clock signal can control the grid driving signal at the same time, so that the grid driving signal and the common voltage signal are transmitted to the display panel at the same time; thus solving the problem of poor white flash caused by the fact that the common voltage signal is started earlier than the grid driving signal in the related art; meanwhile, the problem of bad black lines caused by GOA noise reduction action in the flashing period in the related technology is solved; thereby greatly improving the product quality and improving the user experience.
The foregoing is merely illustrative embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily think about variations or substitutions within the technical scope of the present invention, and the invention should be covered. Therefore, the protection scope of the invention is subject to the protection scope of the claims.
Claims (11)
1. A driving circuit for driving a display panel, the driving circuit comprising: the device comprises a level conversion module, a control module and a grid driving module;
the level conversion module is respectively and electrically connected with a frame start signal line, a plurality of grid clock signal lines and a plurality of first nodes, and is configured to respectively perform level conversion on a first frame start signal of the frame start signal line and a first grid clock signal of the grid clock signal line to obtain a second frame start signal and a second grid clock signal, and provide the second grid clock signal for the plurality of first nodes under the control of the second frame start signal;
the control module is electrically connected with the first nodes, the common voltage signal line, the grid driving module and the display panel respectively, and is configured to provide the second grid clock signal for the grid driving module under the control of the voltage of the first nodes and simultaneously provide the common voltage signal of the common voltage signal line for the display panel;
the grid driving module is respectively and electrically connected with the control module and the display panel and is configured to transmit a grid driving signal to the display panel under the control of the second grid clock signal;
the common voltage signal and the gate driving signal are simultaneously transmitted to the display panel.
2. The drive circuit of claim 1, wherein the control module comprises a plurality of groups of sub-modules, the sub-modules comprising a first control sub-module and a second control sub-module;
in each group of the sub-modules, the first control sub-module and the second control sub-module are electrically connected with the same first node;
the input end of the first control sub-module is electrically connected with the first node, the output end of the first control sub-module is electrically connected with the grid driving module, and the first control sub-module is configured to provide the second grid clock signal for the grid driving module under the control of the voltage of the first node;
the second control submodule comprises a switch unit, the switch unit comprises a control end, a first end and a second end, the control end is electrically connected with the first node, the first end is electrically connected with the common voltage signal line, the second end is electrically connected with the display panel, and the second end is configured to provide the common voltage signal for the display panel under the control of the voltage of the first node.
3. The drive circuit according to claim 2, wherein the switching unit comprises a field effect transistor, a control electrode of the field effect transistor serving as the control terminal, a first electrode serving as the first terminal, and a second electrode serving as the second terminal.
4. A driving circuit according to claim 3, wherein the field effect transistor comprises an N-type thin film transistor or a P-type thin film transistor.
5. The drive circuit of claim 2, wherein the second control sub-module further comprises a first zero ohm resistor, two ends of the first zero ohm resistor being connected to the first node and the control terminal of the switching unit, respectively.
6. The drive circuit of claim 2, wherein the first control sub-module further comprises a second zero ohm resistor, two ends of the second zero ohm resistor being connected to the input terminal and the output terminal of the first control sub-module, respectively.
7. The drive circuit according to claim 2, wherein the number of groups of the submodules is the same as the number of gate clock signal lines.
8. The driving circuit according to claim 7, wherein the number of groups of the sub-modules is four groups, six groups or eight groups.
9. The drive circuit of claim 1, wherein the drive circuit further comprises: a time sequence control module and a public voltage driving module;
the time sequence control module is respectively and electrically connected with the frame start signal line and the grid clock signal lines and is configured to provide a first frame start signal for the frame start signal line and provide the first grid clock signal for the grid clock signal lines;
the common voltage driving module is electrically connected to the common voltage signal line and configured to supply the common voltage signal to the common voltage signal line.
10. A display device comprising the drive circuit of any one of claims 1-9.
11. A driving method for driving the driving circuit according to any one of claims 1 to 9, characterized in that the method comprises:
a first frame start signal is input to a frame start signal line, a first gate clock signal is input to a plurality of gate clock signal lines, and a common voltage signal is input to a common voltage signal line.
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| CN114420065A (en) | 2022-04-29 |
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