CN114417261A - Device and method for verifying Hash algorithm - Google Patents
Device and method for verifying Hash algorithm Download PDFInfo
- Publication number
- CN114417261A CN114417261A CN202111674558.4A CN202111674558A CN114417261A CN 114417261 A CN114417261 A CN 114417261A CN 202111674558 A CN202111674558 A CN 202111674558A CN 114417261 A CN114417261 A CN 114417261A
- Authority
- CN
- China
- Prior art keywords
- operation result
- hash algorithm
- sub
- random number
- comparator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/18—Complex mathematical operations for evaluating statistical data, e.g. average values, frequency distributions, probability functions, regression analysis
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Data Mining & Analysis (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Life Sciences & Earth Sciences (AREA)
- Operations Research (AREA)
- Probability & Statistics with Applications (AREA)
- Bioinformatics & Cheminformatics (AREA)
- Algebra (AREA)
- Evolutionary Biology (AREA)
- Databases & Information Systems (AREA)
- Software Systems (AREA)
- General Engineering & Computer Science (AREA)
- Bioinformatics & Computational Biology (AREA)
- Debugging And Monitoring (AREA)
Abstract
The invention provides a device and a method for verifying a Hash algorithm, wherein the device comprises the following steps: an excitation transmitter configured to output a random number; the function model is connected with the excitation transmitter, is provided with a first Hash algorithm written by a software programming language, is configured to receive the random number, obtains a first operation result by the operation of the random number through the first Hash algorithm, and outputs the first operation result; the device to be tested is connected with the excitation transmitter, is provided with a second Hash algorithm written by a hardware description language, is configured to receive the random number, obtains a second operation result by operating the random number through the second Hash algorithm, and outputs the second operation result; and the comparator is respectively connected with the functional model and the device to be tested, is configured to receive the first operation result and the second operation result, and compares the first operation result and the second operation result to verify the second Hash algorithm based on the comparison result. The invention improves the verification efficiency and reliability of the hash algorithm in the aspect of hardware.
Description
Technical Field
The invention relates to the technical field of algorithms, in particular to a device and a method for verifying a hash algorithm.
Background
The hash algorithm is a widely used digest algorithm, which obtains a message digest with a fixed length from a plaintext with an arbitrary length by the hash algorithm. Common Hash algorithms include MD series, SHA (Secure Hash Algorithm) series, and HMAC (Hash-based Message Authentication Code) Algorithm based on the MD series and the SHA series. In view of security, many SoC chips (system on chip) have algorithm modules integrated therein.
The hash algorithm is mostly realized by a software programming language, and is relatively mature in software. In terms of hardware, the traditional hash algorithm verification is a simple verification platform built based on Verilog HDL language (a hardware description language), and directly writes an excitation, collects output and compares the excitation with standard output data to judge whether the data set is consistent according to verified input and output. The method for verifying the Hash algorithm is low in efficiency, limited in data used for verification, insufficient in verification and difficult in coverage rate meeting requirements.
Disclosure of Invention
In view of the above, the present invention is to provide a device and a method for verifying a hash algorithm, so as to solve the problems of poor verification reliability and low verification efficiency when the hash algorithm is verified in hardware in the prior art.
Based on the above object, the present invention provides a device for verifying a hash algorithm, comprising:
an excitation transmitter configured to output a random number;
the function model is connected with the excitation transmitter, is provided with a first Hash algorithm written by a software programming language and is configured for receiving the random number, operating the random number through the first Hash algorithm to obtain a first operation result and outputting the first operation result;
the device to be tested is connected with the excitation transmitter, is provided with a second Hash algorithm written by a hardware description language and is configured to receive the random number, obtain a second operation result by operating the random number through the second Hash algorithm and output the second operation result; and
and the comparator is respectively connected with the functional model and the device to be tested, is configured to receive the first operation result and the second operation result, and compares the first operation result with the second operation result so as to verify the second Hash algorithm based on the comparison result.
In some embodiments, the apparatus further comprises:
and the input end of the driver is connected with the excitation transmitter, the output end of the driver is connected with the device to be tested through the bus, and the driver is configured to receive the random numbers and sequentially transmit the random numbers with preset amount in the random numbers to the device to be tested through the bus.
In some embodiments, the apparatus further comprises:
and the input monitor is connected with the functional model, is configured to monitor the random number on the bus, and responds to the monitoring of the random number of the current preset quantity, and sends the random number of the current preset quantity to the functional model.
In some embodiments, the functional model is further configured to operate the received current preset amount of random numbers through a first hash algorithm to obtain a first sub-operation result, and send the first sub-operation result to the comparator.
In some embodiments, the device under test is further configured to perform a second hash algorithm operation on the received random numbers of the current preset amount to obtain a second sub-operation result, and output the second sub-operation result.
In some embodiments, the apparatus further comprises:
and the input end of the output monitor is connected with the device to be tested through a bus, the output end of the output monitor is connected with the comparator, and the output monitor is configured to receive the second sub-operation result and send the second sub-operation result to the comparator.
In some embodiments, the comparator is further configured to compare the plurality of pairs of the first sub-operation result and the second sub-operation result respectively to obtain a plurality of comparison results, so as to verify the second hash algorithm based on the plurality of comparison results.
In some embodiments, the comparator is further configured to:
comparing whether the first sub-operation result and the second sub-operation result of each pair are consistent;
responding to the consistency of the first sub-operation result and the second sub-operation result to obtain a consistency result; or
Responding to the inconsistency of the first sub-operation result and the second sub-operation result to obtain a difference result;
respectively counting the number of consistency results and the number of difference results;
and confirming that the second hash algorithm passes the verification in response to the fact that the number of the consistency results is larger than that of the difference results and the difference value of the consistency results and the difference values exceeds a preset value.
In some embodiments, the software programming language includes at least the C language and the hardware description language includes at least the systemveilog language.
In another aspect of the present invention, a method for verifying a hash algorithm is further provided, which includes the following steps:
receiving a random number output by an excitation transmitter through a functional model, calculating the random number through a first Hash algorithm written by a software programming language to obtain a first calculation result, and transmitting the first calculation result to a comparator;
receiving the random number output by the excitation transmitter through the device to be tested, calculating the random number through a second Hash algorithm written by a hardware description language to obtain a second operation result, and transmitting the second operation result to the comparator;
the received first operation result is compared with the second operation result by the comparator to verify the second hash algorithm based on the comparison result.
The invention has at least the following beneficial technical effects:
the invention verifies the Hash algorithm in the device to be tested by adopting the excitation transmitter to output a large number of random numbers, ensures the sufficiency of verification, and can ensure higher coverage rate of verified data under the condition of wider data types and ranges of the random numbers; the device for verifying the Hash algorithm can realize reliable and effective verification, shortens the verification period and improves the verification efficiency compared with the traditional Hash algorithm verification method in the aspect of hardware.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
Fig. 1 is a schematic diagram of an apparatus for verifying a hash algorithm according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of an apparatus for verifying a hash algorithm according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a method for verifying a hash algorithm according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two non-identical entities with the same name or different parameters, and it is understood that "first" and "second" are only used for convenience of expression and should not be construed as limiting the embodiments of the present invention. Furthermore, the terms "comprises" and "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements does not include all of the other steps or elements inherent in the list.
In view of the above object, a first aspect of the embodiments of the present invention provides an embodiment of an apparatus for verifying a hash algorithm. Fig. 1 is a schematic diagram illustrating an embodiment of an apparatus for verifying a hash algorithm according to the present invention. As shown in fig. 1, an apparatus for verifying a hash algorithm according to an embodiment of the present invention includes:
an excitation transmitter 10 configured to output a random number;
the function model 20, the function model 20 is connected with the excitation transmitter 10, the function model 20 has a first hash algorithm written by a software programming language, and is configured to receive a random number, and the random number is operated by the first hash algorithm to obtain a first operation result, and the first operation result is output;
the device to be tested 30 is connected with the excitation transmitter 10, the device to be tested 30 is provided with a second Hash algorithm written by a hardware description language and is configured to receive the random number, the random number is operated by the second Hash algorithm to obtain a second operation result, and the second operation result is output; and
and the comparator 40, wherein the comparator 40 is respectively connected with the functional model 20 and the device under test 30, and is configured to receive the first operation result and the second operation result, and compare the first operation result with the second operation result to verify the second hash algorithm based on the comparison result.
The embodiment of the invention verifies the hash algorithm in the device to be tested 30 by adopting the excitation transmitter 10 to output a large number of random numbers, thereby ensuring the sufficiency of verification and ensuring higher coverage rate of verified data under the condition of wider data types and ranges of the random numbers; the device for verifying the hash algorithm can realize reliable and effective verification, shortens the verification period and improves the verification efficiency compared with the traditional hardware-aspect hash algorithm verification method.
In this embodiment, the random number may be any length and multiple types of message data, and may also be randomly combined within the constraint range.
Fig. 2 is a schematic structural diagram illustrating an apparatus for verifying a hash algorithm according to an embodiment of the present invention. As shown in fig. 2, in the embodiment of the present invention, a Verification platform development framework based on a Universal Verification Methodology (UVM) is adopted, and a Verification environment that is easy to reuse is built.
In some embodiments, the apparatus further comprises: and the driver, the input end of which is connected with the excitation transmitter 10 and the output end of which is connected with the device to be tested 30 through the bus, is configured to receive the random numbers and sequentially transmit the preset amount of random numbers in the random numbers to the device to be tested 30 through the bus.
In this embodiment, the driver (Drv in fig. 2) segments or packs the random numbers output by the excitation transmitter 10 (sequence or Seqr in fig. 2) according to a certain rule, and then sends a preset amount of segmented or packed random numbers to the bus each time, and further transmits the random numbers to the device under test 30 (DUT in fig. 2). The Bus is an AHB (Advanced High-performance Bus) Bus, which can be used as a system-on-chip Bus of an SoC (system on chip).
In some embodiments, the apparatus further comprises: and the input monitor is connected with the functional model 20, is configured to monitor the random numbers on the bus, and sends the random numbers of the current preset quantity to the functional model 20 in response to the monitoring of the random numbers of the current preset quantity.
In some embodiments, the functional model 20 is further configured to operate the received random number of the current preset amount by a first hash algorithm to obtain a first sub-operation result, and send the first sub-operation result to the comparator 40.
In the above embodiment, the input monitor (Mon in _ agent in fig. 2) is arranged to monitor data on the bus, and send the monitored data of the preset amount to the functional model 20 (model in fig. 2), and then the functional model 20 operates on the same random numbers of the preset amount, so that the random numbers used in each calculation in the functional model 20 and the device under test 30 are the same, and the ordering of the data and the reliability of the operation result are ensured. The input monitor may also monitor the correctness of the data at the time of interception. Therefore, the input monitor can ensure the orderliness and correctness of the data and avoid influencing the final comparison result.
In some embodiments, the device under test 30 is further configured to perform a second hash algorithm operation on the received random numbers of the current preset amount to obtain a second sub-operation result, and output the second sub-operation result.
In some embodiments, the apparatus further comprises: and the input end of the output monitor is connected with the device to be tested 30 through a bus, the output end of the output monitor is connected with the comparator 40, and the output monitor is configured to receive the second sub-operation result and send the second sub-operation result to the comparator 40.
In this embodiment, the output monitor (Mon in Out _ agent in fig. 2) is used to cooperate with the input monitor, the device under test 30 calculates the random number of the current preset amount by the second hash algorithm, and then sends the calculation result to the output monitor, and the output monitor is sent to the comparator 40 (Scb in fig. 2), thereby ensuring the reliability of the calculation.
In some embodiments, the comparator 40 is further configured to compare the pairs of the first sub-operation result and the second sub-operation result respectively to obtain a plurality of comparison results, so as to verify the second hash algorithm based on the plurality of comparison results.
In some embodiments, the comparator 40 is further configured to: comparing whether the first sub-operation result and the second sub-operation result of each pair are consistent; responding to the consistency of the first sub-operation result and the second sub-operation result to obtain a consistency result; or responding to the inconsistency of the first sub-operation result and the second sub-operation result to obtain a difference result; respectively counting the number of consistency results and the number of difference results; and confirming that the second hash algorithm passes the verification in response to the fact that the number of the consistency results is larger than that of the difference results and the difference value of the consistency results and the difference values exceeds a preset value.
In this embodiment, if the number of consistent results is much larger than the number of differential results, it indicates that the reliability of the second hash algorithm is better. The best condition is that each pair of the first sub-operation result and the second sub-operation result is consistent, and the hash algorithm written by the hardware description language achieves the same effect as written by the software language.
As shown in fig. 2, in this embodiment, a plurality of buffer units (fifo) are further provided for temporarily storing data.
In some embodiments, the software programming language includes at least the C language and the hardware description language includes at least the systemveilog language.
In this embodiment, the software programming language includes, but is not limited to, a C language, for example, a C + + language, a Python language, and the like. The hardware description language includes, but is not limited to, the SystemVerilog language. The SystemVerilog language, abbreviated as SV language, is a quite new language, is established on the basis of Verilog language, is an extended enhancement of IEEE 1364 Verilog-2001 standard, is compatible with Verilog2001, combines a Hardware Description Language (HDL) with a modern high-level verification language (HVL), and newly becomes a language for next-generation hardware design and verification.
In a second aspect of the embodiments of the present invention, a method for verifying a hash algorithm is also provided. Fig. 3 is a schematic diagram illustrating an embodiment of a method for verifying a hash algorithm provided in the present invention. As shown in fig. 3, a method of verifying a hash algorithm includes the steps of:
step S10, receiving the random number output by the excitation transmitter through the functional model, operating the random number through a first Hash algorithm written by a software programming language to obtain a first operation result, and transmitting the first operation result to the comparator;
step S20, receiving the random number output by the excitation transmitter through the device to be tested, calculating the random number through a second Hash algorithm written by a hardware description language to obtain a second operation result, and sending the second operation result to the comparator;
step S30, comparing the received first operation result with the second operation result through the comparator to verify the second hash algorithm based on the comparison result.
According to the method for verifying the hash algorithm, the excitation transmitter is adopted to output a large number of random numbers to verify the hash algorithm in the device to be tested, so that the completeness of verification is ensured, and the coverage rate of verified data is higher under the condition that the data type and range of the random numbers are wider; and moreover, reliable and effective verification can be realized, and compared with the traditional verification method, the verification period is shortened, and the verification efficiency is improved.
Finally, it should be noted that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.
The various illustrative logical blocks, modules, and circuits described in connection with the disclosure herein may be implemented or performed with the following components designed to perform the functions herein: a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP, and/or any other such configuration.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items. The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (10)
1. An apparatus for validating a hash algorithm, comprising:
an excitation transmitter configured to output a random number;
the function model is connected with the excitation transmitter, is provided with a first hash algorithm written by a software programming language and is configured to receive the random number, calculate the random number through the first hash algorithm to obtain a first operation result and output the first operation result;
the device to be tested is connected with the excitation transmitter, is provided with a second Hash algorithm written by a hardware description language and is configured to receive the random number, obtain a second operation result by operating the random number through the second Hash algorithm and output the second operation result; and
and the comparator is respectively connected with the functional model and the device to be tested, is configured to receive the first operation result and the second operation result, and compares the first operation result with the second operation result so as to verify the second hash algorithm based on the comparison result.
2. The apparatus of claim 1, further comprising:
and the input end of the driver is connected with the excitation transmitter, the output end of the driver is connected with the device to be tested through a bus, and the driver is configured to receive the random numbers and sequentially transmit the random numbers of preset amount in the random numbers to the device to be tested through the bus.
3. The apparatus of claim 2, further comprising:
and the input monitor is connected with the functional model, is configured to monitor the random numbers on the bus, and responds to the monitoring of the random numbers of the current preset quantity, and sends the random numbers of the current preset quantity to the functional model.
4. The apparatus of claim 3, wherein the functional model is further configured to perform a first hash algorithm operation on the received random numbers of the current preset amount to obtain a first sub-operation result, and send the first sub-operation result to the comparator.
5. The apparatus according to claim 4, wherein the device under test is further configured to perform a second hash algorithm operation on the received random numbers of the current preset amount to obtain a second sub-operation result, and output the second sub-operation result.
6. The apparatus of claim 5, further comprising:
and the input end of the output monitor is connected with the device to be tested through the bus, the output end of the output monitor is connected with the comparator, and the output monitor is configured to receive the second sub-operation result and send the second sub-operation result to the comparator.
7. The apparatus of claim 6, wherein the comparator is further configured to compare a plurality of pairs of the first sub-operation result and the second sub-operation result respectively to obtain a plurality of comparison results, and to verify the second hash algorithm based on the plurality of comparison results.
8. The apparatus of claim 7, wherein the comparator is further configured to:
comparing whether each pair of the first sub-operation result and the second sub-operation result is consistent;
responding to the first sub-operation result and the second sub-operation result to be consistent, and obtaining a consistency result; or
Obtaining a difference result in response to the first sub-operation result and the second sub-operation result being inconsistent;
respectively counting the number of the consistency results and the number of the difference results;
and confirming that the second hash algorithm is verified in response to the fact that the number of the consistency results is larger than the number of the difference results and the difference value of the consistency results and the difference values exceeds a preset value.
9. The apparatus of claim 1, wherein the software programming language comprises at least a C language and the hardware description language comprises at least a systemveilog language.
10. A method of validating a hash algorithm, comprising the steps of:
receiving a random number output by an excitation transmitter through a functional model, operating the random number through a first Hash algorithm written by a software programming language to obtain a first operation result, and transmitting the first operation result to a comparator;
receiving the random number output by the excitation transmitter through a device to be tested, calculating the random number through a second Hash algorithm written by a hardware description language to obtain a second operation result, and sending the second operation result to the comparator;
comparing, by the comparator, the received first operation result with the second operation result to verify the second hash algorithm based on a comparison result.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111674558.4A CN114417261A (en) | 2021-12-31 | 2021-12-31 | Device and method for verifying Hash algorithm |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111674558.4A CN114417261A (en) | 2021-12-31 | 2021-12-31 | Device and method for verifying Hash algorithm |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114417261A true CN114417261A (en) | 2022-04-29 |
Family
ID=81271457
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111674558.4A Pending CN114417261A (en) | 2021-12-31 | 2021-12-31 | Device and method for verifying Hash algorithm |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114417261A (en) |
-
2021
- 2021-12-31 CN CN202111674558.4A patent/CN114417261A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11303661B2 (en) | System and method for detection and prevention of attacks on in-vehicle networks | |
| CN104969468B (en) | It is verified using the integrated circuit identification of physics unclonable function and burn-in test circuit based on ring oscillator and reliability | |
| CN109634258B (en) | Bus message checking method, device and system for hardware-in-loop test | |
| CN112134762B (en) | Testing method, device, terminal and storage medium for block chain network structure | |
| CN106030605B (en) | Digital value processing device and method | |
| WO2022267233A1 (en) | Communication fault detection method, device and system based on redundant device | |
| CN103970634A (en) | Back-to-back loopback validation method for large-scale interconnection chips based on detection logic addition | |
| CN112380046A (en) | Calculation result checking method, system, device, equipment and storage medium | |
| Al Khas et al. | SHA-512 based wireless authentication scheme for smart battery management systems | |
| US10613963B2 (en) | Intelligent packet analyzer circuits, systems, and methods | |
| CN109995548B (en) | Device management method and system, data transmission method and system and terminal device | |
| CN102298112B (en) | The method of testing of a kind of PLD and system | |
| CN114417261A (en) | Device and method for verifying Hash algorithm | |
| WO2015131697A1 (en) | Method and apparatus for multiplex-frame random data verification | |
| CN110417567A (en) | A kind of configuration method and device of internet of things equipment | |
| JP6987303B2 (en) | Secure communication device, secure communication system, secure communication method, and secure communication program | |
| CN110572296B (en) | Internet of things terminal equipment communication protocol consistency safety detection method | |
| CN110022178B (en) | Detection circuit and detection method of WiFi module | |
| CN115526142A (en) | Ethernet speed reduction method, system, medium and FPGA (field programmable Gate array) verification platform | |
| CN105190637A (en) | Software security detection method, apparatus and device | |
| CN113872826B (en) | Network card port stability testing method, system, terminal and storage medium | |
| JP6992309B2 (en) | Transmitter, receiver, and communication method | |
| Goel et al. | UVM based controller area network verification IP (VIP) | |
| CN115509917A (en) | Method, system, equipment and storage medium for verifying encryption and decryption algorithm | |
| CN111026579B (en) | Verification method and device for data error detection capability, terminal equipment and medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |