CN114415972B

CN114415972B - Data processing method and device of SSD, storage medium and SSD device

Info

Publication number: CN114415972B
Application number: CN202210309239.1A
Authority: CN
Inventors: 刘鹏; 薛红军; 孙丽华; 孟欣
Original assignee: Beijing Dera Technology Co Ltd
Current assignee: Beijing Dera Technology Co Ltd
Priority date: 2022-03-28
Filing date: 2022-03-28
Publication date: 2022-07-15
Anticipated expiration: 2042-03-28
Also published as: CN114415972A

Abstract

The invention relates to the technical field of data storage, and provides a data processing method and device of an SSD, a storage medium and SSD equipment, wherein the method comprises the following steps: when user data is written, calculating a target physical address corresponding to the target logical address according to a preset address mapping relation, wherein the physical addresses having the mapping relation with the continuously distributed logical addresses are distributed on the wafer blocks in different ONFI channels; and putting the written data into a cache position corresponding to the target physical address in the write cache, and respectively writing the data to be written into the wafer blocks in different ONFI channels in the SSD according to the target physical address. The invention changes the arithmetic logic of the write data through FTL management, can improve the IO performance of SSD equipment by improving the concurrency on nand flash memory media on the premise of not influencing the write performance, reduces the total read delay and improves the random read performance of the large data.

Description

Data processing method and device of SSD, storage medium and SSD device

Technical Field

The present invention relates to the field of data storage technologies, and in particular, to a method and an apparatus for processing SSD data, a storage medium, and an SSD device.

Background

The read-write performance of a Solid State Disk (SSD) is mainly determined by several factors, such as the front-end bus transmission rate, firmware processing, and flash data transmission. Compared with a mechanical hard disk, the solid state disk has the advantages of high read-write performance, small volume, strong shock resistance and the like. However, due to the change of access and update modes of nand Flash, it is necessary to introduce an FTL (Flash Translation Layer) to manage the read/write/erase behavior of the Flash memory so as to be compatible with the previous memory access interface, and the management and scheduling of the FTL become the key factors for efficient use of the Flash memory storage medium.

Currently, research work and practical application aiming at improving the performance of flash memory devices by the management and scheduling of FTLs are mainly divided into the following: the verification scheme is optimized, write amplification is reduced, and concurrency is improved.

In order to meet the requirements of large-capacity and high-performance storage application scenarios, the solid state disk usually stores data in a distributed form of a multi-channel flash memory array at the present stage, as shown in fig. 1, an ONFI bus is a channel for data transmission between a flash memory medium and an SSD controller, and data transmission between the ONFI channels can be performed in parallel. To improve performance, increase error correction capability, and reduce management overhead, multiple flash media share a flash data transfer bus (ONFI bus). The flash memories are usually formed in a group of array blocks (raid groups) formed by multiple wafers (die), that is, multiple wafer blocks (die blocks) are formed into one array block (raid group block). The wafer tiles within each array block are evenly distributed to each ONFI bus channel to achieve maximum back-end transmission bandwidth. For example, 8 wafer blocks are combined into an array block as shown in fig. 2.

In the existing solid state disk design, when user data is written, a controller writes received data into a continuous write buffer (write buffer) first, and when the write buffer is full, the whole write buffer data is written into nand through an ONFI bus. The specific write cache fill sequence is as follows: first 4k user data fills a first 4k write buffer of a first wafer block; the second 4k user data then fills the second 4k write buffer of the first wafer block; filling a third 4k write cache of the first wafer block with third 4k user data; the fourth 4k user data fills the fourth 4k write buffer of the first wafer block. According to such a filling sequence, after the last 4k write buffer of the first wafer block is filled by the user, the next 4k user data fills the first 4k write buffer of the second wafer block in that order until the entire array group page write buffer is filled, and then writes this data into the flash media.

When writing to nand, writing to each physical block of array block RG block in turn according to the arrangement sequence in the writer buffer. After the large block data (e.g., block size =32kB, occupying 8 logical block units lba) is randomly written, the layout of the data of each block size in nand is as shown in fig. 3. During the subsequent 32kB random reading, since the data of each block size is in the same physical die block, taking nand particle as magnesium light B16 and ONFI bus speed as 533MT/s as an example, the read delay at the back end is equal to the busy time (about 68 microseconds) of one multi-page read (multi-plane read) plus the transmission time (about 64 microseconds) of 32kB data on an ONFI bus, so that the read delay at the flash media end is relatively large (about 132 microseconds).

Therefore, in the prior art, as the user data are continuously distributed in the flash memory according to the die block, after the large blocks of data are randomly written, each large block of data is in the same die block in the same channel. Therefore, during the subsequent random reading of the data block with the same size, the busy time of multi-page (multiplane) reading and the data transmission time on the ONFI bus are both longer, the random reading delay is increased, and the random reading performance of the large data block is reduced.

Disclosure of Invention

In view of the above problems, the present invention has been made to provide a data processing method, apparatus, storage medium, and SSD device of the SSD that overcome or at least partially solve the above problems.

In one aspect of the present invention, a data processing method of an SSD is provided, the method comprising:

when user data is written, calculating a target physical address corresponding to a target logical address according to a preset address mapping relation, wherein the mapping relation between the logical address and the physical address is recorded in the address mapping relation, and the physical addresses having the mapping relation with the continuously distributed logical addresses are distributed on the wafer blocks in different ONFI channels;

and respectively writing the data to be written into the wafer blocks in different ONFI channels in the SSD according to the target physical address.

Further, the method further comprises:

and when the SSD is electrified and initialized, generating the address mapping relation according to preset control parameters, wherein the control parameters are used for controlling the number of data blocks which are continuously filled with preset data capacity on each wafer block.

Further, the control parameters are adjusted according to the data size of the data to be written, the nand type and/or the load intensity of the current SSD.

Further, the data capacity of the data block is set according to the data capacity of snapshot reading supported by the nand type of the current SSD.

Further, the data capacity of the data block is smaller than the data capacity of one wafer page, such as 4kB or 8 kB.

Further, the method further comprises:

when user data reading is carried out, calculating a target physical address corresponding to the target logical address according to a preset address mapping relation;

and reading the target physical addresses distributed on different wafer blocks through different ONFI channels to acquire corresponding user data.

In a second aspect, the present invention further provides a data processing apparatus of an SSD, the apparatus including:

the table look-up module is used for calculating a target physical address corresponding to a target logical address according to a preset address mapping relation when user data is written, wherein the address mapping relation records the mapping relation from the logical address to the physical address, and the physical addresses having the mapping relation with the continuously distributed logical addresses are distributed on wafer blocks in different ONFI channels;

and the writing processing module is used for respectively writing the data to be written into the wafer blocks in different ONFI channels in the SSD according to the target physical address.

Further, the table look-up module is further configured to calculate a target physical address corresponding to the target logical address according to a preset address mapping relationship when reading the user data;

the device further comprises:

and the read processing module is used for concurrently reading the target physical addresses distributed on different wafer blocks through different ONFI channels and acquiring corresponding user data.

In a third aspect, the present invention also provides a computer readable storage medium, on which a computer program is stored, which computer program, when executed by a processor, implements the steps of the data processing method of the SSD as above.

In a fourth aspect, the present invention also provides an SSD device comprising a storage controller, the storage controller comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of the data processing method of the SSD as above when executing the computer program.

According to the SSD data processing method and device, the storage medium and the SSD device, the arithmetic logic of the write data is changed through FTL management, the IO performance of the SSD device can be improved through a mode of improving the concurrency on a nand flash memory medium on the premise of not influencing the write performance, the total read delay is reduced, and the random read performance of the large data blocks is improved.

The above description is only an overview of the technical solutions of the present invention, and the present invention can be implemented in accordance with the content of the description so as to make the technical means of the present invention more clearly understood, and the above and other objects, features, and advantages of the present invention will be more clearly understood.

Drawings

Various additional advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:

FIG. 1 is a schematic diagram of a distributed data storage method of a conventional multi-channel flash memory array of a solid state disk;

fig. 2 is a schematic structural diagram of an array block composed of 8 wafer blocks;

FIG. 3 is a schematic layout diagram of a large block of data written in nand in a conventional SSD data processing method;

fig. 4 is a flowchart of a method for implementing logical space operation based on NVMe SSD protocol in the prior art;

fig. 5 is a schematic layout diagram of a large block of data written in the data processing method of the SSD according to the embodiment of the present invention in nand;

fig. 6 is a block diagram of a data processing apparatus of an SSD according to an embodiment of the invention.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Fig. 4 schematically shows a flowchart of a data processing method of the SSD of one embodiment of the present invention. Referring to fig. 4, the data processing method of the SSD according to the embodiment of the present invention specifically includes the following steps:

s11, when writing user data, calculating a target physical address corresponding to the target logical address according to a preset address mapping relation, wherein the address mapping relation records the mapping relation from the logical address to the physical address, and the physical addresses having the mapping relation with the continuously distributed logical addresses are distributed on the wafer blocks in different ONFI channels.

The target logical address is a logical address of data to be written, and the data to be written is large block data, for example, a data block with block size =32 kB.

According to the method, the received user data is mapped to different positions of continuous write buffers according to a certain rule through a new mapping algorithm of pba (physical block address) corresponding to lba (logical address), so that the data to be written, namely large blocks of data, can fall into different channels and wafer blocks at the same time when being finally written into a flash memory medium. Specifically, the principle of the mapping algorithm is as follows: the first lba in the large data block maps to the first pba of lane 1 wafer block 1, the second lba maps to the second pba of lane 1 wafer block 1, the third lba maps to the first pba of lane 2 wafer block 1, the fourth lba maps to the second pba of lane 2 wafer block 1, and so on.

And S12, respectively writing the data to be written into the wafer blocks in different ONFI channels in the SSD according to the target physical address.

In the embodiment of the invention, after the target physical address of the data to be written is determined according to the address mapping relation, the written data is firstly placed in the cache position corresponding to the target physical address in the write cache, and then the data is respectively written into the wafer blocks in different ONFI channels in the SSD from the write cache.

Specifically, the distribution in the flash memory medium can be determined according to the data size of the data to be written, so that the data of the same large data block is distributed on wafer blocks in different ONFI channels.

According to the data processing method of the SSD, provided by the embodiment of the invention, the algorithm logic of data writing is changed through FTL management, the IO performance of the SSD equipment can be improved by a mode of improving concurrency on a nand flash memory medium on the premise of not influencing the writing performance, the total reading delay is reduced, and the random reading performance of large data blocks is improved.

In the embodiment of the present invention, based on different implementation manners of user data writing operations, the corresponding data reading implementation manner is specifically as follows:

when user data is read, calculating a target physical address corresponding to the target logical address according to a preset address mapping relation;

According to the embodiment of the invention, by changing the arithmetic logic of the write data, the total read delay can be reduced on the premise of not influencing the write performance, and the read performance under the application scene is improved.

In the embodiment of the invention, when the SSD is powered on and initialized, the address mapping relationship is generated according to the preset control parameter, and the control parameter is used for controlling the number of data blocks which are continuously filled with the preset data capacity each time on each wafer block. Specifically, the control parameters are adjusted according to the data size of the data to be written, the nand type and/or the load intensity of the current SSD.

The data capacity of the data block can be set according to the data capacity of snapshot reading (i.e. snap read operation) supported by the nand type of the current SSD. Optionally, the data capacity of the data block is typically a fraction of a wafer page size, typically 4kB or 8 kB.

In this embodiment, the data capacity of the data block is 4kB for illustration, and after controlling the continuous filling of several 4k on each wafer block by the control parameter, the next wafer block is skipped to fill. According to the setting of the parameter, different layout modes of the large block data stored in the flash memory medium can be adjusted, the application scenes of the data size block size, the nand type and the workload strength of the large block data can be adjusted, and the use is flexible. In one embodiment, if the block size is 16kB and the flash memory granules are magnesium light B16, which supports snap read operation of 8kB stored data, the parameter M can be set to 2, i.e. each wafer block is filled with 2 consecutive 4k data during user data writing, so that when randomly reading the 16kB block data, the 8k data can be read by the wafer of each channel only requiring one snap read. If the parameter M is 2, the 8k data can be read out only by two snap read operations of the wafer of each ONFI channel, so that the reading delay is relatively large. The M parameter may be adjusted to 1, i.e., 16kB of data is distributed among the wafers on the 4 ONFI channels, each wafer containing only 4kB of data therein. Therefore, the rear-end delay of randomly reading the 16kB data is only one snap read time in each channel and the ONFI bus transmission time of 4kB data, and the optimal reading performance can be achieved.

In a specific embodiment of the present invention, in the process of writing user data, when the user data is stored in the write cache, the first 4k user data fills the first 4k write cache of the first wafer block; the second 4k user data then fills the second 4k write buffer of the first wafer block; skipping the third 4k user data from the write cache behind the first wafer block to fill the first 4k write cache of the second wafer block; the fourth 4k user data fills the second 4k write buffer of the second wafer block. According to the filling sequence, after the second 4k write cache of the last wafer block of an array group page (raid group page) is filled by a user, the next 4k user data fills the third 4k write cache of the first wafer block, and the data is written into the flash memory medium in this sequence until the entire array group page write cache is filled.

After the user data is written into the flash memory medium according to the above filling manner, the large block of data is in such layout distribution in the flash memory as shown in fig. 5:

under the distribution of the data layout, each large block of data is split into 4 wafer blocks in 4 channels, so that the concurrency of nand operation during reading data is improved. Specifically, taking the nand particle as the magnesium light B16 and the ONFI bus speed as 533MT/s as an example, the read delay is changed to be the busy time of a snap read (about 51 microseconds), and the read delay of the flash memory medium end is only about 67 microseconds by adding the ONFI bus transmission time of 8kB (about 16 microseconds), so that the total read delay is greatly reduced compared with the previous multiplane busy time and the ONFI transmission time of 32kB, and the read performance under the application scenario is improved.

For simplicity of explanation, the method embodiments are described as a series of acts or combinations, but those skilled in the art will appreciate that the embodiments are not limited by the order of acts described, as some steps may occur in other orders or concurrently with other steps in accordance with the embodiments of the invention. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred and that no particular act is required to implement the invention.

Fig. 6 schematically shows a configuration diagram of a data processing apparatus of an SSD according to an embodiment of the present invention. Referring to fig. 6, the data processing apparatus of the SSD according to the embodiment of the present invention specifically includes a table lookup module 201 and a write processing module 202, wherein:

the table look-up module 201 is configured to calculate a target physical address corresponding to a target logical address according to a preset address mapping relationship when user data is written, where the address mapping relationship records a mapping relationship from a logical address to a physical address, and physical addresses having a mapping relationship with continuously distributed logical addresses are distributed on wafer blocks in different ONFI channels;

and the write processing module 202 is configured to write the data to be written into the wafer blocks in different ONFI channels in the SSD according to the target physical address.

In this embodiment of the present invention, the apparatus further includes a configuration module not shown in the drawing, where the configuration module is configured to generate the address mapping relationship according to a preset control parameter when the SSD is powered on and initialized, and the control parameter is used to control the number of data blocks of a preset data size that are continuously filled on each wafer block each time.

In this embodiment of the present invention, the table look-up module 202 is further configured to calculate a target physical address corresponding to the target logical address according to a preset address mapping relationship when reading user data;

the device also comprises a reading processing module which is not shown in the attached drawing, wherein the reading processing module is used for concurrently reading the target physical addresses distributed on different wafer blocks through different ONFI channels and acquiring corresponding user data.

For the apparatus embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and reference may be made to the partial description of the method embodiment for relevant points.

Furthermore, an embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored, where the program, when executed by a processor, implements the steps of the data processing method of the SSD as described above.

In this embodiment, if the data processing method of the SSD is implemented in the form of a software functional unit and sold or used as an independent product, the data processing method may be stored in a computer-readable storage medium. Based on such understanding, all or part of the flow of the method according to the embodiments of the present invention may also be implemented by a computer program, which may be stored in a computer-readable storage medium, and when the computer program is executed by a processor, the steps of the method embodiments may be implemented. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, U.S. disk, removable hard disk, magnetic diskette, optical disk, computer Memory, Read-Only Memory (ROM), Random Access Memory (RAM), electrical carrier wave signal, telecommunications signal, and software distribution medium, etc. It should be noted that the computer readable medium may contain content that is subject to appropriate increase or decrease as required by legislation and patent practice in jurisdictions, for example, in some jurisdictions, computer readable media does not include electrical carrier signals and telecommunications signals as is required by legislation and patent practice.

In addition, an embodiment of the present invention further provides an SSD device, which includes a storage controller, where the storage controller includes a memory, a processor, and a computer program stored on the memory and executable on the processor, and when the processor executes the program, the steps of the data processing method of the SSD are implemented. For example, steps S11 to S13 shown in FIG. 4. Alternatively, the processor implements the functions of each module/unit in the data processing apparatus embodiment of the SSD when executing the computer program, for example, the logical address obtaining module 201, the table lookup module 202, and the write processing module 203 shown in fig. 6.

According to the SSD data processing method and device, the storage medium and the SSD device, the algorithm logic of data writing is changed through FTL management, the IO performance of the SSD device can be improved through a mode of improving concurrency on a nand flash memory medium on the premise of not influencing the writing performance, the total reading delay is reduced, and the random reading performance of large data blocks is improved.

Those skilled in the art will appreciate that while some embodiments herein include some features included in other embodiments, rather than others, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments. For example, any of the claimed embodiments may be used in any combination.

Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims

1. A method of data processing of an SSD, the method comprising:

when user data is written, calculating a target physical address corresponding to a target logical address according to a preset address mapping relation, wherein the address mapping relation records the mapping relation between the logical address and the physical address, and the physical addresses having the mapping relation with the continuously distributed logical addresses are distributed on wafer blocks in different ONFI channels;

respectively writing data to be written into wafer blocks in different ONFI channels in the SSD according to the target physical address;

when the SSD is electrified and initialized, the address mapping relation is generated according to preset control parameters, and the control parameters are used for controlling the number of data blocks with preset data capacity continuously filled on each wafer block each time so as to adjust different distribution modes of data to be written stored in a flash memory medium through setting of the control parameters;

and the control parameters are adjusted according to the data size of the data to be written, the nand type and/or the load intensity of the current SSD, so that the data to be written is written into different ONFI channels and wafer blocks in the SSD at the same time.

2. The method of claim 1, wherein the data capacity of the data block is set according to a data capacity of a snapshot read supported by a nand type of a current SSD.

3. The method of claim 1, wherein the data capacity of the data block is less than the data capacity of one wafer page.

4. The method according to any one of claims 1-3, further comprising:

and concurrently reading target physical addresses distributed on different wafer blocks through different ONFI channels to acquire corresponding user data.

5. A data processing apparatus of an SSD, characterized in that the apparatus comprises:

the write processing module is used for respectively writing the data to be written into the wafer blocks in different ONFI channels in the SSD according to the target physical address;

the device also comprises a configuration module, a storage module and a processing module, wherein the configuration module is used for generating the address mapping relation according to a preset control parameter when the SSD is electrified and initialized, the control parameter is used for controlling the number of data blocks with preset data capacity continuously filled on each wafer block at each time, and different distribution modes of data to be written stored in the flash memory medium are adjusted through setting the control parameter; and the control parameters are adjusted according to the data size of the data to be written, the nand type and/or the load intensity of the current SSD, so that the data to be written is written into different ONFI channels and wafer blocks in the SSD at the same time.

6. The apparatus of claim 5, wherein the table lookup module is further configured to calculate a target physical address corresponding to the target logical address according to a preset address mapping relationship when reading user data;

the device further comprises:

7. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 4.

8. An SSD device, comprising a storage controller comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor when executing the computer program implementing the steps of the method of any of claims 1 to 4.