CN114415066A - Circuit system for detecting power failure and detection method thereof - Google Patents
Circuit system for detecting power failure and detection method thereof Download PDFInfo
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- CN114415066A CN114415066A CN202210317978.5A CN202210317978A CN114415066A CN 114415066 A CN114415066 A CN 114415066A CN 202210317978 A CN202210317978 A CN 202210317978A CN 114415066 A CN114415066 A CN 114415066A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
- G01R31/54—Testing for continuity
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
- G01R29/16—Measuring asymmetry of polyphase networks
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
- G01R31/58—Testing of lines, cables or conductors
Abstract
The invention relates to a circuit system for detecting power failure, which comprises a sampling circuit, wherein the sampling circuit comprises: a first line including a first input coupled to a power supply L1; a second line including a second input coupled to a power supply L2; a third line comprising a third input coupled to a power supply L3; a fourth line comprising a fourth input coupled to a power supply N; wherein one of the first line, the second line, and the third line is coupled with the other two lines and the fourth line.
Description
Technical Field
The present invention relates to the field of circuits, and more particularly, to a circuit system for detecting a power failure and a detection method thereof.
Background
With the monitor, a failure of the power supply system can be detected. In a three-phase four-wire system power supply system, the neutral wire N is usually connected directly to the ground of the sampling circuit of the monitor, or via a resistive sampling network, in order to detect whether the N-phase is disconnected. Through the resistance voltage division loop, the microprocessor calculates the electrical parameters of L1, L2, L3 and N phases, restores the real voltage and further judges various faults.
When three phases are electrically balanced, a non-zero non-standard small signal can be detected on the N-phase line to the ground under the condition that the N phases are normally connected and the N phases are disconnected. When three-phase electricity is unbalanced, if N phases are normally connected, a non-zero non-standard large signal can be detected on a line of N phases to the ground; if N phase is disconnected, a non-zero, non-standard small signal can be detected on the line with N phase to ground. The common processing mode of the microprocessor is to perform basic filtering processing on the signal to obtain a voltage signal value on the N phase, and then perform disconnection detection on the N phase according to the voltage value of the N phase.
The method for detecting the power failure cannot judge whether the N phase is broken when the three-phase electricity is balanced, and cannot accurately judge whether the N phase is broken when the three-phase electricity is unbalanced.
Disclosure of Invention
The invention relates to a circuit system for detecting power failure, which comprises a sampling circuit, wherein the sampling circuit comprises: a first line including a first input coupled to a power supply L1; a second line including a second input coupled to a power supply L2; a third line comprising a third input coupled to a power supply L3; a fourth line comprising a fourth input coupled to a power supply N; wherein one of the first line, the second line, and the third line is coupled with the other two lines and the fourth line.
The circuit system as described above, wherein the couplings of the one line with the fourth line and the other two lines are respectively coupled via resistances.
According to the circuit system, the resistors comprise resistors with the resistance value of 2-4K.
In the circuit system described above, the other two lines of the first line, the second line, and the third line, and the fourth line include resistors therein, respectively.
The circuit system as described above, the resistor includes a resistor having a resistance value of 0.5 to 1.5 mega ohms.
In the above circuit system, the resistor comprises a precision resistor.
As with the circuit system described above, the first line includes the first output terminal S1, the second line includes the second output terminal S2, the third line includes the third output terminal S3, and the fourth line includes the fourth output terminal Sn.
The circuitry as described above, the circuitry further comprising a processor configured to: receiving signals from one or more of the outputs; and processing and analyzing the received signals.
The circuitry as described above, the processor configured to: receiving a voltage signal from the fourth output terminal Sn; and judging whether the N phases are disconnected or not based on the received voltage signals.
The circuitry as described above, the processor further configured to: if the voltage signal received from the fourth output end Sn is a non-zero non-standard small signal, determining that the N phases are disconnected; otherwise, determining that the N phases are normally connected.
The circuitry as described above, the processor further configured to: and processing the voltage signal according to a half-wave signal, and determining the normal connection of the N phases when the half-wave signal is obtained through processing.
The circuitry as described above, the processor being further configured to calculate the effective value of the N-phase voltage based on the following equation:
wherein SnxRepresents the N-phase sampled voltage measured from the fourth output terminal Sn, and m represents the number of voltage acquisitions.
The circuitry as described above, the circuitry configured to at least one of:
a) the first line is coupled to the fourth line, the circuitry configured to: a line voltage U21 is detected at the second output terminal S2, a line voltage U31 is detected at the third output terminal S3, and a phase voltage U1 is detected at the fourth output terminal Sn;
b) the second line is coupled to the fourth line, the circuitry configured to: a line voltage U12 is detected at the first output terminal S1, a line voltage U32 is detected at the third output terminal S3, and a phase voltage U2 is detected at the fourth output terminal Sn; or
c) The third line is coupled to the fourth line, the circuitry configured to: a line voltage U13 is detected at the first output S1, a line voltage U23 is detected at the second output S3, and a phase voltage U3 is detected at the fourth output Sn.
The circuitry as described above, the processor configured to accordingly perform at least one of:
a) when the first line is coupled to the fourth line, the phase voltage U1 collected at the fourth output end Sn is used as a reference ground signal, and a line voltage U23 and phase voltages U2 and U3 are calculated based on voltages U31, U21 and U1;
b) when the second line is coupled to the fourth line, the phase voltage U2 collected at the fourth output end Sn is used as a reference ground signal, and a line voltage U31 and phase voltages U3 and U1 are calculated based on voltages U12, U32 and U2; or
c) When the third line is coupled to the fourth line, the phase voltage U3 collected at the fourth output terminal Sn is used as a reference ground signal, and a line voltage U12 and phase voltages U1 and U2 are calculated based on the voltages U23, U13 and U3.
The circuitry as described above, the processor further configured to: determining a three-phase power failure fault and/or a three-phase unbalance fault based on the voltages obtained from a), b) or c).
As with the circuitry described above, the sampling circuit and the processor are disposed on the same printed circuit board.
The circuitry of above, the printed circuit board further comprising a rectifying and filtering circuit disposed between the sampling circuit and the processor.
The circuitry as described above, further comprising a display screen configured to display one or more of the respective fault, measured parameter value, calculated parameter value based on the fault detection result determined by the processor.
The circuitry as described above, the processor further configured to: controlling an action of a relay for controlling on/off of the power supply or a device connected to the power supply based on a fault detection result determined by a processor.
The invention also relates to a detection method for detecting power failure, comprising the following steps: coupling L1, L2, L3, N, respectively, of a power supply to respective inputs of a sampling circuit of a circuitry, wherein the sampling circuit comprises: a first input terminal of a first line, a second input terminal of a second line, a third input terminal of a third line, and a fourth input terminal of a fourth line coupled to power sources L1, L2, L3, N, respectively, and wherein one of the first line, the second line, and the third line is coupled to the other two lines and the fourth line; receiving, by a processor of the circuitry, signals from one or more of the outputs of the lines; and determining, by the processor, a state of the power source based on the signal.
The method as described above, further comprising: receiving, by the processor, a signal from a fourth output terminal Sn of the fourth line; and determining, by the processor, whether the N-phase is disconnected based on a signal from the fourth output terminal Sn.
The method as described above, further comprising: receiving, by the processor, voltage signals from the outputs of the other two lines and the fourth line; taking a voltage signal from a fourth output terminal Sn of the fourth line as a reference ground signal by the processor; calculating, by the processor, other line voltages and phase voltages based on the reference ground signal and voltage signals from the outputs of the two other lines; and determining, by the processor, a three-phase outage fault and/or a three-phase imbalance fault based on the calculation result.
Drawings
FIG. 1A is a schematic diagram of a sampling circuit of circuitry for detecting a power failure, according to one embodiment of the invention;
FIG. 1B is a schematic diagram of a sampling circuit of circuitry for detecting a power failure according to another embodiment of the invention;
FIG. 1C is a schematic diagram of a sampling circuit of circuitry for detecting a power failure according to yet another embodiment of the invention; FIG. 2 is a signal processing flow diagram of circuitry for detecting a power failure according to one embodiment of the invention;
fig. 3 is an N-phase half-wave signal obtained in a case where N-phases are normally connected when three-phase power is unbalanced according to an embodiment of the present invention; and
fig. 4 is an N-phase signal obtained in the case where N-phase is disconnected when three-phase power is unbalanced according to an embodiment of the present invention.
Detailed Description
The following detailed description refers to the accompanying drawings. The drawings show, by way of illustration, specific embodiments in which the claimed subject matter may be practiced. It is to be understood that the following detailed description is intended for purposes of illustration, and is not to be construed as limiting the invention; those skilled in the art, having the benefit of this disclosure, may effect numerous modifications thereto and changes may be made without departing from the scope and spirit of the claimed subject matter.
In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of various described embodiments. It will be apparent, however, to one skilled in the art that the various embodiments described may be practiced without these specific details. Unless defined otherwise, technical and scientific terms used herein shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. For example, the term "coupled" may include an electrical connection or contact, either direct or indirect.
The terms "first," "second," and the like in the description and in the claims of the present application do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. An embodiment is an example implementation or example. Reference in the specification to "an embodiment," "one embodiment," "some embodiments," "various embodiments," or "other embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments, of the technology. The various appearances "an embodiment," "one embodiment," or "some embodiments" are not necessarily all referring to the same embodiments. Elements or aspects from one embodiment may be combined with elements or aspects of another embodiment.
FIG. 1A is a schematic diagram of a sampling circuit of circuitry for detecting a power failure, according to one embodiment of the invention. The sampling circuit may include four lines that may be coupled to L1, L2, L3, and N, respectively, of the power supply. For example, the sampling circuit may include: a first line, which may include a first input a1 coupled to a power supply L1; a second line, which may include a second input a2 coupled to a power supply L2; a third line, which may include a third input a3 coupled to a power supply L3; a fourth line, which may include a fourth input a4 coupled to the power supply N. In a preferred embodiment, these inputs a1, a1, a3, a4 may be configured as respective terminals of a circuit system. The L1, L2, L3 and N phases of the power supply or the device to be monitored can be coupled with the respective terminals of the circuit system of the present invention, so that the circuit system of the present invention can be used for rapid fault detection of the accessed power supply or device.
Further, in an embodiment of the present invention, the first line may include a first output terminal S1, the second line may include a second output terminal S2, the third line may include a third output terminal S3, and the fourth line may include a fourth output terminal Sn.
In an embodiment of the present invention, one of the first line, the second line, and the third line may be provided to be coupled with the other two lines and the fourth line. For example, and by way of one example and not limitation, fig. 1A illustrates one implementation of such a circuit arrangement, wherein the second line (i.e., the sampling line coupled to L2) is coupled to the fourth line (i.e., the sampling line coupled to N). The second line may also be coupled to two other lines, namely the first line and the third line. As an example, fig. 1A schematically illustrates that the node c1 of the first line may be coupled with the node c2 of the second line, the node c3 of the third line may be coupled with the node c2 of the second line, and further, the second line may be coupled with the node c4 of the fourth line. It is to be understood that the above coupling points are merely exemplary and that coupling points at other locations may be configured in various lines without departing from the spirit of the present invention.
Preferably, one or more of the various lines of the sampling circuit may include a resistor to better enable the measurement of the parameter. For example, in the exemplary embodiment of fig. 1A, the first line, the third line, and the fourth line may include resistors R1, R3, and Rn, respectively. The resistance values of these resistors can be configured according to the voltage magnitude to be measured. For example, as one non-limiting example, the circuitry of the present invention may preferably be configured to measure line voltages in the voltage range between 160V-690V, inclusive. To enable measurement of the maximum line voltage 690V, the resistance values of R1, R3, and Rn, respectively, may preferably be configured as a resistor set comprising 4-5 resistors in series, wherein each resistor in the resistor set may assume any resistance value between about 130K and about 300K, and each resistor may have a power of about 0.25W. Thus, in this exemplary configuration, each of R1, R3, and Rn may have a resistance value of about 0.5-1.5 megaohms.
Further preferably, the second line and the fourth line and the first and third lines may be coupled via resistors, respectively. For example, fig. 1A schematically illustrates that node c1 of the first line may preferably be coupled to node c2 of the second line through resistor R12, node c3 of the third line may preferably be coupled to node c2 of the second line through resistor R32, and further, the second line may preferably be coupled to node c4 of the fourth line through resistor Rn 2. In a preferred embodiment of the present invention, the resistance values of R12, R32 and Rn2 may be set to be in the range of 2 to 4K, respectively.
The above resistance may include a conventional resistance. In a more preferred embodiment, the above resistor can be a precision resistor to improve the measurement accuracy. It is understood that the term "precision resistor" as used herein may have the general definition of the parameters of "precision resistor" in the art.
One non-limiting example of a sampling circuit is shown above, namely the second line of the sampling circuit coupled to L2 is coupled to the fourth line coupled to N. However, the present invention is not limited thereto. In an alternative embodiment, the first line coupled with L1 or the third line coupled with L3 may also be coupled to the fourth line coupled with N. For example, fig. 1B and 1C illustrate these two alternative embodiments, respectively. In the embodiment of fig. 1B, the first line coupled with L1 may be coupled to the fourth line coupled with N. Preferably, as shown in fig. 1B, the coupling of the second line, the third line, and the fourth line to the first line may be coupled via resistors R21, R31, and Rn1, respectively. Further, preferably, as shown in fig. 1B, the resistors R2, R3, and Rn may be included in the second wiring, the third wiring, and the fourth wiring, respectively. In the embodiment of fig. 1C, the third line coupled with L3 may be coupled to the fourth line coupled with N. Similarly, in a preferred embodiment, as shown in fig. 1C, the coupling of the first, second, and fourth lines to the third line may be via resistors R13, R23, and Rn3, respectively. Further, preferably, as shown in fig. 1C, resistors R1, R2, and Rn may be included in the first line, the second line, and the fourth line, respectively. Accordingly, other portions of the sampling circuit may be configured in a manner similar to that of fig. 1A, and will not be described in detail herein.
As shown in connection with fig. 2, the circuitry of the present invention may further include a processor 203. The processor 203 may be configured to receive signals from one or more of the above-mentioned outputs and process the received signals. Further, the processor 203 may determine the state of the power supply based on the processing and analysis of the signal. The processor 203 may preferably comprise a microprocessor.
As an embodiment, the processor 203 may be configured to receive a voltage signal from the fourth output terminal Sn, and determine whether the N-phase is disconnected based on the received voltage signal. More specifically, in any one of the three configurations of fig. 1A to 1C, if the voltage signal received by the processor 203 from the fourth output terminal Sn is a non-zero, non-standard small signal, it may be determined that the N-phase line is disconnected; otherwise, the N-phase normal connection is determined to be not broken. As shown in fig. 4, a "non-zero, non-target small signal" as described herein may be a clutter that is unrecognizable without a particular waveform shape. The actual size of the "non-zero, non-target small signal" may be related to the size of the input signal. For example, as an illustrative example, if the input voltage is 100V, this signal may be on the order of a few millivolts, and if the input voltage is 690V, this signal may be on the order of a few tens of millivolts. In general, in the case where the three-phase voltage is a sine wave, such a "non-zero non-standard small signal" can be easily distinguished from a sine signal.
In a preferred embodiment, the voltage signal received from the fourth output terminal Sn may be further processed to confirm whether the N phases are normally connected. For example, in an embodiment of the present invention, the voltage signal received from Sn may be processed as a half-wave signal, and if the half-wave signal is obtained, it is determined that the N-phase normal connection is not disconnected. For example, fig. 3 shows an N-phase half-wave signal obtained in a case where N phases are normally connected when three phases are unbalanced according to one embodiment of the present invention. The scheme of the application connects a line coupled with L2 to a line coupled with N (such as the embodiment of FIG. 1A), and can introduce a half-wave signal into a signal input part of N phases through signal processing, so that whether the N phases are broken can be judged more accurately. Alternatively, the voltage signal received from Sn may be processed as a full-wave signal. The present invention preferably processes the electrical signal received from Sn as a half-wave signal. Compared with full-wave signal processing, half-wave signal processing requires fewer circuit components, so that the circuit can be simplified and the circuit cost can be reduced.
In a further embodiment, the processor 203 may be configured to calculate the effective value of the voltage of the N-phase based on the following formula:
wherein SnxRepresents the N-phase sampled voltage measured from the fourth output terminal Sn, and m represents the number of voltage acquisitions. For example, the N-phase voltage may be sampled at intervals to obtain m sampled voltages. The time interval and the specific number m can be set according to actual needs.
When the three-phase voltage is balanced or unbalanced, when N phases are normally connected, one phase circuit of the three phases is coupled to the N phase circuit, so that a relatively stable half-wave signal is introduced into the N phases, and the normal connection of the N phases can be determined by detecting the half-wave signal in a circuit system; further, the root mean square method (such as the above formula) may be used to calculate the effective value of the N-phase voltage; when N phase is disconnected, only non-0 non-standard small signals can be detected on the N lines to the ground. Therefore, the circuit system and the method can accurately judge whether the N phase is in a normal connection state or a disconnection state no matter when the three-phase voltage is balanced or unbalanced. The above description has been primarily described with respect to the embodiment of FIG. 1A, however, it is to be understood that similar processing may be performed with respect to the embodiments of FIGS. 1B and 1C.
As another example, depending on the specific configuration of the circuit, the processor 203 may additionally receive signals from one or more of the output ports S1, S2, S3. For example, where the first line is coupled to the fourth line, the circuitry may be configured to: the line voltage U21 is detected at the second output S2, the line voltage U31 is detected at the third output S3, and the phase voltage U1 is detected at the fourth output Sn. Where the second line is coupled to the fourth line, the circuitry may be configured to: the line voltage U12 is detected at the first output S1, the line voltage U32 is detected at the third output S3, and the phase voltage U2 is detected at the fourth output Sn. Where the third line is coupled to the fourth line, the circuitry may be configured to: the line voltage U13 is detected at the first output S1, the line voltage U23 is detected at the second output S3, and the phase voltage U3 is detected at the fourth output Sn.
The processor 203 of the circuitry may be configured to accordingly further perform the following:
a) in the case where the first line is coupled to the fourth line, the phase voltage U1 collected at the fourth output terminal Sn is used as a reference ground signal, and the line voltage U23 and the phase voltages U2 and U3 are calculated based on the voltages U31, U21 and U1;
b) in the case where the second line is coupled to the fourth line, the phase voltage U2 collected at the fourth output terminal Sn is taken as a reference ground signal, and the line voltage U31 and the phase voltages U3, U1 are calculated based on the voltages U12, U32, and U2; or
c) In the case where the third line is coupled to the fourth line, the phase voltage U3 picked up at the fourth output terminal Sn is taken as a reference ground signal, and the line voltage U12 and the phase voltages U1, U2 are calculated based on the voltages U23, U13, and U3.
It will be appreciated that the line voltage and phase voltage measured in accordance with the present invention may include their respective magnitudes and angles (e.g., the included angle between them). Other line voltages and phase voltages may be calculated based on their respective magnitudes and angles. It is within the skill of the art to calculate other line voltages and/or phase voltages based on a portion of the line voltages and/or phase voltages. For example, the calculation process may involve vector calculations, fourier calculations, and the like.
The processor 203 of the present invention may be further configured to determine a three-phase outage fault and/or a three-phase imbalance fault based on the voltages calculated in a), b), or c). In the art, this is based on the respective fault determinations that can be made for the line voltage and the phase voltage.
In fig. 1A, the second line is shown as being grounded (or in fig. 1B and 1C, the first line and the third line are shown as being grounded, respectively), however this is only a visual representation. The invention does not actually perform a grounding operation on the second line (or the first line, the third line), but since this line is coupled to the fourth line, and the signal received from the fourth output terminal Sn is taken as a ground reference signal, and further processing is performed on other signals based on the ground reference signal.
FIG. 2 shows a signal processing flow diagram of circuitry for detecting a power failure, according to one embodiment of the invention. For simplicity of description, fig. 2 shows a case where the second line of the sampling circuit 201 is coupled to the fourth line (the embodiment of fig. 1A). However, it may be replaced with the embodiment of fig. 1B or fig. 1C. In addition to the sampling circuit 201 and the processor 203 described above, in a preferred embodiment of the present invention, the circuitry may further include a rectifying-filtering circuit 202 disposed between the sampling circuit 201 and the processor 203. In a preferred embodiment of the invention, the sampling circuit 201, the processor 203 and the rectifying-filtering circuit 202 (optional circuitry, if present) may be provided on the same printed circuit board. The circuitry of the present invention (e.g., on a printed circuit board) may also include a computer-readable medium, which when executed by a processor, causes the processor to perform any one or more of the operations described herein.
As described above, the sampling circuit 201 may collect the corresponding electrical signal according to the actual circuit setup (e.g., the case where the second line is coupled to the fourth line as shown in fig. 2). The acquired signals may then be received by the rectifying and filtering circuit 202 and processed by rectifying and filtering. The processed signal may further be sent to a processor 203. The processor 203 may further perform operations as described above based on the signals to analyze the signals and/or calculate further parameter values. Furthermore, the processor 203 may also determine a fault of the connected circuit/power source to be detected, such as an N-phase line break fault, a three-phase imbalance fault, etc., based on the signal analysis and/or the calculated parameter values.
The invention changes the reference ground inside the circuit. Therefore, whether the N phase is broken or not can be accurately judged no matter the three-phase voltage is balanced or unbalanced. In addition, whether the N phase is disconnected or not can be accurately judged, the relation (such as vector calculation) between the line voltage and the phase voltage is further applied through the improved circuit structure, Fourier calculation is introduced into software, and the three-phase voltage of the system is accurately calculated, so that disconnection faults, three-phase imbalance faults and the like can be further accurately judged. The circuit system of the invention can also control the operation of the relay based on the fault judgment result, for example, when the fault is detected, the relay can be controlled to disconnect the power supply or the equipment connected with the power supply, so that the relay does not work any more. The product of the invention may further comprise a display screen for displaying one or more of the respective parameter values (including the measured parameter values and the calculated parameter values) and the fault results for easy viewing by an operator.
It should be understood that detecting a power failure as described herein may include detecting a power failure directly, or detecting a power failure of a working device connected to a power source indirectly.
The basic concept of the present invention has been described above. It will be apparent to those skilled in the art that the foregoing disclosure is by way of example only, and is not intended to limit the present application. Various modifications, improvements and adaptations to the present application may occur to those skilled in the art, although not explicitly described herein. Such modifications, improvements and adaptations are proposed in the present application and thus fall within the spirit and scope of the embodiments of the present application.
Claims (24)
1. Circuitry for detecting a power failure, comprising a sampling circuit, the sampling circuit comprising:
a first line including a first input coupled to a power supply L1;
a second line including a second input coupled to a power supply L2;
a third line comprising a third input coupled to a power supply L3;
a fourth line comprising a fourth input coupled to a power supply N;
wherein one of the first line, the second line, and the third line is coupled with the other two lines and the fourth line.
2. The circuitry of claim 1, wherein the coupling of the one of the lines to the fourth line and the other two lines is via resistive couplings, respectively.
3. The circuit system of claim 2, wherein the resistor comprises a resistor having a resistance value of 2-4K.
4. The circuit system of claim 1, wherein the other two of the first line, the second line, and the third line, and the fourth line each include a resistor therein.
5. The circuit system of claim 4, wherein the resistor comprises a resistor having a resistance value of 0.5 to 1.5 megaohms.
6. The circuitry of any of claims 2-5, wherein the resistance comprises a precision resistance.
7. The circuitry of any one of claims 1-5,
the first line comprises a first output terminal S1,
the second line comprises a second output terminal S2,
the third circuit includes a third output terminal S3, and
the fourth line includes a fourth output terminal Sn.
8. The circuitry of claim 7, wherein the circuitry further comprises a processor configured for:
receiving signals from one or more of the outputs; and
the received signals are processed and analyzed.
9. The circuitry as recited in claim 8, wherein said processor is configured for:
receiving a voltage signal from the fourth output terminal Sn;
and judging whether the N phases are disconnected or not based on the received voltage signals.
10. The circuitry of claim 9, wherein the processor is further configured for:
if the voltage signal received from the fourth output end Sn is a non-zero non-standard small signal, determining that the N phases are disconnected;
otherwise, determining that the N phases are normally connected.
11. The circuitry of claim 10, wherein the processor is further configured for:
the voltage signal is processed as a half-wave signal, and
and when the half-wave signal is obtained through processing, determining the normal connection of the N phases.
12. The circuitry of claim 11, wherein the processor is further configured to calculate an effective value for an N-phase voltage based on the following equation:
wherein SnxRepresents the N-phase sampled voltage measured from the fourth output terminal Sn, and m represents the number of voltage acquisitions.
13. The circuitry of claim 8, wherein the circuitry is configured to at least one of:
a) the first line is coupled to the fourth line, the circuitry configured to: a line voltage U21 is detected at the second output terminal S2, a line voltage U31 is detected at the third output terminal S3, and a phase voltage U1 is detected at the fourth output terminal Sn;
b) the second line is coupled to the fourth line, the circuitry configured to: a line voltage U12 is detected at the first output terminal S1, a line voltage U32 is detected at the third output terminal S3, and a phase voltage U2 is detected at the fourth output terminal Sn; or
c) The third line is coupled to the fourth line, the circuitry configured to: a line voltage U13 is detected at the first output S1, a line voltage U23 is detected at the second output S3, and a phase voltage U3 is detected at the fourth output Sn.
14. The circuitry of claim 13, wherein the processor is configured to perform at least one of the following accordingly:
a) when the first line is coupled to the fourth line, the phase voltage U1 collected at the fourth output end Sn is used as a reference ground signal, and a line voltage U23 and phase voltages U2 and U3 are calculated based on voltages U31, U21 and U1;
b) when the second line is coupled to the fourth line, the phase voltage U2 collected at the fourth output end Sn is used as a reference ground signal, and a line voltage U31 and phase voltages U3 and U1 are calculated based on voltages U12, U32 and U2; or
c) When the third line is coupled to the fourth line, the phase voltage U3 collected at the fourth output terminal Sn is used as a reference ground signal, and a line voltage U12 and phase voltages U1 and U2 are calculated based on the voltages U23, U13 and U3.
15. The circuitry of claim 14, wherein the processor is further configured for: determining a three-phase power failure fault and/or a three-phase unbalance fault based on the voltages obtained from a), b) or c).
16. The circuitry of claim 8, wherein the sampling circuit and the processor are disposed on the same printed circuit board.
17. The circuitry of claim 16, wherein the printed circuit board further comprises a rectifier filter circuit disposed between the sampling circuit and the processor.
18. The circuitry of claim 9, further comprising a display screen configured to display N disconnect faults based on the N phase disconnect faults determined by the processor.
19. The circuitry of claim 9, wherein the processor is further configured for: controlling an action of a relay for controlling on and off of the power supply or a device connected to the power supply based on the N-phase open circuit fault determined by the processor.
20. The circuitry of claim 15, further comprising a display screen configured to display one or more of the respective fault, measured parameter values, calculated parameter values based on the three-phase outage fault and/or the three-phase imbalance fault determined by the processor.
21. The circuitry of claim 15, wherein the processor is further configured for: controlling an action of a relay for controlling on and off of the power source or a device connected to the power source based on the three-phase power-off fault and/or the three-phase imbalance fault determined by the processor.
22. A detection method for detecting a power failure, comprising:
coupling L1, L2, L3, N, respectively, of a power supply to respective inputs of a sampling circuit of a circuitry, wherein the sampling circuit comprises: a first input terminal of a first line, a second input terminal of a second line, a third input terminal of a third line, and a fourth input terminal of a fourth line coupled to power sources L1, L2, L3, N, respectively, and wherein one of the first line, the second line, and the third line is coupled to the other two lines and the fourth line;
receiving, by a processor of the circuitry, signals from one or more of the outputs of the lines; and
determining, by the processor, a state of the power source based on the signal.
23. The method of claim 22, further comprising:
receiving, by the processor, a signal from a fourth output terminal Sn of the fourth line; and
determining, by the processor, whether the N-phase is disconnected based on a signal from the fourth output terminal Sn.
24. The method of claim 22, further comprising:
receiving, by the processor, voltage signals from the outputs of the other two lines and the fourth line;
taking a voltage signal from a fourth output terminal Sn of the fourth line as a reference ground signal by the processor;
calculating, by the processor, other line voltages and phase voltages based on the reference ground signal and voltage signals from the outputs of the two other lines; and
determining, by the processor, a three-phase outage fault and/or a three-phase imbalance fault based on the calculation result.
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